会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 6. 发明申请
    • FinFET Body Contact Structure
    • FinFET主体接触结构
    • US20070202659A1
    • 2007-08-30
    • US11696331
    • 2007-04-04
    • Richard DonzeKarl EricksonWilliam HovisTerrance KueperJohn SheetsJon Tetzloff
    • Richard DonzeKarl EricksonWilliam HovisTerrance KueperJohn SheetsJon Tetzloff
    • H01L21/76
    • H01L29/785H01L21/84H01L27/1203H01L29/42384H01L29/66795
    • A FinFET body contact structure and a method for creating the FinFET body contact structure are disclosed. The body contact structure comprises a wide fin portion of a semiconductor fin, the wide fin portion having a polysilicon polygon shape formed on a top surface of the wide fin portion. The polysilicon polygon shape has a center area having no polysilicon. FinFETs are formed on two vertical surfaces of the wide fin portion and gates of the FinFETs are coupled to the polysilicon polygon shape. Top surfaces of the wide fin portion and the polysilicon polygon shape are silicided. Silicide bridging is prevented by sidewall spacers. All convex angles on the polysilicon polygon shape are obtuse enough to prevent creation of bridging vertices. The center area is doped of an opposite type from a source and a drain of an associated FinFET.
    • 公开了FinFET体接触结构和用于产生FinFET体接触结构的方法。 本体接触结构包括半导体鳍片的宽鳍片部分,宽鳍片部分形成在宽鳍片部分的顶表面上的多晶硅多边形形状。 多晶硅多晶形状具有不具有多晶硅的中心区域。 FinFET形成在宽鳍片部分的两个垂直表面上,并且FinFET的栅极耦合到多晶硅多边形形状。 宽鳍片部分和多晶硅多边形形状的顶表面被硅化。 通过侧壁间隔物防止硅化物桥接。 多晶硅多边形形状上的所有凸角都足够钝,以防止桥接顶点的产生。 中心区域与相关联的FinFET的源极和漏极相反地掺杂。
    • 8. 发明申请
    • Polysilicon Conductor Width Measurement for 3-Dimensional FETs
    • 三维FET的多晶硅导体宽度测量
    • US20070128740A1
    • 2007-06-07
    • US11670008
    • 2007-02-01
    • Richard DonzeWilliam HovisTerrance KueperJohn SheetsJon Tetzloff
    • Richard DonzeWilliam HovisTerrance KueperJohn SheetsJon Tetzloff
    • H01L21/66
    • H01L27/1203H01L22/34H01L29/785
    • An apparatus and method is disclosed for determining polysilicon conductor width for 3-dimensional field effect transistors (FinFETs). Two or more resistors are constructed using a topology in which polysilicon conductors are formed over a plurality of silicon “fins”. A first resistor has a first line width. A second resistor has a second line width. The second line width is slightly different than the first line width. Advantageously, the first line width is equal to the nominal design width used to make FET gates in the particular semiconductor technology. Resistance measurements of the resistors and subsequent calculations using the resistance measurements are used to determine the actual polysilicon conductor width produced by the semiconductor process. A composite test structure not only allows calculation of the polysilicon conductor width, but provides proof that differences in the widths used in the calculations do not introduce objectionable etching characteristics of the polysilicon conductors.
    • 公开了一种用于确定三维场效应晶体管(FinFET)的多晶硅导体宽度的装置和方法。 使用其中在多个硅“鳍”上形成多晶硅导体的拓扑构造两个或更多个电阻器。 第一电阻器具有第一线宽度。 第二电阻具有第二线宽。 第二行宽度与第一行宽度略有不同。 有利地,第一线宽度等于在特定半导体技术中用于制造FET栅极的标称设计宽度。 电阻的电阻测量和使用电阻测量的随后的计算用于确定由半导体工艺产生的实际多晶硅导体宽度。 复合测试结构不仅允许计算多晶硅导体宽度,而且提供了在计算中使用的宽度差不会引起多晶硅导体的不良刻蚀特性的证据。
    • 9. 发明申请
    • Polysilicon conductor width measurement for 3-dimensional FETs
    • 三维FET的多晶硅导体宽度测量
    • US20060063317A1
    • 2006-03-23
    • US10944622
    • 2004-09-17
    • Richard DonzeWilliam HovisTerrance KueperJohn SheetsJon Tetzloff
    • Richard DonzeWilliam HovisTerrance KueperJohn SheetsJon Tetzloff
    • H01L21/338
    • H01L27/1203H01L22/34H01L29/785
    • An apparatus and method is disclosed for determining polysilicon conductor width for 3-dimensional field effect transistors (FinFETs). Two or more resistors are constructed using a topology in which polysilicon conductors are formed over a plurality of silicon “fins”. A first resistor has a first line width. A second resistor has a second line width. The second line width is slightly different than the first line width. Advantageously, the first line width is equal to the nominal design width used to make FET gates in the particular semiconductor technology. Resistance measurements of the resistors and subsequent calculations using the resistance measurements are used to determine the actual polysilicon conductor width produced by the semiconductor process. A composite test structure not only allows calculation of the polysilicon conductor width, but provides proof that differences in the widths used in the calculations do not introduce objectionable etching characteristics of the polysilicon conductors.
    • 公开了一种用于确定三维场效应晶体管(FinFET)的多晶硅导体宽度的装置和方法。 使用其中在多个硅“鳍”上形成多晶硅导体的拓扑构造两个或更多个电阻器。 第一电阻器具有第一线宽度。 第二电阻具有第二线宽。 第二行宽度与第一行宽度略有不同。 有利地,第一线宽度等于在特定半导体技术中用于制造FET栅极的标称设计宽度。 电阻的电阻测量和使用电阻测量的随后的计算用于确定由半导体工艺产生的实际多晶硅导体宽度。 复合测试结构不仅允许计算多晶硅导体宽度,而且提供了在计算中使用的宽度差不会引起多晶硅导体的不良刻蚀特性的证据。
    • 10. 发明申请
    • Method and apparatus for improving performance margin in logic paths
    • 提高逻辑路径性能余量的方法和装置
    • US20050201188A1
    • 2005-09-15
    • US10798911
    • 2004-03-11
    • Richard DonzeWilliam HovisTerrance KueperJohn SheetsJon Tetzloff
    • Richard DonzeWilliam HovisTerrance KueperJohn SheetsJon Tetzloff
    • G11C7/00
    • G11C5/147G06F1/206G06F1/26G11C7/04G11C11/4074
    • An apparatus and method is disclosed for improving timing margins of logic paths on a semiconductor chip. Typical logic embodiments, such as CMOS (Complementary Metal Oxide Semiconductor), have path delays that become shorter as supply voltage is increased. Embodiments of the present invention store product data on each particular chip. The product data includes, for examples, but not limited to, a voltage range having a low limit voltage and a high limit voltage, a limit temperature, and performance of the particular chip in storage for the particular chip. Each chip has a voltage controller, a timer, and a thermal monitor. The voltage controller communicates with a voltage regulator and dynamically causes a voltage supply coupled to the chip to be as high as possible in the voltage range, subject to the limit temperature.
    • 公开了一种用于改善半导体芯片上的逻辑路径的时序余量的装置和方法。 诸如CMOS(互补金属氧化物半导体)的典型逻辑实施例具有随着电源电压增加而变短的路径延迟。 本发明的实施例将产品数​​据存储在每个特定芯片上。 产品数据包括例如但不限于具有用于特定芯片的存储器中的特定芯片的低限电压和上限电压,极限温度和性能的电压范围。 每个芯片都有一个电压控制器,一个定时器和一个热量监视器。 电压控制器与电压调节器通信,动态地使耦合到芯片的电压在电压范围内尽可能高,受限于极限温度。