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1. 发明授权

US5577078A Edge detector 失效
标题翻译：边缘检测器
公开(公告)号：US5577078A
公开(公告)日：1996-11-19
申请号：US452446
申请日：1995-05-26
申请人： Richard C. Jordan , Robert S. Capowski , Daniel F. Casper , Frank D. Ferraiolo , William C. Laviola , Peter R. Tomaszewski
发明人： Richard C. Jordan , Robert S. Capowski , Daniel F. Casper , Frank D. Ferraiolo , William C. Laviola , Peter R. Tomaszewski
IPC分类号： H03L7/06 , H04L7/033 , H04L7/04 , H04L7/00
CPC分类号： H04L7/0338
摘要： An edge detector has a digital phase locking loop in which one of the signals (e.g., the data signal) is coupled to a delay chain that develops a series of incrementally phase delayed versions of the input. Adjacent phase delayed pairs are selected, one pair at a time, and are compared to the other signal (e.g., the clock signal) to determine if an edge of the clock falls between the edges of the data signal in the selected phase pair, or falls outside the edges of the selected phase pair, on one side or the other thereof. If the clock edge falls outside the selected pair, a control signal selects another pair for comparison and the process is repeated until, for example, the data edges are aligned with the positive going edge of the clock. With a clock frequency equal to twice data frequency, the data can then be sampled on the falling edge of the clock.
摘要翻译：边缘检测器具有数字锁相环，其中信号之一（例如，数据信号）耦合到产生输入的一系列增量相位延迟版本的延迟链。选择相邻相位延迟对，每次一对，并与另一个信号（例如，时钟信号）进行比较，以确定时钟的边沿是否落在所选相位对中的数据信号的边沿之间，或在所选相位对的边缘之外，在其一侧或另一侧上。如果时钟沿落在所选择的对之外，则控制信号选择另一对进行比较，并且重复处理，直到例如数据沿与时钟的正向边对齐。在时钟频率等于两倍数据频率的情况下，可以在时钟的下降沿对数据进行采样。

2. 发明授权

US5487095A Edge detector 失效
公开(公告)号：US5487095A
公开(公告)日：1996-01-23
申请号：US262087
申请日：1994-06-17
申请人： Richard C. Jordan , Robert S. Capowski , Daniel F. Casper , Frank D. Ferraiolo , William C. Laviola , Peter R. Tomaszewski
发明人： Richard C. Jordan , Robert S. Capowski , Daniel F. Casper , Frank D. Ferraiolo , William C. Laviola , Peter R. Tomaszewski
IPC分类号： H03L7/06 , H04L7/033 , H04L7/04 , H04L7/00
CPC分类号： H04L7/0338
摘要： An edge detector has a digital phase locking loop in which one of the signals (e.g., the data signal) is coupled to a delay chain that develops a series of incrementally phase delayed versions of the input. Adjacent phase delayed pairs are selected, one pair at a time, and are compared to the other signal (e.g., the clock signal) to determine if an edge of the clock falls between the edges of the data signal in the selected phase pair, or falls outside the edges of the selected phase pair, on one side or the other thereof. If the clock edge falls outside the selected pair, a control signal selects another pair for comparison and the process is repeated until, for example, the data edges are aligned with the positive going edge of the clock. With a clock frequency equal to twice data frequency, the data can then be sampled on the falling edge of the clock.

3. 发明授权

US5568526A Self timed interface 失效
标题翻译：自定义界面
公开(公告)号：US5568526A
公开(公告)日：1996-10-22
申请号：US452445
申请日：1995-05-26
申请人： Frank D. Ferraiolo , Robert S. Capowski , Daniel F. Casper , Richard C. Jordan , William C. Laviola
发明人： Frank D. Ferraiolo , Robert S. Capowski , Daniel F. Casper , Richard C. Jordan , William C. Laviola
IPC分类号： G06F13/42 , H04L7/00 , H04L7/033 , H04B1/10
CPC分类号： H04L7/0338 , G06F13/4256 , H04L7/0008
摘要： A self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. The received clock signal is used to define boundary edges of a data bit cell individually for each line and the data on each line of the bus is individually phase adjusted so that, for example, a data transition position is in the center of the cell.
摘要翻译：自定时接口（STI），其中时钟信号将串行数据时钟位于并行导电总线上，并且时钟信号在总线的单独线路上传输。总线上每条线上的接收数据与时钟信号单独相位对准。所接收的时钟信号用于为每条线分别定义数据位单元的边界，并且总线的每条线上的数据被单独相位调整，使得例如数据转换位置位于单元的中心。

4. 发明授权

US5598442A Self-timed parallel inter-system data communication channel 失效
标题翻译：自定时并行系统间数据通信通道
公开(公告)号：US5598442A
公开(公告)日：1997-01-28
申请号：US261522
申请日：1994-06-17
申请人： Thomas A. Gregg , Robert S. Capowski , Daniel F. Casper , Frank D. Ferraiolo
发明人： Thomas A. Gregg , Robert S. Capowski , Daniel F. Casper , Frank D. Ferraiolo
IPC分类号： G06F13/42 , H04L7/00 , H04L7/02 , H04L7/033 , H04L7/04 , H04L12/56 , H04L25/14 , H04L25/49 , H04L29/06
CPC分类号： H04L29/06 , G06F13/4278 , H04L25/14 , H04L25/4908 , H04L7/041 , H04L2007/045 , H04L69/14 , H04L7/0008
摘要： A self-timed interface (STI) links two physically separated systems or nodes. A transmit state machine forms each word in a serial bit stream into a plurality of bytes and generates idle and data character sequences. Each byte is separately encoded in a run-length-limited code, along with its idle and data character sequences. Each of the plurality of bytes is transmitted on a separate conducting line along with a transmit clock signal that is also transmitted on a separate line. At the receiver, the data stream on each line is separately phase aligned with the clock, and bit aligned.
摘要翻译：自定义接口（STI）链接两个物理上分离的系统或节点。发送状态机将串行比特流中的每个单词形成多个字节，并生成空闲和数据字符序列。每个字节分别以游程长度限制的代码及其空闲和数据字符序列编码。多个字节中的每一个与分离的线路上发送的发送时钟信号一起在单独的导线上发送。在接收机上，每行上的数据流与时钟分开相位对齐，并且位对齐。

5. 发明授权

US5522088A Shared channel subsystem has a self timed interface using a received clock signal to individually phase align bits received from a parallel bus 失效
标题翻译：共享信道子系统具有使用接收到的时钟信号的自定时接口，以对从并行总线接收的位进行单独的相位对准
公开(公告)号：US5522088A
公开(公告)日：1996-05-28
申请号：US261641
申请日：1994-06-17
申请人： Marten J. Halma , Robert S. Capowski , Daniel F. Casper , Frank D. Ferraiolo , Martin W. Sachs
发明人： Marten J. Halma , Robert S. Capowski , Daniel F. Casper , Frank D. Ferraiolo , Martin W. Sachs
IPC分类号： G06F13/40 , G06F13/42 , G06F13/00
CPC分类号： G06F13/4022 , G06F13/405
摘要： A shared channel subsystem has an input-output element for coupling each of a plurality of input-output controllers to each of a plurality of processor nodes by means of a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal, providing a cost effective, modular input/output element.
摘要翻译：共享信道子系统具有用于通过自定义接口（STI）将多个输入 - 输出控制器中的每一个耦合到多个处理器节点中的每一个的输入 - 输出元件，其中时钟信号将位串行数据时钟并行的导电总线，并且时钟信号在总线的单独线路上传输。总线上每条线上的接收数据与时钟信号单独相位对齐，提供了一个经济有效的模块化输入/输出元件。

6. 发明授权

US5513377A Input-output element has self timed interface using a received clock signal to individually phase aligned bits received from a parallel bus 失效
标题翻译：输入输出元件具有使用接收的时钟信号的自定时接口，以对从并行总线接收的单独的相位对准位
公开(公告)号：US5513377A
公开(公告)日：1996-04-30
申请号：US261561
申请日：1994-06-17
申请人： Robert S. Capowski , Daniel F. Casper , Frederick J. Cox , Frank D. Ferraiolo , Marten J. Halma
发明人： Robert S. Capowski , Daniel F. Casper , Frederick J. Cox , Frank D. Ferraiolo , Marten J. Halma
IPC分类号： H04L29/00 , G06F13/42 , H04L7/00 , G06F13/00
CPC分类号： G06F13/423
摘要： An enhanced input-output element has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal to provide a cost effective, modular, broadband, input/output element that can serve economically two channels and is modularly scalable to serve several hundred channels.
摘要翻译：增强的输入 - 输出元件具有自定时接口（STI），其中时钟信号将位串行数据时钟并入并行导电总线，时钟信号在总线的单独线路上传输。总线上每条线上的接收数据与时钟信号单独相位对准，以提供经济有效的模块化宽带输入/输出元件，可以经济地服务于两个通道，并可模块化地扩展以提供数百个通道。

7. 发明授权

US5613068A Method for transferring data between processors on a network by establishing an address space for each processor in each other processor's 失效
标题翻译：通过为每个其他处理器的存储器中的每个处理器建立地址空间来在网络上的处理器之间传送数据的方法
公开(公告)号：US5613068A
公开(公告)日：1997-03-18
申请号：US262081
申请日：1994-06-17
申请人： Thomas A. Gregg , Robert S. Capowski , Frank D. Ferraiolo , Marten J. Halma , Thomas H. Hillock , Robert E. Murray
发明人： Thomas A. Gregg , Robert S. Capowski , Frank D. Ferraiolo , Marten J. Halma , Thomas H. Hillock , Robert E. Murray
IPC分类号： G06F15/16 , G06F13/00 , G06F15/163 , G06F15/167 , G06F15/17 , G06F15/173 , G06F15/177 , H04L12/56 , G06F9/24 , G06F12/08 , G06F13/38
CPC分类号： G06F15/17375 , G06F15/17
摘要： A multi-system interconnect facility in which each central processor complex in the system has an assigned storage space for each other central processor complex in the system for use in communicating with each other central processor complex. The allegiance or association of systems to particular storage spaces is established when each system is initialized and enables a simple interface between user program(s) and message passing hardware consisting primarily of instructions for moving control and data blocks between the program addressable space and the hardware addressable space.
摘要翻译：一种多系统互连设施，其中系统中的每个中央处理器复合体具有用于系统中的每个其他中央处理器复合体的分配的存储空间，用于与彼此中央处理器复合体通信。当每个系统被初始化时，建立系统对特定存储空间的忠诚或关联，并且使得用户程序和消息传递硬件之间的简单接口主要包括用于在程序可寻址空间和硬件之间移动控制和数据块的指令可寻址空间。

8. 发明授权

US4604709A Channel communicator 失效
标题翻译：频道通讯员
公开(公告)号：US4604709A
公开(公告)日：1986-08-05
申请号：US465952
申请日：1983-02-14
申请人： Frederick T. Blount , Robert S. Capowski , Daniel F. Casper , Lawrence R. DelSonno , Robert F. Geller , Joseph M. Kusmiss , Terrence K. Zimmerman
发明人： Frederick T. Blount , Robert S. Capowski , Daniel F. Casper , Lawrence R. DelSonno , Robert F. Geller , Joseph M. Kusmiss , Terrence K. Zimmerman
IPC分类号： G06F13/12 , H04L29/02 , G06F13/14 , G06F13/38
CPC分类号： G06F13/126
摘要： A channel communicator CC has a storage array for holding an entry for each channel and for holding a busy vector and an interrupt vector that each have a bit for each channel. The CC is connected between the input bus and the output bus that connect the channels and an I/O processor IOP to processor main store. A message to the CC includes the ID of the channel that the message is to or from and the CC uses this ID as an address for accessing a channel entry or a bit in a vector. The message also carries a command that controls the CC to store a data portion of a message or to fetch a channel entry or a vector from the array and load it onto the output bus addressed to the IOP or to one of the channels. The command also controls addressing a particular one of the vectors. The CC also has means responsive to a command to perform a sequence of operations for testing the vectors and for testing fields of an entry in the array and for using the results of the test to control the execution of the command.
摘要翻译：信道通信器CC具有存储阵列，用于保存每个信道的条目，并且用于保存忙向量和每个具有每个信道的位的中断向量。 CC连接在输入总线和连接通道的输出总线和I / O处理器IOP到处理器主存储器之间。向CC发送的消息包括消息所在信道的ID，CC使用该ID作为访问信道条目的地址或向量中的位。该消息还携带控制CC以存储消息的数据部分的命令，或从阵列中获取信道条目或向量，并将其加载到寻址到IOP或其中一个信道的输出总线上。该命令还控制寻址一个特定的向量。 CC还具有响应于命令来执行用于测试向量的操作序列和用于测试阵列中条目的字段以及使用测试结果来控制命令的执行的装置。

9. 发明授权

US5509122A Configurable, recoverable parallel bus 失效
标题翻译：可配置的可并行总线
公开(公告)号：US5509122A
公开(公告)日：1996-04-16
申请号：US71146
申请日：1993-06-01
申请人： Neil G. Bartow , Robert S. Capowski , Louis T. Fasano , Thomas A. Gregg , Gregory Salyer , Douglas W. Westcott
发明人： Neil G. Bartow , Robert S. Capowski , Louis T. Fasano , Thomas A. Gregg , Gregory Salyer , Douglas W. Westcott
IPC分类号： G06F13/12 , G06F15/17 , G06F15/173 , H04J3/06 , H04L7/10 , H04L29/06 , H04L29/08 , H04L29/14 , G06F11/00
CPC分类号： G06F13/122 , G06F15/17 , G06F15/17343 , H04J3/0629 , H04L29/06 , H04L69/40 , H04L7/10 , H04L69/14 , H04L69/323 , H04L69/324
摘要： A system for the transmission of information between elements of a data processing complex and a method for establishing such a system. Two elements of a data processing system are connected by a physical link comprising multiple conductors attached to transceivers at channels in each data processing element. Once the transceivers have been synchronized, commands and responses are exchanged which ensure that all of the transceivers in a channel are connected to the same channel on the other end of the conductor. If the transceivers are considered configured an entry is made in a Configured-Transceiver table. A search is made of an Allowed-Operational-Link table which contains sets of transceivers which are allowed to become operational links. The set of transceivers thus found, is compared against the Configured-Transceiver-Table to verify that all of the members of the set have been configured. If a match is found, this set of transceivers becomes an Intended-Operational-Link. The Intended-Operational-Link is verified to ensure that both channels agree on the set of conductors which form the operational link. If the Intended-Operational-Link verifies, the operational link is established therefrom.
摘要翻译：一种用于在数据处理复合体的元件之间传输信息的系统和用于建立这样的系统的方法。数据处理系统的两个元件通过物理链路连接，该物理链路包括在每个数据处理元件中的通道处附接到收发器的多个导体。一旦收发器已经同步，则交换命令和响应，这确保通道中的所有收发器连接到导体另一端上的相同通道。如果收发器被视为配置，则在配置收发器表中进行条目。搜索允许操作链表，其中包含允许成为操作链接的收发器集合。因此找到的收发器集合与Configured-Transceiver-Table进行比较，以验证集合中的所有成员是否已配置。如果找到一个匹配，这组收发器就成为一个Intended-Operational-Link。验证了目的 - 操作链路，以确保两个通道对形成操作链路的一组导体达成一致。如果“预想 - 运营 - 链路”验证，则建立运营链路。

10. 发明授权

US5412803A Communications system having plurality of originator and corresponding recipient buffers with each buffer having three different logical areas for transmitting messages in single transfer 失效
标题翻译：具有多个发起者和对应的接收缓冲器的通信系统，每个缓冲器具有三个不同的逻辑区域，用于在单次传送中发送消息
公开(公告)号：US5412803A
公开(公告)日：1995-05-02
申请号：US839652
申请日：1992-02-20
申请人： Neil G. Bartow , Paul J. Brown , Robert S. Capowski , Louis T. Fasano , Thomas A. Gregg , Gregory Salyer , Douglas W. Westcott
发明人： Neil G. Bartow , Paul J. Brown , Robert S. Capowski , Louis T. Fasano , Thomas A. Gregg , Gregory Salyer , Douglas W. Westcott
IPC分类号： G06F13/00 , G06F13/12 , G06F13/38 , H04L29/06 , H04L29/08 , H04L29/14
CPC分类号： G06F13/122 , H04L69/40 , H04L69/14
摘要： Buffers are provided in two elements between which data is to be transferred wherein both buffers are managed solely by the originator of the data transfer. Only one transfer is required to transmit a message, and a second transfer acknowledges the completion of the function because message delivery to the receiver is guaranteed under the implemented protocol. When a request is sent, a message timer is started at the sender. When the normal response for the request is received, the timer is reset; however, if the duration of the message operation exceeds the timeout value, a message-timeout procedure is initiated. When the cancel command is issued, a second timer is set. If this timer is exceeded, subsequent cancel commands can be issued. If subsequent cancel commands are issued, a cancel complete command must be sent and responded to. Since the commands must be executed in the sequence in which they are received, a response to the cancel complete command ensures that there are no other cancel operation commands remaining in the receiver, allowing subsequent operations to start without danger of being canceled.
摘要翻译：缓冲器被提供在要传送数据的两个元件中，其中两个缓冲器仅由数据传送的发起者管理。传输消息只需要一次传输，第二次传输确认功能的完成，因为在实现的协议下向接收者传递消息。当发送请求时，在发送方开始一个消息定时器。当接收到请求的正常响应时，定时器被复位; 然而，如果消息操作的持续时间超过超时值，则启动消息超时过程。当取消命令发出时，设置第二个定时器。如果超过此定时器，则可以发出后续取消命令。如果发出后续取消命令，则必须发送取消完成命令并进行响应。由于命令必须按照接收的顺序执行，所以对取消完成命令的响应确保在接收器中不存在其他取消操作命令，允许后续操作开始而不会被取消危险。

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