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1. 发明申请

US20050154817A1 Method of operation and controlling a memory device 审中-公开
标题翻译：操作和控制存储器件的方法
公开(公告)号：US20050154817A1
公开(公告)日：2005-07-14
申请号：US11030382
申请日：2005-01-06
申请人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
发明人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
IPC分类号： G06F12/00 , G06F13/16 , G06F13/42 , G11C7/10 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C11/4076
CPC分类号： G11C7/1072 , G06F1/3225 , G06F13/1689 , G06F13/1694 , G06F13/4239 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2207/2254 , Y02D10/151
摘要： A method of operation of a memory device and system includes receiving a first and second value in embodiments. The first value is representative of a number of clock cycles of a clock signal that elapse between latching a column address and an access of data sensed from a row of memory cells in a memory array. A location of the data is based on the column address. The second value is representative of a number of clock cycles of the clock signal that elapse between the access of data from the memory array and outputting the data. The first and second values are received during an initialization sequence. Information in units of time that represents first and second timing parameters that pertains to the memory device is read from a storage location. The information that represents the first and second timing parameters are then converted from units of time to units of clock cycles to derive the first and second values.
摘要翻译：存储器件和系统的操作方法包括在实施例中接收第一和第二值。第一个值表示在锁存列地址和从存储器阵列中的一行存储器单元传感的数据的访问之间经过的时钟信号的多个时钟周期。数据的位置基于列地址。第二个值表示从存储器阵列访问数据并输出数据之间经过的时钟信号的数个时钟周期。在初始化序列期间接收第一和第二值。从存储位置读取表示与存储器件相关的第一和第二定时参数的以时间为单位的信息。然后将表示第一和第二定时参数的信息从时间单位从时钟周期的单位转换为导出第一和第二值。

2. 发明申请

US20050193183A1 Method and apparatus for initializing dynamic random access memory (DRAM) devices 审中-公开
标题翻译：用于初始化动态随机存取存储器（DRAM）设备的方法和装置
公开(公告)号：US20050193183A1
公开(公告)日：2005-09-01
申请号：US11119319
申请日：2005-04-29
申请人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
发明人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
IPC分类号： G06F12/00 , G06F13/16 , G06F13/42 , G11C7/10 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G06F1/04
CPC分类号： G11C7/1072 , G06F1/3225 , G06F13/1689 , G06F13/1694 , G06F13/4239 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2207/2254 , Y02D10/151
摘要： A memory module comprises a random access memory device having a memory array. The random access memory device includes a first register to store a first value that is representative of a number of clock cycles of a clock signal to elapse between latching a column address and an access of data sensed from a row of memory cells in the memory array, wherein a location of the data is based on the column address. A second register stores a second value that is representative of a number of clock cycles of the clock signal to elapse between the access of data from the memory array and outputting the data. A storage device stores a plurality of parameter information that pertains to the random access memory device. The first value and the second value is based on at least a first parameter information of the plurality of parameter information.
摘要翻译：存储器模块包括具有存储器阵列的随机存取存储器件。随机存取存储器件包括第一寄存器，用于存储表示在锁存列地址和从存储器阵列中的一行存储器单元传感的数据的访问之间经过的时钟信号的时钟周期数的第一值，其中所述数据的位置基于所述列地址。第二寄存器存储表示在从存储器阵列访问数据并输出数据之间经过的时钟信号的时钟周期数的第二值。存储装置存储与随机存取存储装置有关的多个参数信息。第一值和第二值基于多个参数信息的至少第一参数信息。

3. 发明申请

US20050154853A1 Memory device and method of operation of a memory device 审中-公开
标题翻译：存储器件和存储器件的操作方法
公开(公告)号：US20050154853A1
公开(公告)日：2005-07-14
申请号：US11030231
申请日：2005-01-06
申请人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
发明人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
IPC分类号： G06F12/00 , G06F13/16 , G06F13/42 , G11C7/10 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C11/4076
CPC分类号： G11C7/1072 , G06F1/3225 , G06F13/1689 , G06F13/1694 , G06F13/4239 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2207/2254 , Y02D10/151
摘要： A method of operation of a memory device and a memory device having registers to store values representing a number of clock cycles to access and output data is provided in embodiments. Data is sensed from an array of memory cells using a plurality of sense amplifiers. A column address that identifies data sensed is latched using the plurality of sense amplifiers. The data is accessed, based on the column address, after a first number of clock cycles of a clock signal have elapsed after latching the column address. The first number of clock cycles is represented by a first value stored in a first register on the memory device. The data is output after a second number of clock cycles have elapsed after accessing the data from the array of memory cells. The second number of clock cycles is represented by a second value stored in a second register on the memory device. A column decoder driving a column select line based on the column address accesses the data.
摘要翻译：在实施例中提供了一种存储器件和存储器件的操作方法，该存储器件具有用于存储表示多个时钟周期以访问和输出数据的值的寄存器。使用多个读出放大器从存储器单元阵列感测数据。使用多个读出放大器来锁存识别感测数据的列地址。在锁存列地址后经过时钟信号的第一个时钟周期之后，基于列地址访问数据。第一数量的时钟周期由存储在存储器件上的第一寄存器中的第一值表示。在从存储单元阵列访问数据之后经过了第二个时钟周期数之后，数据被输出。第二数量的时钟周期由存储在存储器件中的第二寄存器中的第二值表示。基于列地址驱动列选择行的列解码器访问数据。

4. 发明申请

US20050216654A1 System and module including a memory device having a power down mode 有权
标题翻译：系统和模块包括具有断电模式的存储器件
公开(公告)号：US20050216654A1
公开(公告)日：2005-09-29
申请号：US11137469
申请日：2005-05-25
申请人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
发明人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
IPC分类号： G06F12/00 , G06F13/16 , G06F13/42 , G11C7/10 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C11/4076
CPC分类号： G11C7/1072 , G06F1/3225 , G06F13/1689 , G06F13/1694 , G06F13/4239 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2207/2254 , Y02D10/151
摘要： A memory module comprises a memory device including a memory array to store data. An interface receives an instruction to exit a power down mode. A register stores a value representative of a period of time to elapse between exiting from the power down mode and a time at which the memory device is capable of receiving a command to access the data. A storage device stores a plurality of parameter information that pertains to the memory device. The value is based on at least a first parameter information of the plurality of parameter information.
摘要翻译：存储器模块包括存储设备，该存储器设备包括存储数据以存储数据。接口接收退出掉电模式的指令。寄存器存储代表从断电模式退出的时间段与存储器装置能够接收访问数据的命令的时间之间的值。存储装置存储与存储装置有关的多个参数信息。该值基于多个参数信息的至少第一参数信息。

5. 发明申请

US20050235130A1 System for a memory device having a power down mode and method 有权
标题翻译：具有断电模式和方法的存储器件的系统
公开(公告)号：US20050235130A1
公开(公告)日：2005-10-20
申请号：US11151791
申请日：2005-06-14
申请人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
发明人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
IPC分类号： G06F12/00 , G06F13/16 , G06F13/42 , G11C7/10 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C11/4076
CPC分类号： G11C7/1072 , G06F1/3225 , G06F13/1689 , G06F13/1694 , G06F13/4239 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2207/2254 , Y02D10/151
摘要： A system comprising a storage location to store information representing a timing parameter pertaining to a random access memory device. An integrated circuit device generates a value that is representative of a period of time that elapses between the random access memory device exiting from a power down mode and a time at which the random access memory device is capable of receiving a command. The integrated circuit device generates the value from the information representing the timing parameter pertaining to the random access memory device.
摘要翻译：一种系统，包括存储位置以存储表示随机存取存储器件的定时参数的信息。集成电路装置生成代表在从断电模式退出的随机存取存储装置与随机存取存储装置能够接收指令的时间之间经过的时间段的值。集成电路装置根据表示随机存取存储装置的定时参数的信息生成该值。

6. 发明申请

US20050120161A1 Methods of operation of a memory device and system 有权
标题翻译：存储器件和系统的操作方法
公开(公告)号：US20050120161A1
公开(公告)日：2005-06-02
申请号：US10993046
申请日：2004-11-19
申请人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
发明人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
IPC分类号： G06F12/00 , G06F13/16 , G06F13/42 , G11C7/10 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C11/4076
CPC分类号： G11C7/1072 , G06F1/3225 , G06F13/1689 , G06F13/1694 , G06F13/4239 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2207/2254 , Y02D10/151
摘要： Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first frequency of operation and the second frequency of operation is read from a serial presence detect device.
摘要翻译：在实施例中提供了存储器件和系统的操作方法。初始化操作在初始化序列期间以第一操作频率进行。然后在第二操作频率下执行存储器存取操作。第二个操作频率高于第一个操作频率。此外，存储器访问操作包括读取操作和写入操作。在实施例中，从串行存在检测装置读取表示第一操作频率和第二操作频率的信息。

7. 发明申请

US20050060487A1 Memory device having a power down exit register 有权
标题翻译：具有断电输出寄存器的存储器件
公开(公告)号：US20050060487A1
公开(公告)日：2005-03-17
申请号：US10944320
申请日：2004-09-17
申请人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
发明人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
IPC分类号： G06F12/00 , G06F13/16 , G06F13/42 , G11C7/10 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C11/4076
CPC分类号： G11C7/1072 , G06F1/3225 , G06F13/1689 , G06F13/1694 , G06F13/4239 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2207/2254 , Y02D10/151
摘要： A memory device including an array of memory cells, and a register circuit to store a value representative of a period of time to elapse before the memory device is ready to receive a command when recovering from a power down mode is provided in an embodiment. The command specifies an access to the array of memory cells. A delay lock loop circuit synchronizes data transfers using an external clock signal. The delay lock loop circuit reacquires synchronization with the external clock signal during the period of time.
摘要翻译：在一个实施例中，提供了一种包括存储器单元阵列的存储器件以及用于存储表示在从掉电模式恢复之前存储器件准备好接收命令之前经过一段时间的值的寄存器电路。该命令指定对存储单元阵列的访问。延迟锁定环路电路使用外部时钟信号同步数据传输。延迟锁定环路电路在一段时间内重新获得与外部时钟信号的同步。

8. 发明授权

US09036436B2 Supporting calibration for sub-rate operation in clocked memory systems 有权
标题翻译：支持定时存储器系统中子速率操作的校准
公开(公告)号：US09036436B2
公开(公告)日：2015-05-19
申请号：US13982474
申请日：2012-05-03
申请人： Akash Bansal , Yohan U. Frans , Kishore V. Kasamsetty , Todd Bystrom , Simon Li , Arun Vaidyanath
发明人： Akash Bansal , Yohan U. Frans , Kishore V. Kasamsetty , Todd Bystrom , Simon Li , Arun Vaidyanath
IPC分类号： G11C7/22 , G11C29/02 , G06F1/10
CPC分类号： G11C7/22 , G06F1/10 , G11C7/222 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： The disclosed embodiments related to a clocked memory system which performs a calibration operation at a full-rate frequency to determine a full-rate calibration state that specifies a delay between a clock signal and a corresponding data signal in the clocked memory system. Next, the clocked memory system uses the full-rate calibration state to calculate a sub-rate calibration state, which is associated with a sub-rate frequency (e.g., 1/2, 1/4 or 1/8 of the full-rate frequency). The system then uses this sub-rate calibration state when the clocked memory system is operating at the sub-rate frequency. This calculation of the sub-rate state calibration states eliminates the need to perform an additional time-consuming calibration operation for each sub-rate.
摘要翻译：所公开的实施例涉及一种时钟存储器系统，其以全速率频率执行校准操作，以确定指定时钟信号与时钟控制的存储器系统中的相应数据信号之间的延迟的全速率校准状态。接下来，时钟存储器系统使用全速率校准状态来计算子速率校准状态，其与子速率频率（例如，全速率的1/2，1/4或1/8）相关联频率）。当时钟存储器系统以子速率频率工作时，系统然后使用该子速率校准状态。子速率状态校准状态的这种计算消除了对每个子速率执行附加耗时的校准操作的需要。

9. 发明授权

US08130891B2 Clock-data recovery (“CDR”) circuit, apparatus and method for variable frequency data 有权
标题翻译：时钟数据恢复（“CDR”）电路，可变频率数据的装置和方法
公开(公告)号：US08130891B2
公开(公告)日：2012-03-06
申请号：US12710250
申请日：2010-02-22
申请人： Dennis Kim , Jason Wei , Yohan Frans , Todd Bystrom , Nhat Nguyen , Kevin Donnelly
发明人： Dennis Kim , Jason Wei , Yohan Frans , Todd Bystrom , Nhat Nguyen , Kevin Donnelly
IPC分类号： H03D3/24
CPC分类号： H03L7/0814 , H03L7/091 , H04L7/0331
摘要： A circuit, such as a CDR circuit, includes a sampler to receive a data signal having a variable data bit-rate responsive to a clock signal in an embodiment of the present invention. A clock circuit is coupled to the sampler and generates the clock signal responsive to a selectable update rate and a selectable phase adjust step-size. In a second embodiment of the present invention, the clock circuit includes a Stall logic that is coupled to first, second and third stages and is capable to hold the phase adjust signal responsive to the first and second stage output signals. In a third embodiment of the present invention, an indicator detects the variable data bit-rate and a counter provides the selectable phase adjust step-size for the adjust signal. In a fourth embodiment of the present invention, the clock circuit includes the Stall logic, the indicator and the counter. In a fifth embodiment of the present invention, the clock circuit includes an Averaging circuit to output a phase adjust signal responsive to the averaging of a first and second adjust signals for a predetermined period of time.
摘要翻译：诸如CDR电路的电路包括采样器，以在本发明的实施例中接收具有响应于时钟信号的可变数据比特率的数据信号。时钟电路耦合到采样器并且响应于可选择的更新速率和可选择的相位调整步长而产生时钟信号。在本发明的第二实施例中，时钟电路包括耦合到第一，第二和第三级的失调逻辑，并且能够响应于第一和第二级输出信号保持相位调整信号。在本发明的第三实施例中，指示器检测可变数据比特率，并且计数器为调整信号提供可选择的相位调整步长。在本发明的第四实施例中，时钟电路包括失速逻辑，指示器和计数器。在本发明的第五实施例中，时钟电路包括平均电路，用于响应于在预定时间段内的第一和第二调整信号的平均来输出相位调整信号。

10. 发明授权

US07668271B2 Clock-data recovery (“CDR”) circuit, apparatus and method for variable frequency data 有权
标题翻译：时钟数据恢复（“CDR”）电路，可变频率数据的装置和方法
公开(公告)号：US07668271B2
公开(公告)日：2010-02-23
申请号：US10675027
申请日：2003-09-30
申请人： Dennis Kim , Jason Wei , Yohan Frans , Todd Bystrom , Nhat Nguyen , Kevin Donnelly
发明人： Dennis Kim , Jason Wei , Yohan Frans , Todd Bystrom , Nhat Nguyen , Kevin Donnelly
IPC分类号： H04L7/00
CPC分类号： H03L7/0814 , H03L7/091 , H04L7/0331
摘要： A circuit, such as a CDR circuit, includes a sampler to receive a data signal having a variable data bit-rate responsive to a clock signal in an embodiment of the present invention. A clock circuit is coupled to the sampler and generates the clock signal responsive to a selectable update rate and a selectable phase adjust step-size. In a second embodiment of the present invention, the circuit includes a Stall logic that is coupled to first, second and third stages and is capable to hold the phase adjust signal responsive to the first and second stage output signals. In a third embodiment of the present invention, an indicator detects the variable data bit-rate and a counter provides the selectable phase adjust step-size for the adjust signal. In a fourth embodiment of the present invention, the circuit includes the Stall logic, the indicator and the counter. In a fifth embodiment of the present invention, the circuit includes an Averaging circuit to output a phase adjust signal responsive to the averaging of a first and second adjust signals for a predetermined period of time.
摘要翻译：诸如CDR电路的电路包括采样器，以在本发明的实施例中接收具有响应于时钟信号的可变数据比特率的数据信号。时钟电路耦合到采样器并且响应于可选择的更新速率和可选择的相位调整步长而产生时钟信号。在本发明的第二实施例中，该电路包括一个与第一，第二和第三级耦合的稳态逻辑，并能够响应第一和第二级输出信号保持相位调整信号。在本发明的第三实施例中，指示器检测可变数据比特率，并且计数器为调整信号提供可选择的相位调整步长。在本发明的第四实施例中，电路包括停顿逻辑，指示器和计数器。在本发明的第五实施例中，电路包括平均电路，用于响应于在预定时间段内对第一和第二调整信号的平均来输出相位调整信号。

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