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1. 发明授权

US08405186B2 Transistor structure with a sidewall-defined intrinsic base to extrinsic base link-up region and method of forming the structure 有权
标题翻译：具有侧壁限定的内在基极到外部基极连接区域的晶体管结构和形成该结构的方法
公开(公告)号：US08405186B2
公开(公告)日：2013-03-26
申请号：US12817249
申请日：2010-06-17
申请人： Renata Camillo-Castillo , Mattias E. Dahlstrom , Peter B. Gray , David L. Harame , Russell T. Herrin , Alvin J. Joseph , Andreas D. Stricker
发明人： Renata Camillo-Castillo , Mattias E. Dahlstrom , Peter B. Gray , David L. Harame , Russell T. Herrin , Alvin J. Joseph , Andreas D. Stricker
IPC分类号： H01L21/70
CPC分类号： H01L29/732 , H01L29/66242 , H01L29/66287 , H01L29/7378
摘要： Disclosed are embodiments of an improved transistor structure (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure. The structure embodiments can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method embodiments allow for self-aligning of the emitter to base regions and further allow the geometries of different features (e.g., the thickness of the dielectric layer, the width of the conductive strap, the width of the dielectric spacer and the width of the emitter layer) to be selectively adjusted in order to optimize transistor performance.
摘要翻译：公开了改进的晶体管结构（例如，双极晶体管（BT）结构或异质结双极晶体管（HBT）结构）的实施例以及形成晶体管结构的方法。结构实施例可以包括夹在本征基极层和凸起的非本征基极层之间的电介质层，以将集电极 - 基极电容Ccb，用于本征基极层的侧壁限定导电带限制到外部基极层连接区域以减少基极电阻Rb和外部基极层和发射极层之间的介电间隔物，以减少基极 - 发射极的Cbe电容。该方法实施例允许发射极与基极区域的自对准，并进一步允许不同特征的几何形状（例如，电介质层的厚度，导电带的宽度，电介质间隔物的宽度和介电隔离物的宽度发射极层）进行选择性调整，以优化晶体管性能。

2. 发明申请

US20110309471A1 TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE STRUCTURE 有权
标题翻译：具有侧向定义的内部基极到极端基底连接区域的晶体管结构及形成结构的方法
公开(公告)号：US20110309471A1
公开(公告)日：2011-12-22
申请号：US12817249
申请日：2010-06-17
申请人： Renata Camillo-Castillo , Mattias E. Dahlstrom , Peter B. Gray , David L. Harame , Russell T. Herrin , Alvin J. Joseph , Andreas D. Stricker
发明人： Renata Camillo-Castillo , Mattias E. Dahlstrom , Peter B. Gray , David L. Harame , Russell T. Herrin , Alvin J. Joseph , Andreas D. Stricker
IPC分类号： H01L29/73 , H01L21/331
CPC分类号： H01L29/732 , H01L29/66242 , H01L29/66287 , H01L29/7378
摘要： Disclosed are embodiments of an improved transistor structure (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure. The structure embodiments can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method embodiments allow for self-aligning of the emitter to base regions and further allow the geometries of different features (e.g., the thickness of the dielectric layer, the width of the conductive strap, the width of the dielectric spacer and the width of the emitter layer) to be selectively adjusted in order to optimize transistor performance.
摘要翻译：公开了改进的晶体管结构（例如，双极晶体管（BT）结构或异质结双极晶体管（HBT）结构）的实施例以及形成晶体管结构的方法。结构实施例可以包括夹在本征基极层和凸起的非本征基极层之间的电介质层，以将集电极 - 基极电容Ccb，用于本征基极层的侧壁限定导电带限制到外部基极层连接区域以减少基极电阻Rb和外部基极层和发射极层之间的介电间隔物，以减少基极 - 发射极的Cbe电容。该方法实施例允许发射极与基极区域的自对准，并进一步允许不同特征的几何形状（例如，电介质层的厚度，导电带的宽度，电介质间隔物的宽度和介电隔离物的宽度发射极层）进行选择性调整，以优化晶体管性能。

3. 发明申请

US20130009280A1 BIPOLAR JUNCTION TRANSISTORS WITH A LINK REGION CONNECTING THE INTRINSIC AND EXTRINSIC BASES 有权
标题翻译：具有连接本地和特殊基础的链接区域的双极性连接晶体管
公开(公告)号：US20130009280A1
公开(公告)日：2013-01-10
申请号：US13177146
申请日：2011-07-06
申请人： Renata Camillo-Castillo , Peter B. Gray , David L. Harame , Alvin J. Joseph , Marwan H. Khater , Qizhi Liu
发明人： Renata Camillo-Castillo , Peter B. Gray , David L. Harame , Alvin J. Joseph , Marwan H. Khater , Qizhi Liu
IPC分类号： H01L21/331 , H01L29/73
CPC分类号： H01L29/73 , H01L21/8249 , H01L27/0623 , H01L29/0821 , H01L29/107 , H01L29/66272 , H01L29/7322
摘要： Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor includes a dielectric layer on an intrinsic base and an extrinsic base at least partially separated from the intrinsic base by the dielectric layer. An emitter opening extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer that physically links the extrinsic base and the intrinsic base together.
摘要翻译：用于制造双极结型晶体管的方法，通过该方法制造的双极结型晶体管以及双极结型晶体管的设计结构。双极结晶体管包括在本征基极上的电介质层和通过电介质层至少部分地与本征基极分离的外部基极。发射极开口延伸穿过外部基极和电介质层。电介质层相对于发射器开口横向凹入以限定内部基极和外部基极之间的腔。空腔填充有将外部基极和内在基极物理连接在一起的半导体层。

4. 发明授权

US08536012B2 Bipolar junction transistors with a link region connecting the intrinsic and extrinsic bases 有权
标题翻译：具有连接内在和外在基极的连接区域的双极结晶体管
公开(公告)号：US08536012B2
公开(公告)日：2013-09-17
申请号：US13177146
申请日：2011-07-06
申请人： Renata Camillo-Castillo , Peter B. Gray , David L. Harame , Alvin J. Joseph , Marwan H. Khater , Qizhi Liu
发明人： Renata Camillo-Castillo , Peter B. Gray , David L. Harame , Alvin J. Joseph , Marwan H. Khater , Qizhi Liu
IPC分类号： H01L21/331 , H01L21/02
CPC分类号： H01L29/73 , H01L21/8249 , H01L27/0623 , H01L29/0821 , H01L29/107 , H01L29/66272 , H01L29/7322
摘要： Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor includes a dielectric layer on an intrinsic base and an extrinsic base at least partially separated from the intrinsic base by the dielectric layer. An emitter opening extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer that physically links the extrinsic base and the intrinsic base together.
摘要翻译：用于制造双极结型晶体管的方法，通过该方法制造的双极结型晶体管以及双极结型晶体管的设计结构。双极结晶体管包括在本征基极上的电介质层和通过电介质层至少部分地与本征基极分离的外部基极。发射极开口延伸穿过外部基极和电介质层。电介质层相对于发射器开口横向凹入以限定内部基极和外部基极之间的腔。空腔填充有将外部基极和内在基极物理连接在一起的半导体层。

5. 发明授权

US07253096B2 Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same 失效
标题翻译：双极晶体管具有可选择的自对准的外部基极和其形成方法
公开(公告)号：US07253096B2
公开(公告)日：2007-08-07
申请号：US11289915
申请日：2005-11-30
申请人： Marwan H. Khater , James S. Dunn , David L. Harame , Alvin J. Joseph , Qizhi Liu , Francois Pagette , Stephen A. St. Onge , Andreas D. Stricker
发明人： Marwan H. Khater , James S. Dunn , David L. Harame , Alvin J. Joseph , Qizhi Liu , Francois Pagette , Stephen A. St. Onge , Andreas D. Stricker
IPC分类号： H01L21/4763
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/66242 , H01L29/732 , H01L29/7378
摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.
摘要翻译：公开了一种具有凸起的外在基极和在本征基极和发射极之间可选自对准的双极晶体管。制造方法可以包括在内在基底上形成多晶硅或硅的第一非本征基极层的预定厚度。然后通过在第一非本征基层上的光刻形成电介质着色焊盘。接下来，在电介质贴片垫的顶部上形成第二非多晶硅或硅的非本征基极层，以最终确定凸出的非本征基本总厚度。使用光刻和RIE形成发射器开口，其中第二外部基极层被蚀刻停止在电介质着色焊盘上。通过选择第一非本征基极层厚度，电介质着陆焊盘宽度和间隔物宽度来实现发射极和凸出的外部基极之间的自对准程度。

6. 发明授权

US07002221B2 Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same 有权
公开(公告)号：US07002221B2
公开(公告)日：2006-02-21
申请号：US10604988
申请日：2003-08-29
申请人： Marwan H. Khater , James S. Dunn , David L. Harame , Alvin J. Joseph , Qizhi Liu , Francois Pagette , Stephen A. St. Onge , Andreas D. Stricker
发明人： Marwan H. Khater , James S. Dunn , David L. Harame , Alvin J. Joseph , Qizhi Liu , Francois Pagette , Stephen A. St. Onge , Andreas D. Stricker
IPC分类号： H01L23/62
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/66242 , H01L29/732 , H01L29/7378
摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.

7. 发明授权

US08735986B2 Forming structures on resistive substrates 有权
标题翻译：在电阻基板上形成结构
公开(公告)号：US08735986B2
公开(公告)日：2014-05-27
申请号：US13312442
申请日：2011-12-06
申请人： Alan B. Botula , Renata Camillo-Castillo , James S. Dunn , Jeffrey P. Gambino , Douglas B. Hershberger , Alvin J. Joseph , Robert M. Rassel , Mark E. Stidham
发明人： Alan B. Botula , Renata Camillo-Castillo , James S. Dunn , Jeffrey P. Gambino , Douglas B. Hershberger , Alvin J. Joseph , Robert M. Rassel , Mark E. Stidham
IPC分类号： H01L27/12
CPC分类号： H01L21/76224 , H01L21/26506 , H01L21/823892 , H01L27/04 , H01L27/0623 , H01L27/0635 , H01L27/0802 , H01L27/0811 , H01L27/0928
摘要： A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.
摘要翻译：衬底包括具有第一电阻率的第一区域，用于优化场效应晶体管，具有第二电阻率的第二区域，用于优化双极晶体管器件和三阱的npn子集电极，具有第三电阻率的第三区域，具有第三电阻率用于无源器件的高电阻率，第四区域，基本上没有植入，以为器件提供低周边电容。

8. 发明申请

US20130140668A1 Forming Structures on Resistive Substrates 有权
标题翻译：电阻基板上的形成结构
公开(公告)号：US20130140668A1
公开(公告)日：2013-06-06
申请号：US13312442
申请日：2011-12-06
申请人： Alan B. Botula , Renata Camillo-Castillo , James S. Dunn , Jeffrey P. Gambino , Douglas B. Hershberger , Alvin J. Joseph , Mark E. Stidham , Robert M. Rassel
发明人： Alan B. Botula , Renata Camillo-Castillo , James S. Dunn , Jeffrey P. Gambino , Douglas B. Hershberger , Alvin J. Joseph , Mark E. Stidham , Robert M. Rassel
IPC分类号： H01L27/04 , H01L21/76
CPC分类号： H01L21/76224 , H01L21/26506 , H01L21/823892 , H01L27/04 , H01L27/0623 , H01L27/0635 , H01L27/0802 , H01L27/0811 , H01L27/0928
摘要： A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.
摘要翻译：衬底包括具有第一电阻率的第一区域，用于优化场效应晶体管，具有第二电阻率的第二区域，用于优化双极晶体管器件和三阱的npn子集电极，具有第三电阻率的第三区域，具有第三电阻率用于无源器件的高电阻率，第四区域，基本上没有植入，以为器件提供低周边电容。

9. 发明授权

US07932541B2 High performance collector-up bipolar transistor 有权
标题翻译：高性能集电极双极晶体管
公开(公告)号：US07932541B2
公开(公告)日：2011-04-26
申请号：US12013790
申请日：2008-01-14
申请人： Alvin J. Joseph , Andreas D. Stricker
发明人： Alvin J. Joseph , Andreas D. Stricker
IPC分类号： H01L27/082
CPC分类号： H01L29/7378 , H01L29/0817 , H01L29/0821 , H01L29/167 , H01L29/66242
摘要： Disclosed are embodiments of a hetero-junction bipolar transistor (HBT) structure and method of forming the structure that provides substantially lower collector-to-base parasitic capacitance and collector resistance, while also lowering or maintaining base-to-emitter capacitance, emitter resistance and base resistance in order to achieve frequency capabilities in the THz range. The HBT is a collector-up HBT in which a dielectric layer and optional sidewall spacers separate the raised extrinsic base and the collector so as to reduce collector-to-base capacitance. A lower portion of the collector is single crystalline semiconductor so as to reduce collector resistance. The raised extrinsic base and the intrinsic base are stacked single crystalline epitaxial layers, where link-up is automatic and self-aligned, so as to reduce base resistance. The emitter is a heavily doped region below the top surface of a single crystalline semiconductor substrate so as to reduce emitter resistance.
摘要翻译：公开了异质结双极晶体管（HBT）结构的实施方案和形成提供基本上较低的集电极到基极寄生电容和集电极电阻的结构的方法，同时还降低或维持基极 - 发射极电容，发射极电阻和以达到THz范围内的频率能力。 HBT是集电极HBT，其中介电层和可选的侧壁间隔物分离凸起的外在基极和集电极，以便降低集电极到基极的电容。集电极的下部是单晶半导体，以减少集电极电阻。凸起的外在基极和本征基极是堆叠的单晶外延层，其中连接自动和自对准，以便降低基极电阻。发射极是单晶半导体衬底的顶表面下方的重掺杂区域，以便降低发射极电阻。

10. 发明申请

US20090179228A1 HIGH PERFORMANCE COLLECTOR-UP BIPOLAR TRANSISTOR 有权
标题翻译：高性能收集双极晶体管
公开(公告)号：US20090179228A1
公开(公告)日：2009-07-16
申请号：US12013790
申请日：2008-01-14
申请人： Alvin J. Joseph , Andreas D. Stricker
发明人： Alvin J. Joseph , Andreas D. Stricker
IPC分类号： H01L29/737 , H01L21/331
CPC分类号： H01L29/7378 , H01L29/0817 , H01L29/0821 , H01L29/167 , H01L29/66242
摘要： Disclosed are embodiments of a hetero-junction bipolar transistor (HBT) structure and method of forming the structure that provides substantially lower collector-to-base parasitic capacitance and collector resistance, while also lowering or maintaining base-to-emitter capacitance, emitter resistance and base resistance in order to achieve frequency capabilities in the THz range. The HBT is a collector-up HBT in which a dielectric layer and optional sidewall spacers separate the raised extrinsic base and the collector so as to reduce collector-to-base capacitance. A lower portion of the collector is single crystalline semiconductor so as to reduce collector resistance. The raised extrinsic base and the intrinsic base are stacked single crystalline epitaxial layers, where link-up is automatic and self-aligned, so as to reduce base resistance. The emitter is a heavily doped region below the top surface of a single crystalline semiconductor substrate so as to reduce emitter resistance.
摘要翻译：公开了异质结双极晶体管（HBT）结构的实施方案和形成提供基本上较低的集电极到基极寄生电容和集电极电阻的结构的方法，同时还降低或维持基极 - 发射极电容，发射极电阻和以达到THz范围内的频率能力。 HBT是集电极HBT，其中介电层和可选的侧壁间隔物分离凸起的外在基极和集电极，以便降低集电极到基极的电容。集电极的下部是单晶半导体，以减少集电极电阻。凸起的外在基极和本征基极是堆叠的单晶外延层，其中连接自动和自对准，以便降低基极电阻。发射极是单晶半导体衬底的顶表面下方的重掺杂区域，以便降低发射极电阻。

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