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1. 发明授权

US08735986B2 Forming structures on resistive substrates 有权
标题翻译：在电阻基板上形成结构
公开(公告)号：US08735986B2
公开(公告)日：2014-05-27
申请号：US13312442
申请日：2011-12-06
申请人： Alan B. Botula , Renata Camillo-Castillo , James S. Dunn , Jeffrey P. Gambino , Douglas B. Hershberger , Alvin J. Joseph , Robert M. Rassel , Mark E. Stidham
发明人： Alan B. Botula , Renata Camillo-Castillo , James S. Dunn , Jeffrey P. Gambino , Douglas B. Hershberger , Alvin J. Joseph , Robert M. Rassel , Mark E. Stidham
IPC分类号： H01L27/12
CPC分类号： H01L21/76224 , H01L21/26506 , H01L21/823892 , H01L27/04 , H01L27/0623 , H01L27/0635 , H01L27/0802 , H01L27/0811 , H01L27/0928
摘要： A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.
摘要翻译：衬底包括具有第一电阻率的第一区域，用于优化场效应晶体管，具有第二电阻率的第二区域，用于优化双极晶体管器件和三阱的npn子集电极，具有第三电阻率的第三区域，具有第三电阻率用于无源器件的高电阻率，第四区域，基本上没有植入，以为器件提供低周边电容。

2. 发明申请

US20130140668A1 Forming Structures on Resistive Substrates 有权
标题翻译：电阻基板上的形成结构
公开(公告)号：US20130140668A1
公开(公告)日：2013-06-06
申请号：US13312442
申请日：2011-12-06
申请人： Alan B. Botula , Renata Camillo-Castillo , James S. Dunn , Jeffrey P. Gambino , Douglas B. Hershberger , Alvin J. Joseph , Mark E. Stidham , Robert M. Rassel
发明人： Alan B. Botula , Renata Camillo-Castillo , James S. Dunn , Jeffrey P. Gambino , Douglas B. Hershberger , Alvin J. Joseph , Mark E. Stidham , Robert M. Rassel
IPC分类号： H01L27/04 , H01L21/76
CPC分类号： H01L21/76224 , H01L21/26506 , H01L21/823892 , H01L27/04 , H01L27/0623 , H01L27/0635 , H01L27/0802 , H01L27/0811 , H01L27/0928
摘要： A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.
摘要翻译：衬底包括具有第一电阻率的第一区域，用于优化场效应晶体管，具有第二电阻率的第二区域，用于优化双极晶体管器件和三阱的npn子集电极，具有第三电阻率的第三区域，具有第三电阻率用于无源器件的高电阻率，第四区域，基本上没有植入，以为器件提供低周边电容。

3. 发明授权

US08518782B2 Semiconductor device including asymmetric lightly doped drain (LDD) region, related method and design structure 有权
标题翻译：半导体器件包括非对称轻掺杂漏极（LDD）区域，相关方法和设计结构
公开(公告)号：US08518782B2
公开(公告)日：2013-08-27
申请号：US12963054
申请日：2010-12-08
申请人： Alan B. Botula , Robert M. Rassel , Yun Shi , Mark E. Stidham
发明人： Alan B. Botula , Robert M. Rassel , Yun Shi , Mark E. Stidham
IPC分类号： H01L21/426
CPC分类号： H01L29/7833 , H01L21/26586 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including a first source drain region, a second source drain region, and an intrinsic region therebetween; an asymmetric lightly doped drain (LDD) region within the substrate, wherein the asymmetric LDD region extends from the first source drain region into the intrinsic region between the first source drain region and the second source drain region; and a gate positioned atop the semiconductor substrate, wherein an outer edge of the gate overlaps the second source drain region. A related method and design structure are also disclosed.
摘要翻译：公开了一种半导体器件。半导体器件包括：半导体衬底，包括第一源极漏极区域，第二源极漏极区域及其之间的固有区域; 在所述衬底内的不对称轻掺杂漏极（LDD）区域，其中所述不对称LDD区域从所述第一源极漏极区域延伸到所述第一源极漏极区域和所述第二源极漏极区域之间的本征区域; 以及位于所述半导体衬底顶部的栅极，其中所述栅极的外边缘与所述第二源极漏极区重叠。还公开了相关的方法和设计结构。

4. 发明申请

US20120018837A1 SCHOTTKY BARRIER DIODE WITH PERIMETER CAPACITANCE WELL JUNCTION 有权
标题翻译：肖特基二极管与周边电容良好连接
公开(公告)号：US20120018837A1
公开(公告)日：2012-01-26
申请号：US12840791
申请日：2010-07-21
申请人： Frederick G. Anderson , Jenifer E. Lary , Robert M. Rassel , Mark E. Stidham
发明人： Frederick G. Anderson , Jenifer E. Lary , Robert M. Rassel , Mark E. Stidham
IPC分类号： H01L29/872 , G06F9/45 , H01L21/329
CPC分类号： H01L29/872 , H01L21/761 , H01L29/0619 , H01L29/0646 , H01L29/0692 , H01L29/66143
摘要： A Schottky barrier diode comprises a first-type substrate, a second-type well isolation region on the first-type substrate, and a first-type well region on the second-type well isolation region. With embodiments herein a feature referred to as a perimeter capacitance well junction ring is on the second-type well isolation region. A second-type well region is on the second-type well isolation region. The perimeter capacitance well junction ring is positioned between and separates the first-type well region and the second-type well region. A second-type contact region is on the second-type well region, and a first-type contact region contacts the inner portion of the first-type well region. The inner portion of the first-type well region is positioned within the center of the first-type contact region. Additionally, a first ohmic metallic layer is on the first-type contact region and a second ohmic metallic layer is on the first-type well region. The first ohmic metallic layer contacts the second ohmic metallic layer at a junction that makes up the Schottky barrier of the Schottky barrier diode.
摘要翻译：肖特基势垒二极管包括第一类型衬底，第一类型衬底上的第二类型阱隔离区域和第二类型阱隔离区域上的第一类型阱区域。在这里的实施例中，被称为周边电容阱接合环的特征在第二类型的隔离区域上。第二类型井区域位于第二类型井隔离区域上。周边电容阱接合环位于第一类型阱区域和第二类型阱区域之间并分离。第二类型接触区域位于第二类型阱区域上，并且第一类型接触区域接触第一类型阱区域的内部部分。第一类型阱区域的内部位于第一类型接触区域的中心内。此外，第一欧姆金属层位于第一类型接触区域上，第二欧姆金属层位于第一类型阱区域上。第一欧姆金属层在构成肖特基势垒二极管的肖特基势垒的结处接触第二欧姆金属层。

5. 发明授权

US08519478B2 Schottky barrier diode, a method of forming the diode and a design structure for the diode 有权
标题翻译：肖特基势垒二极管，形成二极管的方法和二极管的设计结构
公开(公告)号：US08519478B2
公开(公告)日：2013-08-27
申请号：US13019716
申请日：2011-02-02
申请人： Robert M. Rassel , Mark E. Stidham
发明人： Robert M. Rassel , Mark E. Stidham
IPC分类号： H01L29/06
CPC分类号： H01L29/66143 , G06F17/5068 , H01L29/872
摘要： Disclosed are embodiments of a Schottky barrier diode. This diode can be formed in a semiconductor substrate having a doped region with a first conductivity type. A trench isolation structure can laterally surround a section of the doped region at the top surface of the substrate. A semiconductor layer can be positioned on the top surface of the substrate. This semiconductor layer can have a Schottky barrier portion over the defined section of the doped region and a guardring portion over the trench isolation structure laterally surrounding the Schottky barrier portion. The Schottky barrier portion can have the first conductivity type and the guarding portion can have a second conductivity type different from the first conductivity type. A metal silicide layer can overlie the semiconductor layer. Also disclosed are embodiments of a method of forming this Schottky barrier diode and of a design structure for the Schottky barrier diode.
摘要翻译：公开了肖特基势垒二极管的实施例。该二极管可以形成在具有第一导电类型的掺杂区域的半导体衬底中。沟槽隔离结构可以横向围绕衬底顶表面处的掺杂区域的一部分。半导体层可以位于衬底的顶表面上。该半导体层可以在掺杂区域的限定部分上方具有肖特基势垒部分，并且在沟槽隔离结构之上的护套部分横向围绕肖特基势垒部分。肖特基势垒部分可以具有第一导电类型，并且防护部分可以具有不同于第一导电类型的第二导电类型。金属硅化物层可以覆盖半导体层。还公开了形成该肖特基势垒二极管的方法和肖特基势垒二极管的设计结构的实施例。

6. 发明申请

US20120193747A1 SCHOTTKY BARRIER DIODE, A METHOD OF FORMING THE DIODE AND A DESIGN STRUCTURE FOR THE DIODE 有权
标题翻译：肖特基二极管，形成二极管的方法和二极管的设计结构
公开(公告)号：US20120193747A1
公开(公告)日：2012-08-02
申请号：US13019716
申请日：2011-02-02
申请人： Robert M. Rassel , Mark E. Stidham
发明人： Robert M. Rassel , Mark E. Stidham
IPC分类号： H01L29/872 , G06F17/50 , H01L21/329
CPC分类号： H01L29/66143 , G06F17/5068 , H01L29/872
摘要： Disclosed are embodiments of a Schottky barrier diode. This diode can be formed in a semiconductor substrate having a doped region with a first conductivity type. A trench isolation structure can laterally surround a section of the doped region at the top surface of the substrate. A semiconductor layer can be positioned on the top surface of the substrate. This semiconductor layer can have a Schottky barrier portion over the defined section of the doped region and a guardring portion over the trench isolation structure laterally surrounding the Schottky barrier portion. The Schottky barrier portion can have the first conductivity type and the guarding portion can have a second conductivity type different from the first conductivity type. A metal silicide layer can overlie the semiconductor layer. Also disclosed are embodiments of a method of forming this Schottky barrier diode and of a design structure for the Schottky barrier diode.
摘要翻译：公开了肖特基势垒二极管的实施例。该二极管可以形成在具有第一导电类型的掺杂区域的半导体衬底中。沟槽隔离结构可以横向围绕衬底顶表面处的掺杂区域的一部分。半导体层可以位于衬底的顶表面上。该半导体层可以在掺杂区域的限定部分上方具有肖特基势垒部分，并且在沟槽隔离结构之上的护套部分横向围绕肖特基势垒部分。肖特基势垒部分可以具有第一导电类型，并且防护部分可以具有不同于第一导电类型的第二导电类型。金属硅化物层可以覆盖半导体层。还公开了形成该肖特基势垒二极管的方法和肖特基势垒二极管的设计结构的实施例。

7. 发明授权

US08421181B2 Schottky barrier diode with perimeter capacitance well junction 有权
标题翻译：肖特基势垒二极管，具有周边电容阱结
公开(公告)号：US08421181B2
公开(公告)日：2013-04-16
申请号：US12840791
申请日：2010-07-21
申请人： Frederick G. Anderson , Jenifer E. Lary , Robert M. Rassel , Mark E. Stidham
发明人： Frederick G. Anderson , Jenifer E. Lary , Robert M. Rassel , Mark E. Stidham
IPC分类号： H01L29/66
CPC分类号： H01L29/872 , H01L21/761 , H01L29/0619 , H01L29/0646 , H01L29/0692 , H01L29/66143
摘要： A Schottky barrier diode comprises a first-type substrate, a second-type well isolation region on the first-type substrate, and a first-type well region on the second-type well isolation region. With embodiments herein a feature referred to as a perimeter capacitance well junction ring is on the second-type well isolation region. A second-type well region is on the second-type well isolation region. The perimeter capacitance well junction ring is positioned between and separates the first-type well region and the second-type well region. A second-type contact region is on the second-type well region, and a first-type contact region contacts the inner portion of the first-type well region. The inner portion of the first-type well region is positioned within the center of the first-type contact region. Additionally, a first ohmic metallic layer is on the first-type contact region and a second ohmic metallic layer is on the first-type well region. The first ohmic metallic layer contacts the second ohmic metallic layer at a junction that makes up the Schottky barrier of the Schottky barrier diode.
摘要翻译：肖特基势垒二极管包括第一类型衬底，第一类型衬底上的第二类型阱隔离区域和第二类型阱隔离区域上的第一类型阱区域。在这里的实施例中，被称为周边电容阱接合环的特征在第二类型的隔离区域上。第二类型井区域位于第二类型井隔离区域上。周边电容阱接合环位于第一类型阱区域和第二类型阱区域之间并分离。第二类型接触区域位于第二类型阱区域上，并且第一类型接触区域接触第一类型阱区域的内部部分。第一类型阱区域的内部位于第一类型接触区域的中心内。此外，第一欧姆金属层位于第一类型接触区域上，第二欧姆金属层位于第一类型阱区域上。第一欧姆金属层在构成肖特基势垒二极管的肖特基势垒的结处接触第二欧姆金属层。

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