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1. 发明授权

US06326696B1 Electronic package with interconnected chips 失效
标题翻译：具有互连芯片的电子封装
公开(公告)号：US06326696B1
公开(公告)日：2001-12-04
申请号：US09018698
申请日：1998-02-04
申请人： Raymond Robert Horton , Alphonso Philip Lanzetta , Joseph Maryan Milewski , Lawrence S. Mok , Robert Kevin Montoye , Hussain Shaukatulla
发明人： Raymond Robert Horton , Alphonso Philip Lanzetta , Joseph Maryan Milewski , Lawrence S. Mok , Robert Kevin Montoye , Hussain Shaukatulla
IPC分类号： H01L2348
CPC分类号： H01L23/49822 , H01L23/49811 , H01L23/49833 , H01L24/45 , H01L24/48 , H01L2224/05599 , H01L2224/16145 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/854 , H01L2224/85439 , H01L2224/85444 , H01L2224/8547 , H01L2924/00014 , H01L2924/01039 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： An electronic package which includes a circuitized substrate with a cavity and a first semiconductor chip positioned therein. The first chip is electrically coupled to conductive members located on the circuitized substrate. A second semiconductor chip is positioned on and electrically coupled to the first chip.
摘要翻译：一种电子封装，其包括具有空腔的电路化基板和位于其中的第一半导体芯片。第一芯片电耦合到位于电路化基板上的导电构件。第二半导体芯片位于第一芯片上并电耦合到第一芯片。

2. 发明授权

US06306686B1 Method of fabricating an electronic package with interconnected chips 失效
标题翻译：制造具有互连芯片的电子封装的方法
公开(公告)号：US06306686B1
公开(公告)日：2001-10-23
申请号：US09487747
申请日：2000-01-19
申请人： Raymond Robert Horton , Alphonso Philip Lanzetta , Joseph Maryan Milewski , Lawrence S. Mok , Robert Kevin Montoye , Hussain Shaukatulla
发明人： Raymond Robert Horton , Alphonso Philip Lanzetta , Joseph Maryan Milewski , Lawrence S. Mok , Robert Kevin Montoye , Hussain Shaukatulla
IPC分类号： H01L2150
CPC分类号： H01L23/49822 , H01L23/49811 , H01L23/49833 , H01L24/45 , H01L24/48 , H01L2224/05599 , H01L2224/16145 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/854 , H01L2224/85439 , H01L2224/85444 , H01L2224/8547 , H01L2924/00014 , H01L2924/01039 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： An electronic package which includes a circuitized substrate with a cavity and a first semiconductor chip positioned therein. The first chip is electrically coupled to conductive members located on the circuitized substrate. A second semiconductor chip is positioned on and electrically coupled to the first chip.
摘要翻译：一种电子封装，其包括具有空腔的电路化基板和位于其中的第一半导体芯片。第一芯片电耦合到位于电路化基板上的导电构件。第二半导体芯片位于第一芯片上并电耦合到第一芯片。

3. 发明授权

US06806563B2 Composite capacitor and stiffener for chip carrier 失效
标题翻译：用于芯片载体的复合电容器和加强件
公开(公告)号：US06806563B2
公开(公告)日：2004-10-19
申请号：US10392615
申请日：2003-03-20
申请人： James Patrick Libous , Joseph Maryan Milewski
发明人： James Patrick Libous , Joseph Maryan Milewski
IPC分类号： H01L2352
CPC分类号： H01L23/49822 , H01L23/49838 , H01L23/50 , H01L2224/16 , H01L2924/01019 , H01L2924/01078 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311
摘要： A chip package comprises a substrate with a composite capacitor/stiffener on the substrate. In one embodiment of the present invention, the substrate comprises a plurality of dielectric layers and a plurality of metallic layers interlaced with the dielectric layers. One of the metallic layers is on a surface of the substrate. Another dielectric layer is adhered onto the one metallic layer. A metallic plate is adhered onto the other dielectric layer, opposite the one metallic layer. The metallic plate is electrically connected to power or ground. The one metallic layer is electrically connected to ground or power, respectively, such that the metallic plate, the other dielectric layer and the one metallic layer form a capacitor. The one metallic layer is joined to a respective one of the plurality of dielectric layers in a same manner as another of the plurality of metallic layers is joined to another, respective one of the plurality of dielectric layers. Other embodiments of the composite capacitor/stiffener are also disclosed.
摘要翻译：芯片封装包括在衬底上具有复合电容器/加强件的衬底。在本发明的一个实施例中，衬底包括多个电介质层和与电介质层交织的多个金属层。金属层中的一个位于基板的表面上。另一个电介质层粘附到一个金属层上。金属板粘附在另一个电介质层上，与一个金属层相对。金属板电连接到电源或接地。一个金属层分别电连接到地或电源，使得金属板，另一个介电层和一个金属层形成电容器。一个金属层以与多个金属层中的另一个金属层的另一个接合到多个电介质层中的相应一个电介质层的相同方式连接到多个电介质层中的相应一个。还公开了复合电容器/加强件的其它实施例。

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