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1. 发明授权

US08537625B2 Memory voltage regulator with leakage current voltage control 有权
标题翻译：内存电压调节器，具有漏电流电压控制
公开(公告)号：US08537625B2
公开(公告)日：2013-09-17
申请号：US13045294
申请日：2011-03-10
申请人： Ravindraraj Ramaraju , Shayan Zhang , Kenneth R. Burch , Charles E. Seaberg , Andrew C. Russell
发明人： Ravindraraj Ramaraju , Shayan Zhang , Kenneth R. Burch , Charles E. Seaberg , Andrew C. Russell
IPC分类号： G11C11/412
CPC分类号： G11C11/417 , G11C5/147 , G11C11/412 , G11C29/021 , G11C29/028
摘要： A voltage regulator for a memory that regulates a voltage provided to the memory cells based on a measured leakage current from a second set of memory cells. In one embodiment, based on the measured leakage current, the voltage to the cells is raised or lowered to control the amount of leakage current from the cells.
摘要翻译：一种用于存储器的电压调节器，其基于来自第二组存储器单元的测量的泄漏电流来调节提供给存储器单元的电压。在一个实施例中，基于测量的漏电流，提高或降低对电池的电压以控制来自电池的泄漏电流的量。

2. 发明申请

US20120230126A1 MEMORY VOLTAGE REGULATOR WITH LEAKAGE CURRENT VOLTAGE CONTROL 有权
标题翻译：具有漏电流电压控制的存储电压调节器
公开(公告)号：US20120230126A1
公开(公告)日：2012-09-13
申请号：US13045294
申请日：2011-03-10
申请人： Ravindraraj Ramaraju , Shayan Zhang , Kenneth R. Burch , Charles E. Seaberg , Andrew C. Russell
发明人： Ravindraraj Ramaraju , Shayan Zhang , Kenneth R. Burch , Charles E. Seaberg , Andrew C. Russell
IPC分类号： G11C5/14 , G11C7/14 , G11C7/00
CPC分类号： G11C11/417 , G11C5/147 , G11C11/412 , G11C29/021 , G11C29/028
摘要： A voltage regulator for a memory that regulates a voltage provided to the memory cells based on a measured leakage current from a second set of memory cells. In one embodiment, based on the measured leakage current, the voltage to the cells is raised or lowered to control the amount of leakage current from the cells.
摘要翻译：一种用于存储器的电压调节器，其基于来自第二组存储器单元的测量的泄漏电流来调节提供给存储器单元的电压。在一个实施例中，基于测量的漏电流，提高或降低对电池的电压以控制来自电池的泄漏电流的量。

3. 发明申请

US20120200336A1 ELECTRONIC CIRCUIT HAVING SHARED LEAKAGE CURRENT REDUCTION CIRCUITS 有权
标题翻译：具有共享漏电流减少电路的电子电路
公开(公告)号：US20120200336A1
公开(公告)日：2012-08-09
申请号：US13020565
申请日：2011-02-03
申请人： Ravindraraj Ramaraju , David R. Bearden , Andrew C. Russell , Shayan Zhang
发明人： Ravindraraj Ramaraju , David R. Bearden , Andrew C. Russell , Shayan Zhang
IPC分类号： H03K3/011 , G05F1/10
CPC分类号： H03K19/0008 , H03K19/0016
摘要： An electronic circuit includes a plurality of circuit blocks, a plurality of bias circuits, a switching circuit, and plurality of transistors. The plurality of circuit blocks each includes a high power terminal and a low power terminal. The switching circuit includes a plurality of switches for selectively coupling a bias circuit of the plurality of bias circuits to the low power terminal of a circuit block of the plurality of circuit blocks. Each bias circuit of the plurality of bias circuits is selectively couplable to the low power terminal of each of the plurality of circuit blocks. Each transistor of the plurality of transistors has a first current terminal coupled to a circuit ground terminal, and each transistor of the plurality of transistors has a control terminal for controlling the conductivity of the plurality of the transistors by a bias circuit of the plurality of bias circuits.
摘要翻译：电子电路包括多个电路块，多个偏置电路，开关电路和多个晶体管。多个电路块各自包括高功率端子和低功率端子。开关电路包括多个开关，用于将多个偏置电路的偏置电路选择性地耦合到多个电路块的电路块的低功率端子。多个偏置电路的每个偏置电路可以选择性地耦合到多个电路块中的每一个的低功率端子。多个晶体管的每个晶体管具有耦合到电路接地端子的第一电流端子，并且多个晶体管中的每个晶体管具有控制端子，用于通过多个偏置的偏置电路来控制多个晶体管的导电性电路。

4. 发明授权

US08566620B2 Data processing having multiple low power modes and method therefor 有权
标题翻译：具有多种低功率模式的数据处理及其方法
公开(公告)号：US08566620B2
公开(公告)日：2013-10-22
申请号：US12846042
申请日：2010-07-29
申请人： Andrew C. Russell , Ravindraraj Ramaraju , Shayan Zhang
发明人： Andrew C. Russell , Ravindraraj Ramaraju , Shayan Zhang
IPC分类号： G06F1/00
CPC分类号： G06F12/0804 , G06F1/3203 , G06F1/3275 , Y02D10/14
摘要： A method is provided for operating a data processing system having a memory. The memory is coupled between a first power supply voltage terminal for receiving a first variable potential and a second power supply voltage terminal for receiving a second variable potential. An initial difference between the first variable potential and the second variable potential is not less than a first voltage. The method comprises: receiving a command to transition the data processing system from a first power supply voltage to a second power supply voltage; changing the second variable potential so that a difference between the second variable potential and the first variable potential is greater than the first voltage; and after changing the second variable potential, changing the first variable potential, wherein a difference between the first variable potential and the second variable potential is not less than the first voltage.
摘要翻译：提供了一种用于操作具有存储器的数据处理系统的方法。存储器耦合在用于接收第一可变电位的第一电源电压端子和用于接收第二可变电位的第二电源电压端子之间。第一可变电位和第二可变电位之间的初始差不小于第一电压。该方法包括：接收将数据处理系统从第一电源电压转换到第二电源电压的命令; 改变第二可变电位，使得第二可变电位和第一可变电位之间的差大于第一电压; 并且在改变第二可变电位之后，改变第一可变电位，其中第一可变电位和第二可变电位之间的差不小于第一电压。

5. 发明授权

US08710916B2 Electronic circuit having shared leakage current reduction circuits 有权
标题翻译：具有共享泄漏电流降低电路的电子电路
公开(公告)号：US08710916B2
公开(公告)日：2014-04-29
申请号：US13020565
申请日：2011-02-03
申请人： Ravindraraj Ramaraju , David R. Bearden , Andrew C. Russell , Shayan Zhang
发明人： Ravindraraj Ramaraju , David R. Bearden , Andrew C. Russell , Shayan Zhang
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H03K19/0008 , H03K19/0016
摘要： An electronic circuit includes a plurality of circuit blocks, a plurality of bias circuits, a switching circuit, and plurality of transistors. The plurality of circuit blocks each includes a high power terminal and a low power terminal. The switching circuit includes a plurality of switches for selectively coupling a bias circuit of the plurality of bias circuits to the low power terminal of a circuit block of the plurality of circuit blocks. Each bias circuit of the plurality of bias circuits is selectively couplable to the low power terminal of each of the plurality of circuit blocks. Each transistor of the plurality of transistors has a first current terminal coupled to a circuit ground terminal, and each transistor of the plurality of transistors has a control terminal for controlling the conductivity of the plurality of the transistors by a bias circuit of the plurality of bias circuits.
摘要翻译：电子电路包括多个电路块，多个偏置电路，开关电路和多个晶体管。多个电路块各自包括高功率端子和低功率端子。开关电路包括多个开关，用于将多个偏置电路的偏置电路选择性地耦合到多个电路块的电路块的低功率端子。多个偏置电路的每个偏置电路可以选择性地耦合到多个电路块中的每一个的低功率端子。多个晶体管的每个晶体管具有耦合到电路接地端子的第一电流端子，并且多个晶体管中的每个晶体管具有控制端子，用于通过多个偏置的偏置电路来控制多个晶体管的导电性电路。

6. 发明申请

US20120030482A1 DATA PROCESSING HAVING MULTIPLE LOW POWER MODES AND METHOD THEREFOR 有权
标题翻译：具有多种低功耗模式的数据处理及其方法
公开(公告)号：US20120030482A1
公开(公告)日：2012-02-02
申请号：US12846042
申请日：2010-07-29
申请人： Andrew C. Russell , Ravindraraj Ramaraju , Shayan Zhang
发明人： Andrew C. Russell , Ravindraraj Ramaraju , Shayan Zhang
IPC分类号： G06F1/26 , G06F12/02
CPC分类号： G06F12/0804 , G06F1/3203 , G06F1/3275 , Y02D10/14
摘要： A method is provided for operating a data processing system having a memory. The memory is coupled between a first power supply voltage terminal for receiving a first variable potential and a second power supply voltage terminal for receiving a second variable potential. An initial difference between the first variable potential and the second variable potential is not less than a first voltage. The method comprises: receiving a command to transition the data processing system from a first power supply voltage to a second power supply voltage; changing the second variable potential so that a difference between the second variable potential and the first variable potential is greater than the first voltage; and after changing the second variable potential, changing the first variable potential, wherein a difference between the first variable potential and the second variable potential is not less than the first voltage.
摘要翻译：提供了一种用于操作具有存储器的数据处理系统的方法。存储器耦合在用于接收第一可变电位的第一电源电压端子和用于接收第二可变电位的第二电源电压端子之间。第一可变电位和第二可变电位之间的初始差不小于第一电压。该方法包括：接收将数据处理系统从第一电源电压转换到第二电源电压的命令; 改变第二可变电位，使得第二可变电位和第一可变电位之间的差大于第一电压; 并且在改变第二可变电位之后，改变第一可变电位，其中第一可变电位和第二可变电位之间的差不小于第一电压。

7. 发明授权

US08587356B2 Recoverable and reconfigurable pipeline structure for state-retention power gating 有权
标题翻译：用于状态保持功率门控的可恢复和可重新配置的管道结构
公开(公告)号：US08587356B2
公开(公告)日：2013-11-19
申请号：US13403597
申请日：2012-02-23
申请人： Shayan Zhang , William C. Moyer , Ravindraraj Ramaraju
发明人： Shayan Zhang , William C. Moyer , Ravindraraj Ramaraju
IPC分类号： H03K3/00
CPC分类号： H03K3/35606 , H03K3/356008
摘要： A system, electronic circuit, and method are disclosed. A method embodiment comprises receiving a control signal associated with a power gating operation mode of an electronic circuit, applying a reference voltage to the electronic circuit based upon the power gating operation mode, and maintaining data representing a state of a logic stage of the electronic circuit based upon the power gating operation mode. Maintaining comprises, in the described embodiment, storing data of a state of a first logic stage of the electronic circuit within a first storage element in a first power gating operation mode, and recovering data of a state of a second logic stage of the electronic circuit utilizing the data of the state of the first logic stage of the electronic circuit within the first storage element in a second power gating operation mode.
摘要翻译：公开了一种系统，电子电路和方法。方法实施例包括接收与电子电路的电源门控操作模式相关联的控制信号，基于电源门控操作模式将参考电压施加到电子电路，以及维护表示电子电路的逻辑级状态的数据基于电源门控操作模式。在所描述的实施例中，维护包括在第一电源门控操作模式中将电子电路的第一逻辑级的状态的数据存储在第一存储元件内，以及恢复电子电路的第二逻辑级的状态的数据在第二电源门控操作模式中利用第一存储元件内的电子电路的第一逻辑级的状态的数据。

8. 发明申请

US20130154707A1 RECOVERABLE AND RECONFIGURABLE PIPELINE STRUCTURE FOR STATE-RETENTION POWER GATING 有权
标题翻译：用于状态保持功率补偿的可恢复和可重新配置的管道结构
公开(公告)号：US20130154707A1
公开(公告)日：2013-06-20
申请号：US13403597
申请日：2012-02-23
申请人： Shayan Zhang , William C. Moyer , Ravindraraj Ramaraju
发明人： Shayan Zhang , William C. Moyer , Ravindraraj Ramaraju
IPC分类号： H03K3/00
CPC分类号： H03K3/35606 , H03K3/356008
摘要： A system, electronic circuit, and method are disclosed. A method embodiment comprises receiving a control signal associated with a power gating operation mode of an electronic circuit, applying a reference voltage to the electronic circuit based upon the power gating operation mode, and maintaining data representing a state of a logic stage of the electronic circuit based upon the power gating operation mode. Maintaining comprises, in the described embodiment, storing data of a state of a first logic stage of the electronic circuit within a first storage element in a first power gating operation mode, and recovering data of a state of a second logic stage of the electronic circuit utilizing the data of the state of the first logic stage of the electronic circuit within the first storage element in a second power gating operation mode.
摘要翻译：公开了一种系统，电子电路和方法。方法实施例包括接收与电子电路的电源门控操作模式相关联的控制信号，基于电源门控操作模式将参考电压施加到电子电路，以及维护表示电子电路的逻辑级状态的数据基于电源门控操作模式。在所描述的实施例中，维护包括在第一电源门控操作模式中将电子电路的第一逻辑级的状态的数据存储在第一存储元件内，以及恢复电子电路的第二逻辑级的状态的数据在第二电源门控操作模式中利用第一存储元件内的电子电路的第一逻辑级的状态的数据。

9. 发明授权

US08941427B2 Configurable flip-flop 有权
标题翻译：可配置的触发器
公开(公告)号：US08941427B2
公开(公告)日：2015-01-27
申请号：US13326685
申请日：2011-12-15
申请人： Shayan Zhang , Ravindraraj Ramaraju
发明人： Shayan Zhang , Ravindraraj Ramaraju
IPC分类号： H03K3/289
CPC分类号： H03K3/356156
摘要： A configurable flip-flop can be operated in a normal mode and a buffer mode. In the normal mode, the flip-flop latches data at the flip-flop input based on a clock signal. In the buffer mode, the flip-flop provides data at the flip-flop input to the flip-flop output, independent of the clock signal.
摘要翻译：可以在正常模式和缓冲模式下操作可配置的触发器。在正常模式下，触发器基于时钟信号在触发器输入端锁存数据。在缓冲模式下，触发器将触发器输入端的数据提供给触发器输出，与时钟信号无关。

10. 发明申请

US20130154708A1 CONFIGURABLE FLIP-FLOP 有权
标题翻译：可配置FLIP-FLOP
公开(公告)号：US20130154708A1
公开(公告)日：2013-06-20
申请号：US13326685
申请日：2011-12-15
申请人： Shayan Zhang , Ravindraraj Ramaraju
发明人： Shayan Zhang , Ravindraraj Ramaraju
IPC分类号： H03K3/289 , H03K3/286
CPC分类号： H03K3/356156
摘要： A configurable flip-flop can be operated in a normal mode and a buffer mode. In the normal mode, the flip-flop latches data at the flip-flop input based on a clock signal. In the buffer mode, the flip-flop provides data at the flip-flop input to the flip-flop output, independent of the clock signal.
摘要翻译：可以在正常模式和缓冲模式下操作可配置的触发器。在正常模式下，触发器基于时钟信号在触发器输入端锁存数据。在缓冲模式下，触发器将触发器输入端的数据提供给触发器输出，与时钟信号无关。

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