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1. 发明授权

US07984229B2 Pipelined tag and information array access with speculative retrieval of tag that corresponds to information access 有权
标题翻译：流水线标签和信息数组访问，与信息访问相对应的标签的推测检索
公开(公告)号：US07984229B2
公开(公告)日：2011-07-19
申请号：US11684529
申请日：2007-03-09
申请人： Ravindraraj Ramaraju , Ambica Ashok , David R. Bearden , Prashant U. Kenkare
发明人： Ravindraraj Ramaraju , Ambica Ashok , David R. Bearden , Prashant U. Kenkare
IPC分类号： G06F12/00
CPC分类号： G06F12/0895 , Y02D10/13
摘要： A cache design is described in which corresponding accesses to tag and information arrays are phased in time, and in which tags are retrieved (typically speculatively) from a tag array without benefit of an effective address calculation subsequently used for a corresponding retrieval from an information array. In some exploitations, such a design may allow cycle times (and throughput) of a memory subsystem to more closely match demands of some processor and computation system architectures. Our techniques seek to allow early (indeed speculative) retrieval from the tag array without delays that would otherwise be associated with calculation of an effective address eventually employed for a corresponding retrieval from the information array. Speculation can be resolved using the eventually calculated effective address or using separate functionality. In some embodiments, we use calculated effective addresses for way selection based on tags retrieved from the tag array.
摘要翻译：描述了一种高速缓存设计，其中对标签和信息数组的相应访问在时间上是相位的，并且其中从标签数组中检索（通常是推测性地）的标签，而不受随后用于从信息数组的相应检索的有效地址计算的益处。在一些开发中，这样的设计可以允许存储器子系统的周期时间（和吞吐量）更接近地匹配一些处理器和计算系统架构的需求。我们的技术旨在允许从标签数组中提前（确实是推测性的）检索，而不会延迟，否则将与从信息数组中相应检索最终采用的有效地址的计算相关联。可以使用最终计算的有效地址或使用单独的功能来解决投机。在一些实施例中，我们使用基于从标签阵列检索的标签的方法选择的计算的有效地址。

2. 发明申请

US20080222361A1 PIPELINED TAG AND INFORMATION ARRAY ACCESS WITH SPECULATIVE RETRIEVAL OF TAG THAT CORRESPONDS TO INFORMATION ACCESS 有权
标题翻译：管道标签和信息阵列访问与信息访问相关的标签的检索
公开(公告)号：US20080222361A1
公开(公告)日：2008-09-11
申请号：US11684529
申请日：2007-03-09
申请人： Ravindraraj Ramaraju , Ambica Ashok , David R. Bearden , Prashant U. Kenkare
发明人： Ravindraraj Ramaraju , Ambica Ashok , David R. Bearden , Prashant U. Kenkare
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , Y02D10/13
摘要： A cache design is described in which corresponding accesses to tag and information arrays are phased in time, and in which tags are retrieved (typically speculatively) from a tag array without benefit of an effective address calculation subsequently used for a corresponding retrieval from an information array. In some exploitations, such a design may allow cycle times (and throughput) of a memory subsystem to more closely match demands of some processor and computation system architectures. In some cases, phased access can be described as pipelined tag and information array access, though strictly speaking, indexing into the information array need not depend on results of the tag array access. Our techniques seek to allow early (indeed speculative) retrieval from the tag array without delays that would otherwise be associated with calculation of an effective address eventually employed for a corresponding retrieval from the information array. Speculation can be resolved using the eventually calculated effective address or using separate functionality. In some embodiments, we use calculated effective addresses for way selection based on tags retrieved from the tag array.
摘要翻译：描述了一种高速缓存设计，其中对标签和信息数组的相应访问在时间上是相位的，并且其中从标签数组中检索（通常是推测性地）的标签，而不受随后用于从信息数组的相应检索的有效地址计算的益处。在一些开发中，这样的设计可以允许存储器子系统的周期时间（和吞吐量）更接近地匹配一些处理器和计算系统架构的需求。在某些情况下，分阶段访问可以被描述为流水线标签和信息数组访问，但严格来说，索引到信息数组不需要依赖于标签数组访问的结果。我们的技术旨在允许从标签数组中提前（确实是推测性的）检索，而不会延迟，否则将与从信息数组中相应检索最终采用的有效地址的计算相关联。可以使用最终计算的有效地址或使用单独的功能来解决投机。在一些实施例中，我们使用基于从标签阵列检索的标签的方法选择的计算的有效地址。

3. 发明申请

US20130046928A1 Memory Management Unit Tag Memory 有权
标题翻译：内存管理单元标签内存
公开(公告)号：US20130046928A1
公开(公告)日：2013-02-21
申请号：US13213900
申请日：2011-08-19
申请人： Ravindraraj Ramaraju , David R. Bearden , Prashant U. Kenkare , Jogendra C. Sarker
发明人： Ravindraraj Ramaraju , David R. Bearden , Prashant U. Kenkare , Jogendra C. Sarker
IPC分类号： G06F12/02
CPC分类号： G06F12/1027 , G06F9/355 , G06F9/3824 , G06F9/3832 , G11C15/04
摘要： A method and data processing system for accessing an entry in a memory array by placing a tag memory unit (114) in parallel with an operand adder circuit (112) to enable tag lookup and generation of speculative way hit/miss information (126) directly from the operands (111, 113) without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands (111, 113) are applied with a carry-out value (Cout48) to a content-addressable memory array (114) to generate two speculative hit/miss signals. A sum value (EA51) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output (126).
摘要翻译：一种方法和数据处理系统，用于通过将标记存储器单元（114）与操作数加法器电路（112）并行放置来访问存储器阵列中的入口，以使标签查找和直接产生投机方式命中/未命中信息（126）不使用操作数加法器的输出和从操作数（111,113）中读出。将来自操作数（111,113）的PGZ编码的地址位（0:51）与进位值（Cout48）一起施加到内容寻址存储器阵列（114），以产生两个推测的命中/未命中信号。从最低有效基址和偏移地址位计算的和值（EA51）确定选择哪种推测性命中/未命中信号用于输出（126）。

4. 发明授权

US07843218B1 Data latch with structural hold 有权
标题翻译：数据锁存结构保持
公开(公告)号：US07843218B1
公开(公告)日：2010-11-30
申请号：US12607657
申请日：2009-10-28
申请人： Ravindraraj Ramaraju , David R. Bearden , Cody B. Croxton , Prashant U. Kenkare
发明人： Ravindraraj Ramaraju , David R. Bearden , Cody B. Croxton , Prashant U. Kenkare
IPC分类号： H03K19/173
CPC分类号： G01R31/318541
摘要： A multiplexed data flip-flop circuit (500) is described in which a multiplexer (510) outputs functional or scan data, a master latch (520) generates a master latch output signal at a hold time under control of a master clock signal, a slave latch (540) generates a flip flop output signal at a launch time under control of a slave clock signal, clock generation circuitry (550) generates a second clock signal that has a DC state during a functional mode and has a switching state during a scan mode, and data propagation logic circuitry (564) uses the first and second clock signals to generate the master and slave clock signals during a scan mode to delay the launch time of the slave latch with respect to the hold time of the master latch.
摘要翻译：描述了多路复用数据触发器电路（500），其中复用器（510）输出功能或扫描数据，主锁存器（520）在主时钟信号的控制下在保持时间产生主锁存器输出信号，从锁存器（540）在从时钟信号的控制下在启动时产生触发器输出信号，时钟产生电路（550）产生在功能模式期间具有DC状态的第二时钟信号，并且在第一时钟信号期间具有开关状态扫描模式和数据传播逻辑电路（564）在扫描模式期间使用第一和第二时钟信号来产生主时钟信号和从时钟信号，以相对于主锁存器的保持时间延迟从锁存器的启动时间。

5. 发明授权

US09021194B2 Memory management unit tag memory 有权
标题翻译：内存管理单元标签内存
公开(公告)号：US09021194B2
公开(公告)日：2015-04-28
申请号：US13213900
申请日：2011-08-19
申请人： Ravindraraj Ramaraju , David R. Bearden , Prashant U. Kenkare , Jogendra C. Sarker
发明人： Ravindraraj Ramaraju , David R. Bearden , Prashant U. Kenkare , Jogendra C. Sarker
IPC分类号： G06F9/355 , G06F9/38 , G06F12/10
CPC分类号： G06F12/1027 , G06F9/355 , G06F9/3824 , G06F9/3832 , G11C15/04
摘要： A method and data processing system for accessing an entry in a memory array by placing a tag memory unit (114) in parallel with an operand adder circuit (112) to enable tag lookup and generation of speculative way hit/miss information (126) directly from the operands (111, 113) without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands (111, 113) are applied with a carry-out value (Cout48) to a content-addressable memory array (114) to generate two speculative hit/miss signals. A sum value (EA51) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output (126).
摘要翻译：一种方法和数据处理系统，用于通过将标记存储器单元（114）与操作数加法器电路（112）并行放置来访问存储器阵列中的入口，以使标签查找和直接产生投机方式命中/未命中信息（126）不使用操作数加法器的输出和从操作数（111,113）中读出。将来自操作数（111,113）的PGZ编码的地址位（0:51）与进位值（Cout48）一起施加到内容寻址存储器阵列（114），以产生两个推测的命中/未命中信号。从最低有效基址和偏移地址位计算的和值（EA51）确定选择哪种推测性命中/未命中信号用于输出（126）。

6. 发明授权

US08943292B2 System and method for memory array access with fast address decoder 有权
标题翻译：具有快速地址解码器的存储器阵列访问的系统和方法
公开(公告)号：US08943292B2
公开(公告)日：2015-01-27
申请号：US11552817
申请日：2006-10-25
申请人： Ravindraraj Ramaraju , David R. Bearden , Prashant U. Kenkare
发明人： Ravindraraj Ramaraju , David R. Bearden , Prashant U. Kenkare
IPC分类号： G06F12/02 , G06F9/355 , G06F9/345
CPC分类号： G06F9/355 , G06F9/345
摘要： A method includes storing a first transaction entry to a first software configurable storage location, storing a second transaction entry to a second software configurable storage location, determining that a first transaction indicated by the first transaction entry has occurred, determining that a second transaction indicated by the second transaction entry has occurred subsequent to the first transaction, and, in response to determining that the first transaction occurred and the second transaction occurred, storing at least one transaction attribute captured during at least one clock cycle subsequent to the second transaction. The first and second software configurable storage locations may be located in a trace buffer, where the at least one transaction attribute is stored to the trace buffer and overwrites the first and second transaction attributes. Each transaction entry may include a dead cycle field, a consecutive transaction requirement field, and a last entry field.
摘要翻译：一种方法包括将第一交易条目存储到第一软件可配置存储位置，将第二交易条目存储到第二软件可配置存储位置，确定由第一交易条目指示的第一交易已经发生，确定由第一交易条目指示的第二交易第二交易条目已经在第一交易之后发生，并且响应于确定第一交易发生和第二交易发生，存储在第二交易之后的至少一个时钟周期期间捕获的至少一个交易属性。第一和第二软件可配置存储位置可以位于跟踪缓冲器中，其中至少一个事务属性被存储到跟踪缓冲器并且覆盖第一和第二事务属性。每个交易条目可以包括死循环字段，连续交易需求字段和最后输入字段。

7. 发明授权

US07292495B1 Integrated circuit having a memory with low voltage read/write operation 有权
标题翻译：具有低电压读/写操作的存储器的集成电路
公开(公告)号：US07292495B1
公开(公告)日：2007-11-06
申请号：US11427610
申请日：2006-06-29
申请人： Prashant U. Kenkare , Andrew C. Russell , David R. Bearden , James D. Burnett , Troy L. Cooper , Shayan Zhang
发明人： Prashant U. Kenkare , Andrew C. Russell , David R. Bearden , James D. Burnett , Troy L. Cooper , Shayan Zhang
IPC分类号： G11C7/00
CPC分类号： G11C11/417 , G11C5/147 , G11C11/419
摘要： An integrated circuit with a low voltage read/write operation is provided. The integrated circuit may include a processor and a plurality of memory cells organized in rows and columns and coupled to the processor, wherein a row of memory cells comprises a word line and all of the memory cells coupled to the word line, and wherein a column of memory cells comprises a bit line and all of the memory cells coupled to the bit line. The integrated circuit may further include a first power supply voltage terminal for receiving a first power supply voltage, wherein the first power supply voltage is provided to power the processor, and wherein the first power supply voltage is provided to power the plurality of memory cells during a first access operation of the plurality of memory cells. The integrated circuit may further include a second power supply voltage terminal for receiving a second power supply voltage higher than the first power supply voltage, wherein the second power supply voltage is provided to power the plurality of memory cells during a second access operation of the plurality of memory cells.
摘要翻译：提供具有低电压读/写操作的集成电路。集成电路可以包括处理器和以行和列组织并且耦合到处理器的多个存储单元，其中存储单元行包括字线和耦合到字线的所有存储器单元，并且其中列的存储器单元包括位线和耦合到位线的所有存储器单元。集成电路还可以包括用于接收第一电源电压的第一电源电压端子，其中提供第一电源电压以为处理器供电，并且其中提供第一电源电压以在多个存储器单元期间供电多个存储单元的第一访问操作。集成电路还可以包括用于接收高于第一电源电压的第二电源电压的第二电源电压端子，其中提供第二电源电压以在多个存储器单元的第二访问操作期间为多个存储器单元供电的记忆细胞。

8. 发明授权

US07542369B2 Integrated circuit having a memory with low voltage read/write operation 有权
标题翻译：具有低电压读/写操作的存储器的集成电路
公开(公告)号：US07542369B2
公开(公告)日：2009-06-02
申请号：US11863961
申请日：2007-09-28
申请人： Prashant U. Kenkare , Andrew C. Russell , David R. Bearden , James D. Burnett , Troy L. Cooper , Shayan Zhang
发明人： Prashant U. Kenkare , Andrew C. Russell , David R. Bearden , James D. Burnett , Troy L. Cooper , Shayan Zhang
IPC分类号： G11C11/00
CPC分类号： G11C11/417 , G11C5/147 , G11C11/419
摘要： An integrated circuit with a low voltage read/write operation is provided. The integrated circuit may include a processor and a plurality of memory cells organized in rows and columns and coupled to the processor, wherein a row of memory cells comprises a word line and all of the memory cells coupled to the word line, and wherein a column of memory cells comprises a bit line and all of the memory cells coupled to the bit line. The integrated circuit may further include a first power supply voltage terminal for receiving a first power supply voltage, wherein the first power supply voltage is provided to power the processor, and wherein the first power supply voltage is provided to power the plurality of memory cells during a first access operation of the plurality of memory cells. The integrated circuit may further include a second power supply voltage terminal for receiving a second power supply voltage higher than the first power supply voltage, wherein the second power supply voltage is provided to power the plurality of memory cells during a second access operation of the plurality of memory cells.
摘要翻译：提供具有低电压读/写操作的集成电路。集成电路可以包括处理器和以行和列组织并且耦合到处理器的多个存储单元，其中存储单元行包括字线和耦合到字线的所有存储器单元，并且其中列的存储器单元包括位线和耦合到位线的所有存储器单元。集成电路还可以包括用于接收第一电源电压的第一电源电压端子，其中提供第一电源电压以为处理器供电，并且其中提供第一电源电压以在多个存储器单元期间供电多个存储单元的第一访问操作。集成电路还可以包括用于接收高于第一电源电压的第二电源电压的第二电源电压端子，其中提供第二电源电压以在多个存储器单元的第二访问操作期间为多个存储器单元供电的记忆细胞。

9. 发明授权

US09367475B2 System and method for cache access 有权
标题翻译：用于缓存访问的系统和方法
公开(公告)号：US09367475B2
公开(公告)日：2016-06-14
申请号：US13440728
申请日：2012-04-05
申请人： Ravindraraj Ramaraju , David R. Bearden , Andrew C. Russell
发明人： Ravindraraj Ramaraju , David R. Bearden , Andrew C. Russell
IPC分类号： G06F12/00 , G06F13/00 , G06F12/08 , G06F1/32
CPC分类号： G06F12/0895 , G06F1/3225 , G06F1/3275 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： The rows of a cache are generally maintained in a low power state. In response to a memory access operation, the data processor predicts a plurality of cache rows that may be targeted by the operation, and transitions each of the plurality of cache rows to an active state to prepare them for access. The plurality of cache rows are predicted based on speculatively decoding a portion of a base address and a corresponding portion of an offset without performing a full addition of the portions. Because a full addition is not performed, the speculative decoding can be performed at sufficient speed to allow the set of rows to be transitioned to the active state before full decoding of the memory address is completed. The cache row associated with the memory address is therefore ready for access when decoding is complete, maintaining low latency for cache accesses.
摘要翻译：缓存的行通常维持在低功率状态。响应于存储器访问操作，数据处理器预测可能由操作定向的多个高速缓存行，并且将多个高速缓存行中的每一个转换为活动状态以准备它们进行访问。基于对基本地址的一部分和偏移的对应部分的推测性解码来预测多个高速缓存行，而不执行部分的完全添加。由于没有执行完全相加，所以可以以足够的速度执行推测解码，以便在存储器地址的完全解码完成之前允许该组行转换到活动状态。因此，当解码完成时，与存储器地址相关联的高速缓存行可以进行访问，从而保持高速缓存访问的低延迟。

10. 发明申请

US20120200336A1 ELECTRONIC CIRCUIT HAVING SHARED LEAKAGE CURRENT REDUCTION CIRCUITS 有权
标题翻译：具有共享漏电流减少电路的电子电路
公开(公告)号：US20120200336A1
公开(公告)日：2012-08-09
申请号：US13020565
申请日：2011-02-03
申请人： Ravindraraj Ramaraju , David R. Bearden , Andrew C. Russell , Shayan Zhang
发明人： Ravindraraj Ramaraju , David R. Bearden , Andrew C. Russell , Shayan Zhang
IPC分类号： H03K3/011 , G05F1/10
CPC分类号： H03K19/0008 , H03K19/0016
摘要： An electronic circuit includes a plurality of circuit blocks, a plurality of bias circuits, a switching circuit, and plurality of transistors. The plurality of circuit blocks each includes a high power terminal and a low power terminal. The switching circuit includes a plurality of switches for selectively coupling a bias circuit of the plurality of bias circuits to the low power terminal of a circuit block of the plurality of circuit blocks. Each bias circuit of the plurality of bias circuits is selectively couplable to the low power terminal of each of the plurality of circuit blocks. Each transistor of the plurality of transistors has a first current terminal coupled to a circuit ground terminal, and each transistor of the plurality of transistors has a control terminal for controlling the conductivity of the plurality of the transistors by a bias circuit of the plurality of bias circuits.
摘要翻译：电子电路包括多个电路块，多个偏置电路，开关电路和多个晶体管。多个电路块各自包括高功率端子和低功率端子。开关电路包括多个开关，用于将多个偏置电路的偏置电路选择性地耦合到多个电路块的电路块的低功率端子。多个偏置电路的每个偏置电路可以选择性地耦合到多个电路块中的每一个的低功率端子。多个晶体管的每个晶体管具有耦合到电路接地端子的第一电流端子，并且多个晶体管中的每个晶体管具有控制端子，用于通过多个偏置的偏置电路来控制多个晶体管的导电性电路。

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