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1. 发明授权

US06849153B2 Removal of post-rie polymer on A1/CU metal line 有权
标题翻译：去除A1 / CU金属线上的后聚合物
公开(公告)号：US06849153B2
公开(公告)日：2005-02-01
申请号：US09204706
申请日：1998-12-03
申请人： Ravikumar Ramachandran , Wesley Natzle , Martin Gutsche , Hiroyuki Akatsu , Chien Yu
发明人： Ravikumar Ramachandran , Wesley Natzle , Martin Gutsche , Hiroyuki Akatsu , Chien Yu
IPC分类号： H01L21/302 , G03F7/42 , H01L21/02 , H01L21/027 , H01L21/306 , H01L21/3065 , H01L21/3205 , H01L21/3213 , C23F1/08
CPC分类号： H01L21/02071 , H01L21/02054 , H01L21/31138 , H01L21/32136 , Y10S134/902
摘要： A method for removal of post reactive ion etch sidewall polymer rails on a Al/Cu metal line of a semiconductor or microelectronic composite structure comprising: 1) supplying a mixture of an etching gas and an acid neutralizing gas into a vacuum chamber in which said composite structure is supported to form a water soluble material of sidewall polymer rails left behind on the Al/Cu metal line from the RIE process; removing the water soluble material with deionized water; and removing photo-resist from said composite structure by either a water-only plasma process or a chemical down stream etching method; or 2) forming a water-only plasma process to strip the photo-resist layer of a semiconductor or microelectronic composite structure previously subjected to a RIE process; supplying a mixture of an etching gas and an acid neutralizing gas into a vacuum chamber on which said structure is supported to form a water soluble material of saidwall polymer rails left behind on the Al/Cu metal line from the RIE process; and removing the water soluble material with deionized water.
摘要翻译：一种用于去除在半导体或微电子复合结构的Al / Cu金属线上的反应活性离子蚀刻侧壁聚合物轨道的方法，包括：1）将蚀刻气体和酸中和气体的混合物供应到真空室中，其中所述复合材料结构被支撑以形成从RIE工艺在Al / Cu金属线上留下的侧壁聚合物轨道的水溶性材料; 用去离子水去除水溶性物质; 以及通过水纯等离子体工艺或化学下游蚀刻方法从所述复合结构中除去光致抗蚀剂; 或2）形成仅水性等离子体工艺以剥离先前经受RIE工艺的半导体或微电子复合结构的光致抗蚀剂层;将蚀刻气体和酸中和气体的混合物供应到真空室中，在真空室中，被支撑以形成从RIE工艺在Al / Cu金属线上留下的所述壁聚合物轨道的水溶性材料; 并用去离子水去除水溶性物质。

2. 发明授权

US5980770A Removal of post-RIE polymer on Al/Cu metal line 失效
标题翻译：在Al / Cu金属线上去除RIE后聚合物
公开(公告)号：US5980770A
公开(公告)日：1999-11-09
申请号：US061565
申请日：1998-04-16
申请人： Ravikumar Ramachandran , Wesley Natzle , Martin Gutsche , Hiroyuki Akatsu , Chien Yu
发明人： Ravikumar Ramachandran , Wesley Natzle , Martin Gutsche , Hiroyuki Akatsu , Chien Yu
IPC分类号： H01L21/302 , H01L21/02 , H01L21/3213 , C03C25/06 , C23F1/12
CPC分类号： H01L21/02071 , H01L21/31138 , H01L21/32136 , Y10S438/906
摘要： A method for removal of post reactive ion etch sidewall polymer rails on a Al/Cu metal line of a semiconductor or microelectronic composite structure comprising:1) supplying a mixture of an etching gas and an acid neutralizing gas into a vacuum chamber in which said composite structure is supported to form a water soluble material of sidewall polymer rails left behind on the Al/Cu metal line from the RIE process; removing the water soluble material with deionized water; and removing photo-resist from said composite structure by either a water-only plasma process or a chemical down stream etching method; or2) forming a water-only plasma process to strip the photo-resist layer of a semiconductor or microelectronic composite structure previously subjected to a RIE process;supplying a mixture of an etching gas and an acid neutralizing gas into a vacuum chamber on which said structure is supported to form a water soluble material of saidwall polymer rails left behind on the Al/Cu metal line from the RIE process; andremoving the water soluble material with deionized water.
摘要翻译：一种用于去除在半导体或微电子复合结构的Al / Cu金属线上的反应活性离子蚀刻侧壁聚合物轨道的方法，包括：1）将蚀刻气体和酸中和气体的混合物供应到真空室中，其中所述复合材料结构被支撑以形成从RIE工艺在Al / Cu金属线上留下的侧壁聚合物轨道的水溶性材料; 用去离子水去除水溶性物质; 以及通过水纯等离子体工艺或化学下游蚀刻方法从所述复合结构中除去光致抗蚀剂; 或2）形成仅水等离子体工艺以剥离先前经过RIE工艺的半导体或微电子复合结构的光致抗蚀剂层; 将一种蚀刻气体和酸中和气体的混合物供给到所述结构被支撑的真空室中，以形成从RIE工艺在Al / Cu金属管线上留下的所述壁聚合物轨道的水溶性材料; 并用去离子水除去水溶性物质。

3. 发明授权

US5807439A Apparatus and method for improved washing and drying of semiconductor wafers 失效
公开(公告)号：US5807439A
公开(公告)日：1998-09-15
申请号：US939547
申请日：1997-09-29
申请人： Hiroyuki Akatsu , Ravikumar Ramachandran
发明人： Hiroyuki Akatsu , Ravikumar Ramachandran
IPC分类号： H01L21/304 , H01L21/00 , F26B7/00
CPC分类号： H01L21/67028 , H01L21/67023 , Y10S134/902
摘要： Apparatus and method are provided for improved washing and drying of semiconductor wafers utilizing an enhanced "Marangoni effect" flow of liquid off of the wafers for superior prevention of watermarks (water spots) on integrated circuits (ICs) on the wafers. The apparatus includes a housing 12 which may be hermetically sealed, an open-top wash tank 60 within a lower part of the housing, a moveable rack 16 for holding the wafers either in the tank for washing or in an upper part of the housing for drying, apparatus 34 for supplying chilled (near freezing) de-ionized water (DIW) to a lower part of the tank, the DIW flowing within the tank and overflowing the top thereof, a pump 20 for draining overflowing DIW from the housing, and apparatus 40 for supplying to the housing organic vapor such as isopropyl alcohol (IPA) in a dry gas such as nitrogen. During wafer drying operation of the apparatus the pressure within the housing is kept at about one Torr or less.

4. 发明授权

US06723611B2 Vertical hard mask 失效
标题翻译：垂直硬面罩
公开(公告)号：US06723611B2
公开(公告)日：2004-04-20
申请号：US10241225
申请日：2002-09-10
申请人： Hiroyuki Akatsu , Oleg Gluschenkov , Porshia S. Parkinson , Ravikumar Ramachandran , Helmut Horst Tews , Kenneth T. Settlemyer, Jr.
发明人： Hiroyuki Akatsu , Oleg Gluschenkov , Porshia S. Parkinson , Ravikumar Ramachandran , Helmut Horst Tews , Kenneth T. Settlemyer, Jr.
IPC分类号： H01L2120
CPC分类号： H01L27/1087
摘要： In the course of forming a trench capacitor or similar structure, the sidewalls of an aperture in a substrate are lined with a film stack containing a diffusion barrier; an upper portion of the outer layer is stripped, so that the upper and lower portions have different materials exposed; the lower portion of the film stack is stripped while the upper portion is protected by a hardmask layer; a diffusion step is performed in the lower portion while the upper portion is protected; and a selected material such as hemispherical grained silicon is deposited selectively on the lower portion while the exposed surface of the upper portion is a material on which the selected material forms poorly, so that the diffusing material penetrates and the selected material is formed only on the lower portion.
摘要翻译：在形成沟槽电容器或类似结构的过程中，衬底中的孔的侧壁衬有包含扩散阻挡层的膜堆叠; 外层的上部被剥离，使得上部和下部具有不同的材料暴露; 薄膜堆叠的下部被剥离，同时上部被硬掩模层保护; 在上部被保护的同时在下部进行扩散步骤; 并且选择性地将选择的材料如半球形硅沉积在下部上，而上部的暴露表面是选择的材料形成不良的材料，使得扩散材料渗透，并且所选择的材料仅形成在下部。

5. 发明授权

US5932493A Method to minimize watermarks on silicon substrates 失效
标题翻译：最小化硅衬底上的水印的方法
公开(公告)号：US5932493A
公开(公告)日：1999-08-03
申请号：US929590
申请日：1997-09-15
申请人： Hiroyuki Akatsu , Ronald Hoyer , Ravikumar Ramachandran
发明人： Hiroyuki Akatsu , Ronald Hoyer , Ravikumar Ramachandran
IPC分类号： H01L21/304 , H01L21/306 , H01L21/00
CPC分类号： H01L21/02052
摘要： Formation of watermarks during semiconductor processing can be prevented by rinsing silicon wafers in an organic solvent prior to drying. Water droplets on the silicon wafer surface are taken up by the solvent and film is formed over the wafer surface. Following this rinse, the wafer may be subjected to standard IPA-based drying techniques.
摘要翻译：可以通过在干燥之前冲洗有机溶剂中的硅晶片来防止在半导体加工期间形成水印。硅晶片表面上的水滴被溶剂吸收，并且在晶片表面上形成膜。在该冲洗之后，可以对晶片进行标准的基于IPA的干燥技术。

6. 发明授权

US06887761B1 Vertical semiconductor devices 失效
标题翻译：垂直半导体器件
公开(公告)号：US06887761B1
公开(公告)日：2005-05-03
申请号：US10708647
申请日：2004-03-17
申请人： Hiroyuki Akatsu , Thomas W. Dyer , Ravikumar Ramachandran , Kenneth T. Settlemyer, Jr.
发明人： Hiroyuki Akatsu , Thomas W. Dyer , Ravikumar Ramachandran , Kenneth T. Settlemyer, Jr.
IPC分类号： H01L21/336 , H01L21/762 , H01L29/78 , H01I29/76
CPC分类号： H01L29/66666 , H01L21/2257 , H01L21/76224 , H01L29/7827
摘要： A method and structure for increasing the threshold voltage of vertical semiconductor devices. The method comprises creating a deep trench in a substrate whose semiconductor material has an orientation plane perpendicular to the surface of the substrate. Then, vertical transistors are formed around and along the depth of the deep trench. Next, two shallow trench isolation are formed such that they sandwich the deep trench in an active region and the two shallow trench isolation regions abut the active region via planes perpendicular to the orientation plane. Then, the channel regions of the vertical transistors are exposed to the atmosphere in the deep trench and then chemically etched to planes parallel to the orientation plane. Then, a gate dielectric layer is formed on the wall of the deep trench. Finally, the deep trench is filled with poly-silicon to form the gate for the vertical transistors.
摘要翻译：一种用于增加垂直半导体器件的阈值电压的方法和结构。该方法包括在其半导体材料具有垂直于衬底表面的取向平面的衬底中形成深沟槽。然后，在深沟槽的深度周围形成垂直晶体管。接下来，形成两个浅沟槽隔离，使得它们在有源区域中夹住深沟槽，并且两个浅沟槽隔离区域经由垂直于取向平面的平面邻接有源区。然后，垂直晶体管的沟道区域暴露在深沟槽中的大气中，然后化学蚀刻到平行于取向平面的平面上。然后，在深沟槽的壁上形成栅极电介质层。最后，深沟槽充满多晶硅，形成垂直晶体管的栅极。

7. 发明授权

US5934299A Apparatus and method for improved washing and drying of semiconductor wafers 失效
标题翻译：用于改善半导体晶片的洗涤和干燥的装置和方法
公开(公告)号：US5934299A
公开(公告)日：1999-08-10
申请号：US95985
申请日：1998-06-11
申请人： Hiroyuki Akatsu , Ravikumar Ramachandran
发明人： Hiroyuki Akatsu , Ravikumar Ramachandran
IPC分类号： H01L21/304 , H01L21/00 , B08B3/00
CPC分类号： H01L21/67028 , H01L21/67023 , Y10S134/902
摘要： Apparatus and method are provided for improved washing and drying of semiconductor wafers utilizing an enhanced "Marangoni effect" flow of liquid off of the wafers for superior prevention of watermarks (water spots) on integrated circuits (ICs) on the wafers. The apparatus includes a housing 12 which may be hermetically sealed, an open-top wash tank 60 within a lower part of the housing, a moveable rack 16 for holding the wafers either in the tank for washing or in an upper part of the housing for drying, apparatus 34 for supplying chilled (near freezing) de-ionized water (DIW) to a lower part of the tank, the DIW flowing within the tank and overflowing the top thereof, a pump 20 for draining overflowing DIW from the housing, and apparatus 40 for supplying to the housing organic vapor such as isopropyl alcohol (IPA) in a dry gas such as nitrogen. During wafer drying operation of the apparatus the pressure within the housing is kept at about one Torr or less.
摘要翻译：提供了用于利用晶片的液体增强的“马兰戈尼效应”流动来改善半导体晶片的洗涤和干燥的装置和方法，以优越地防止晶片上的集成电路（IC）上的水印（水斑）。该装置包括可以气密密封的壳体12，在壳体的下部内的开放式清洗罐60，用于将晶片保持在用于洗涤的罐中或在壳体的上部中的可移动的支架16 干燥装置34，用于向罐的下部供应冷冻（近冷冻）去离子水（DIW），DIW在罐内流动并溢出其顶部;泵20，用于从壳体排出溢流的DIW;以及用于在诸如氮气的干燥气体中供应到壳体有机蒸气如异丙醇（IPA）的装置40。在设备的晶片干燥操作期间，壳体内的压力保持在约1托或更低。

8. 发明申请

US20130330899A1 PREVENTING FULLY SILICIDED FORMATION IN HIGH-K METAL GATE PROCESSING 审中-公开
标题翻译：防止高K金属加工过程中的完全硅化物形成
公开(公告)号：US20130330899A1
公开(公告)日：2013-12-12
申请号：US13527063
申请日：2012-06-19
申请人： Huiming Bu , Ming Cai , Kevin K. Chan , Dechao Guo , Ravikumar Ramachandran , Liyang Song , Chun-Chen Yeh
发明人： Huiming Bu , Ming Cai , Kevin K. Chan , Dechao Guo , Ravikumar Ramachandran , Liyang Song , Chun-Chen Yeh
IPC分类号： H01L21/336 , H01L21/04
CPC分类号： H01L29/78 , H01L29/4966 , H01L29/51 , H01L29/665 , H01L29/66628
摘要： A method of forming gate stack structure for a transistor device includes forming a gate dielectric layer over a substrate; forming a first silicon gate layer over the gate dielectric layer; forming a dopant-rich monolayer over the first silicon gate layer; and forming a second silicon gate layer over the dopant-rich monolayer, wherein the dopant-rich monolayer prevents silicidation of the first silicon gate layer during silicidation of the second silicon gate layer.
摘要翻译：一种形成用于晶体管器件的栅叠层结构的方法包括在衬底上形成栅介电层; 在所述栅极介电层上形成第一硅栅极层; 在所述第一硅栅极层上形成富含掺杂剂的单层; 以及在所述富掺杂剂单层上形成第二硅栅极层，其中所述富掺杂剂层在所述第二硅栅极层的硅化期间防止所述第一硅栅极层的硅化。

9. 发明申请

US20120175711A1 Self-Aligned Contacts for High k/Metal Gate Process Flow 有权
标题翻译：用于高k /金属栅极工艺流程的自对准触点
公开(公告)号：US20120175711A1
公开(公告)日：2012-07-12
申请号：US12987221
申请日：2011-01-10
申请人： Ravikumar Ramachandran , Ramachandra Divakaruni , Ying Li
发明人： Ravikumar Ramachandran , Ramachandra Divakaruni , Ying Li
IPC分类号： H01L29/772 , H01L21/283
CPC分类号： H01L29/401 , H01L21/76895 , H01L21/76897 , H01L29/49 , H01L29/4983 , H01L29/51 , H01L29/66545 , H01L29/6656
摘要： A semiconductor structure is provided that includes a semiconductor substrate having a plurality of gate stacks located on a surface of the semiconductor substrate. Each gate stack includes, from bottom to top, a high k gate dielectric layer, a work function metal layer and a conductive metal. A spacer is located on sidewalls of each gate stack and a self-aligned dielectric liner is present on an upper surface of each spacer. A bottom surface of each self-aligned dielectric liner is present on an upper surface of a semiconductor metal alloy. A contact metal is located between neighboring gate stacks and is separated from each gate stack by the self-aligned dielectric liner. The structure also includes another contact metal having a portion that is located on and in direct contact with an upper surface of the contact metal and another portion that is located on and in direct contact with the conductive metal of one of the gate stacks. Methods of forming the semiconductor structure using a replacement gate and a non-replacement gate scheme are also disclosed.
摘要翻译：提供一种半导体结构，其包括具有位于半导体衬底的表面上的多个栅极叠层的半导体衬底。每个栅极堆叠包括从底部到顶部的高k栅极电介质层，功函数金属层和导电金属。间隔件位于每个栅极堆叠的侧壁上，并且自对准电介质衬垫存在于每个间隔件的上表面上。每个自对准电介质衬垫的底表面存在于半导体金属合金的上表面上。接触金属位于相邻的栅极堆叠之间，并通过自对准电介质衬垫与每个栅极堆叠分离。该结构还包括另一个接触金属，其具有位于接触金属的上表面上且与触头金属的上表面直接接触的部分，以及位于与其中一个栅极叠层的导电金属直接接触的另一部分。还公开了使用替换栅极和非替代栅极方案形成半导体结构的方法。

10. 发明授权

US08193099B1 Protecting exposed metal gate structures from etching processes in integrated circuit manufacturing 有权
标题翻译：保护暴露的金属栅极结构免受集成电路制造中的蚀刻工艺
公开(公告)号：US08193099B1
公开(公告)日：2012-06-05
申请号：US13049933
申请日：2011-03-17
申请人： Mukesh V. Khare , Renee T. Mo , Ravikumar Ramachandran , Richard S. Wise , Hongwen Yan
发明人： Mukesh V. Khare , Renee T. Mo , Ravikumar Ramachandran , Richard S. Wise , Hongwen Yan
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/32136 , H01L21/823437 , H01L21/823481 , H01L21/823828 , H01L21/823878
摘要： A method of forming a semiconductor device includes forming a transistor gate stack over a substrate having an active area and a shallow trench isolation (STI) region. First sidewall spacers are formed on the transistor gate stack, and an isotropic etch process is applied to isotropically remove an excess portion of a metal layer included within the transistor gate stack, the excess portion left unprotected by the first sidewall spacers. Second sidewall spacers are formed on the transistor gate stack, the second sidewall spacers completely encapsulating the metal layer of the transistor gate stack.
摘要翻译：形成半导体器件的方法包括在具有有源区和浅沟槽隔离（STI）区的衬底上形成晶体管栅叠。第一侧壁间隔物形成在晶体管栅极堆叠上，并且各向同性蚀刻工艺被应用于各向同性地去除包括在晶体管栅极叠层内的金属层的过剩部分，剩余部分未被第一侧壁间隔物保护。第二侧壁间隔物形成在晶体管栅极叠层上，第二侧壁间隔物完全封装晶体管栅极叠层的金属层。

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