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1. 发明申请

US20070226423A1 Processor, data processing system, and method for initializing a memory block in a data processing system having multiple coherency domains 有权
标题翻译：处理器，数据处理系统和用于初始化具有多个相干域的数据处理系统中的存储器块的方法
公开(公告)号：US20070226423A1
公开(公告)日：2007-09-27
申请号：US11388001
申请日：2006-03-23
申请人： Ravi Arimilli , Guy Guthrie , William Starke , Derek Williams
发明人： Ravi Arimilli , Guy Guthrie , William Starke , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0822 , G06F12/084
摘要： A data processing system includes at least first and second coherency domains, each including at least one processor core and a memory. In response to an initialization operation by a processor core that indicates a target memory block to be initialized, a cache memory in the first coherency domain determines a coherency state of the target memory block with respect to the cache memory. In response to the determination, the cache memory selects a scope of broadcast of an initialization request identifying the target memory block. A narrower scope including the first coherency domain and excluding the second coherency domain is selected in response to a determination of a first coherency state, and a broader scope including the first coherency domain and the second coherency domain is selected in response to a determination of a second coherency state. The cache memory then broadcasts an initialization request with the selected scope. In response to the initialization request, the target memory block is initialized within a memory of the data processing system to an initialization value.
摘要翻译：数据处理系统至少包括第一和第二相干域，每个域包括至少一个处理器核和存储器。响应于指示要初始化的目标存储器块的处理器核心的初始化操作，第一相干域中的高速缓存存储器确定目标存储器块相对于高速缓冲存储器的一致性状态。响应于该确定，高速缓存存储器选择识别目标存储器块的初始化请求的广播范围。响应于第一相关性状态的确定而选择包括第一相关域并且排除第二相关性域的较窄范围，并且响应于确定第一相关性域的第一相关性域和第二相关域第二一致性状态。然后，高速缓冲存储器播放具有所选范围的初始化请求。响应于初始化请求，将目标存储器块在数据处理系统的存储器内初始化为初始化值。

2. 发明申请

US20070250669A1 DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING THAT REDUCE STORE QUEUE ENTRY UTILIZATION FOR SYNCHRONIZING OPERATIONS 失效
标题翻译：数据处理系统，处理器和数据处理方法减少存储队列进入同步操作的使用
公开(公告)号：US20070250669A1
公开(公告)日：2007-10-25
申请号：US11380020
申请日：2006-04-25
申请人： Ravi Arimilli , Thomas Capasso , Robert Cargnoni , Guy Guthrie , Hugh Shen , William Starke
发明人： Ravi Arimilli , Thomas Capasso , Robert Cargnoni , Guy Guthrie , Hugh Shen , William Starke
IPC分类号： G06F13/00
CPC分类号： G06F9/3842 , G06F9/3851 , G06F9/544
摘要： A data processing system includes a processor core and a memory subsystem. The memory subsystem includes a store queue having a plurality of entries, where each entry includes an address field for holding the target address of store operation, a data field for holding data for the store operation, and a virtual sync field indicating a presence or absence of a synchronizing operation associated with the entry. The memory subsystem further includes a store queue controller that, responsive to receipt at the memory subsystem of a sequence of operations including a synchronizing operation and a particular store operation, places a target address and data of the particular store operation within the address field and data field, respectively, of an entry in the store queue and sets the virtual sync field of the entry to represent the synchronizing operation, such that a number of store queue entries utilized is reduced.
摘要翻译：数据处理系统包括处理器核心和存储器子系统。存储器子系统包括具有多个条目的存储队列，其中每个条目包括用于保存存储操作的目标地址的地址字段，用于保存用于存储操作的数据的数据字段和指示存在或不存在的虚拟同步字段与该条目相关联的同步操作。存储器子系统还包括存储队列控制器，其响应于在存储器子系统处的接收包括同步操作和特定存储操作的一系列操作，将特定存储操作的目标地址和数据放置在地址字段和数据中字段，并且设置条目的虚拟同步字段以表示同步操作，使得减少使用的存储队列条目的数量。

3. 发明申请

US20070250668A1 DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING THAT SUPPORT MEMORY ACCESS ACCORDING TO DIVERSE MEMORY MODELS 失效
标题翻译：数据处理系统，处理器和数据处理方法，支持根据多个存储器模型的存储器访问
公开(公告)号：US20070250668A1
公开(公告)日：2007-10-25
申请号：US11380018
申请日：2006-04-25
申请人： Ravi Arimilli , Thomas Capasso , Guy Guthrie , Hugh Shen , William Starke
发明人： Ravi Arimilli , Thomas Capasso , Guy Guthrie , Hugh Shen , William Starke
IPC分类号： G06F13/00
CPC分类号： G06F13/1631 , G06F12/0811 , G06F12/0815 , G06F12/0846 , G06F12/0888
摘要： A data processing system includes a memory subsystem and an execution unit, coupled to the memory subsystem, which executes store instructions to determine target memory addresses of store operations to be performed by the memory subsystem. The data processing system further includes a mode field having a first setting indicating strong ordering between store operations and a second setting indicating weak ordering between store operations. Store operations accessing the memory subsystem are associated with either the first setting or the second setting. The data processing system also includes logic that, based upon settings of the mode field, inserts a synchronizing operation between a store operation associated with the first setting and a store operation associated with the second setting, such that all store operations preceding the synchronizing operation complete before store operations subsequent to the synchronizing operation.
摘要翻译：数据处理系统包括存储器子系统和执行单元，其耦合到存储器子系统，其执行存储指令以确定要由存储器子系统执行的存储操作的目标存储器地址。数据处理系统还包括具有指示存储操作之间的强顺序的第一设置的模式字段和指示存储操作之间的弱顺序的第二设置。访问内存子系统的存储操作与第一个设置或第二个设置相关联。数据处理系统还包括基于模式字段的设置的逻辑，在与第一设置相关联的存储操作与与第二设置相关联的存储操作之间插入同步操作，使得同步操作之前的所有存储操作完成在同步操作之后的存储操作之前。

4. 发明申请

US20070081516A1 Data processing system, method and interconnect fabric supporting multiple planes of processing nodes 有权
标题翻译：支持多个处理节点平面的数据处理系统，方法和互连结构
公开(公告)号：US20070081516A1
公开(公告)日：2007-04-12
申请号：US11245887
申请日：2005-10-07
申请人： Ravi Arimilli , Benjiman Goodman , Guy Guthrie , Praveen Reddy , William Starke
发明人： Ravi Arimilli , Benjiman Goodman , Guy Guthrie , Praveen Reddy , William Starke
IPC分类号： H04L12/28
CPC分类号： G06F15/16
摘要： A data processing system includes a first plane including a first plurality of processing nodes, each including multiple processing units, and a second plane including a second plurality of processing nodes, each including multiple processing units. The data processing system also includes a plurality of point-to-point first tier links. Each of the first plurality and second plurality of processing nodes includes one or more first tier links among the plurality of first tier links, where the first tier link(s) within each processing node connect a pair of processing units in the same processing node for communication. The data processing system further includes a plurality of point-to-point second tier links. At least a first of the plurality of second tier links connects processing units in different ones of the first plurality of processing nodes, at least a second of the plurality of second tier links connects processing units in different ones of the second plurality of processing nodes, and at least a third of the plurality of second tier links connects a processing unit in the first plane to a processing unit in the second plane.
摘要翻译：数据处理系统包括包括第一多个处理节点的第一平面，每个处理节点包括多个处理单元，以及包括第二多个处理节点的第二平面，每个处理节点包括多个处理单元。数据处理系统还包括多个点对点第一层链路。第一多个处理节点和第二多个处理节点中的每一个包括多个第一层链路之中的一个或多个第一层链路，其中每个处理节点内的第一层链路连接相同处理节点中的一对处理单元，用于通讯。数据处理系统还包括多个点到点第二层链路。所述多个第二层链路中的至少第一层连接所述第一多个处理节点中的不同处理节点中的处理单元，所述多个第二层链路中的至少一个链接连接所述第二多个处理节点中的不同处理节点中的处理单元，并且所述多个第二层链路中的至少三分之一链路将所述第一平面中的处理单元连接到所述第二平面中的处理单元。

5. 发明申请

US20060271741A1 Data processing system, cache system and method for scrubbing a domain indication in response to execution of program code 有权
标题翻译：数据处理系统，缓存系统和用于响应于程序代码的执行来擦除域指示的方法
公开(公告)号：US20060271741A1
公开(公告)日：2006-11-30
申请号：US11136642
申请日：2005-05-24
申请人： Leo Clark , James Fields , Guy Guthrie , William Starke , Derek Williams
发明人： Leo Clark , James Fields , Guy Guthrie , William Starke , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0813
摘要： In response to execution of program code, a control register within scrubbing logic in a local coherency domain is initialized with at least a target address of a target memory block. In response to the initialization, the scrubbing logic issues to at least one cache hierarchy in a remote coherency domain a domain indication scrubbing request targeting a target memory block that may be cached by the at least one cache hierarchy. In response to receipt of a coherency response indicating that the target memory block is not cached in the remote coherency domain, a domain indication in the local coherency domain is updated to indicate that the target memory block is cached, if at all, only within the local coherency domain.
摘要翻译：响应于程序代码的执行，用至少目标存储器块的目标地址初始化局部一致性域内的擦除逻辑中的控制寄存器。响应于初始化，擦除逻辑向远程一致性域中的至少一个高速缓存层级发出针对可由所述至少一个高速缓存层级缓存的目标存储器块的域指示擦除请求。响应于接收到指示目标存储器块未被缓存在远程一致性域中的一致性响应，本地一致性域中的域指示被更新以指示目标存储器块被缓存，如果完全只在局部一致性域。

6. 发明申请

US20060184749A1 Reducing number of rejected snoop requests by extending time to respond to snoop request 有权
公开(公告)号：US20060184749A1
公开(公告)日：2006-08-17
申请号：US11056764
申请日：2005-02-11
申请人： Guy Guthrie , Hugh Shen , William Starke , Derek Williams
发明人： Guy Guthrie , Hugh Shen , William Starke , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0831
摘要： A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if the stall/reorder unit is not full. The entered snoop request is dispatched to a selector upon entering a bottom latch in the pipeline. The stall/reorder unit is not informed as to whether the dispatched snoop request is accepted by an arbitration mechanism for several clock cycles after the dispatch occurred. A copy of the dispatched snoop request is stored in a top latch in an overrun pipeline of latches in the first unit upon dispatching the snoop request. By maintaining information about the snoop request, the snoop request may be dispatched again to the selector in case the dispatched snoop request was rejected thereby increasing the chance that the snoop request will ultimately be accepted.

7. 发明申请

US20060085603A1 Processor, data processing system and method for synchronzing access to data in shared memory 有权
标题翻译：处理器，数据处理系统和方法，用于同步共享存储器中数据的访问
公开(公告)号：US20060085603A1
公开(公告)日：2006-04-20
申请号：US10965113
申请日：2004-10-14
申请人： Guy Guthrie , Sheldon Levenstein , William Starke , Derek Williams
发明人： Guy Guthrie , Sheldon Levenstein , William Starke , Derek Williams
IPC分类号： G06F12/00
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3851 , G06F12/0811 , G06F12/0831 , G06F12/0855
摘要： A processing unit for a multiprocessor data processing system includes a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, at least one instruction execution unit that executes a store-conditional instruction to determine a store target address, a store queue that, following execution of the store-conditional instruction, buffers a corresponding store operation, sequencer logic associated with the store queue. The sequencer logic, responsive to receipt of a latency indication indicating that resolution of the store-conditional operation as passing or failing is subject to significant latency, invalidates, prior to resolution of the store-conditional operation, a cache line in the store-through upper level cache to which a load-reserve operation previously bound.
摘要翻译：一种用于多处理器数据处理系统的处理单元，包括存储器上级缓存器，取指令执行指令排序单元，执行存储条件指令以确定存储目标地址的至少一个指令执行单元，存储器在存储条件指令的执行之后，缓存与存储队列相关联的对应存储操作，定序器逻辑的队列。定序器逻辑响应于指示存储条件操作的解析作为传递或失败的等待时间指示受到重大等待时间的影响，在存储条件操作的解析之前无效，存储器中的高速缓存行加载预备操作先前绑定到的高级缓存。

8. 发明申请

US20080016284A1 DATA PROCESSING SYSTEM AND METHOD FOR PREDICTIVELY SELECTING A SCOPE OF BROADCAST OF AN OPERATION UTILIZING A HISTORY-BASED PREDICTION 审中-公开
标题翻译：数据处理系统和方法，用于预测性地选择使用基于历史的预测操作的广播范围
公开(公告)号：US20080016284A1
公开(公告)日：2008-01-17
申请号：US11863979
申请日：2007-09-28
申请人： BENJIMAN GOODMAN , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
发明人： BENJIMAN GOODMAN , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0833 , G06F2212/507
摘要： According to a method of data processing, a predictor is maintained that indicates a historical scope of broadcast for one or more previous operations transmitted on an interconnect of a data processing system. A scope of broadcast of a subsequent operation is predictively selected by reference to the predictor.
摘要翻译：根据数据处理的方法，保持预测器，其指示在数据处理系统的互连上发送的一个或多个先前操作的广播的历史范围。通过参考预测器预测性地选择后续操作的广播范围。

9. 发明申请

US20060271743A1 Data processing system, cache system and method for passively scrubbing a domain indication 失效
公开(公告)号：US20060271743A1
公开(公告)日：2006-11-30
申请号：US11136652
申请日：2005-05-24
申请人： Leo Clark , James Fields , Guy Guthrie , William Starke , Derek Williams
发明人： Leo Clark , James Fields , Guy Guthrie , William Starke , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0831
摘要： Scrubbing logic in a local coherency domain issues a domain query request to at least one cache hierarchy in a remote coherency domain. The domain query request is a non-destructive probe of a coherency state associated with a target memory block by the at least one cache hierarchy. A coherency response to the domain query request is received. In response to the coherency response indicating that the target memory block is not cached in the remote coherency domain, a domain indication in the local coherency domain is updated to indicate that the target memory block is cached, if at all, only within the local coherency domain.

10. 发明申请

US20060184746A1 Reducing number of rejected snoop requests by extending time to respond to snoop request 失效
标题翻译：通过延长响应窥探请求的时间来减少被拒绝的窥探请求数
公开(公告)号：US20060184746A1
公开(公告)日：2006-08-17
申请号：US11056679
申请日：2005-02-11
申请人： Guy Guthrie , Hugh Shen , William Starke , Derek Williams
发明人： Guy Guthrie , Hugh Shen , William Starke , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F13/1605 , G06F12/0831
摘要： A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. The snoop request is entered in the first available latch of the stall/reorder unit unless the stall/reorder unit is full in which case the new snoop request is transmitted to a second unit configured to transmit a request to retry resending the new snoop request. Snoop requests have a higher priority than requests from processors and snoop requests are selected by the arbitration mechanism over processor requests unless the arbitration mechanism requests otherwise (“stall request”) to the stall/reorder unit. By snoop requests having a higher priority than processor requests, the number of snoop requests rejected is reduced. By having the arbitration mechanism issue a stall request, the processor will not be starved.
摘要翻译：用于减少拒绝的窥探请求数量的缓存，系统和方法。缓存中的“停止/重新排序单元”从互连中接收窥探请求。监听请求被输入到停止/重新排序单元的第一可用锁存器中，除非停止/重新排序单元已满，在这种情况下，新的窥探请求被发送到被配置为发送重新发送新的窥探请求的请求的第二单元。侦听请求具有比来自处理器的请求更高的优先级，并且仲裁机制通过处理器请求选择侦听请求，除非仲裁机制另请求（“停止请求”）到停止/重新排序单元。通过具有比处理器请求更高优先级的侦听请求，减少了被拒绝的侦听请求的数量。通过使仲裁机制发出停顿请求，处理器不会饿死。

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