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1. 发明授权

US09082714B2 Use of etch process post wordline definition to improve data retention in a flash memory device 有权
标题翻译：使用蚀刻处理后字幕定义来改善闪存设备中的数据保留
公开(公告)号：US09082714B2
公开(公告)日：2015-07-14
申请号：US13993444
申请日：2011-09-22
申请人： Randy J. Koval , Max F. Hineman , Ronald A. Weimer , Vinayak K. Shamanna , Thomas M. Graettinger , William R. Kueber , Christopher Larsen , Alex J. Schrinsky
发明人： Randy J. Koval , Max F. Hineman , Ronald A. Weimer , Vinayak K. Shamanna , Thomas M. Graettinger , William R. Kueber , Christopher Larsen , Alex J. Schrinsky
IPC分类号： H01L21/76 , H01L21/306 , H01L29/51 , H01L29/788 , H01L29/792 , H01L27/115
CPC分类号： H01L21/30604 , H01L21/76 , H01L27/11521 , H01L27/11568 , H01L29/513 , H01L29/788 , H01L29/7881 , H01L29/792
摘要： Embodiments of the present disclosure are directed towards use of an etch process post wordline definition to improve data retention in a flash memory device. In one embodiment, a method includes forming a plurality of wordline structures on a substrate, wherein individual wordline structures of the plurality of wordline structures include a control gate having an electrically conductive material and a cap having an electrically insulative material formed on the control gate, depositing an electrically insulative material to form a liner on a surface of the individual wordline structures, and etching the liner to remove at least a portion of the liner. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例涉及使用蚀刻处理后字幕定义来改善闪存器件中的数据保持。在一个实施例中，一种方法包括在衬底上形成多个字线结构，其中多个字线结构中的各个字线结构包括具有导电材料的控制栅极和在控制栅极上形成有电绝缘材料的盖，沉积电绝缘材料以在单个字线结构的表面上形成衬垫，以及蚀刻衬垫以去除衬垫的至少一部分。可以描述和/或要求保护其他实施例。

2. 发明申请

US20130264628A1 USE OF ETCH PROCESS POST WORDLINE DEFINITION TO IMPROVE DATA RETENTION IN A FLASH MEMORY DEVICE 有权
标题翻译： ETCH过程的使用在字幕定义中改进闪存存储器件中的数据保持
公开(公告)号：US20130264628A1
公开(公告)日：2013-10-10
申请号：US13993444
申请日：2011-09-22
申请人： Randy J. Koval , Max F. Hineman , Ronald A. Weimer , Vinayak K. Shamanna , Thomas M. Graettinger , William R. Kueber , Christopher Larsen , Alex J. Schrinsky
发明人： Randy J. Koval , Max F. Hineman , Ronald A. Weimer , Vinayak K. Shamanna , Thomas M. Graettinger , William R. Kueber , Christopher Larsen , Alex J. Schrinsky
IPC分类号： H01L21/306 , H01L29/788
CPC分类号： H01L21/30604 , H01L21/76 , H01L27/11521 , H01L27/11568 , H01L29/513 , H01L29/788 , H01L29/7881 , H01L29/792
摘要： Embodiments of the present disclosure describe techniques and configurations relating to use of an etch process post wordline definition to improve data retention in a flash memory device. In one embodiment, a method includes forming a plurality of wordline structures on a substrate, wherein individual wordline structures of the plurality of wordline structures include a control gate having an electrically conductive material and a cap having an electrically insulative material formed on the control gate, depositing an electrically insulative material to form a liner on a surface of the individual wordline structures, and etching the liner to remove at least a portion of the liner. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述与使用蚀刻处理后字幕定义相关的技术和配置以改善闪存设备中的数据保持。在一个实施例中，一种方法包括在衬底上形成多个字线结构，其中多个字线结构中的各个字线结构包括具有导电材料的控制栅极和在控制栅极上形成有电绝缘材料的盖，沉积电绝缘材料以在单个字线结构的表面上形成衬垫，以及蚀刻衬垫以去除衬垫的至少一部分。可以描述和/或要求保护其他实施例。

3. 发明授权

US07476588B2 Methods of forming NAND cell units with string gates of various widths 失效
标题翻译：用各种宽度的串门形成NAND单元单元的方法
公开(公告)号：US07476588B2
公开(公告)日：2009-01-13
申请号：US11652903
申请日：2007-01-12
申请人： David J. Keller , Hongbin Zhu , Alex J. Schrinsky
发明人： David J. Keller , Hongbin Zhu , Alex J. Schrinsky
IPC分类号： H01L21/336 , H01L21/311 , H01L21/302
CPC分类号： H01L27/115 , H01L21/31122 , H01L21/31144 , H01L21/32139 , H01L27/11521 , H01L27/11524
摘要： Some embodiments include methods of forming a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate. Some embodiments include utilization of an etch comprising HBr and O2 to extend a pattern through a carbon-containing layer. The patterned carbon-containing layer may be used to pattern NAND cell unit gates. Some embodiments include structures having a patterned carbon-containing layer defining a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate.
摘要翻译：一些实施例包括形成具有与离选择栅极更远的其它NAND串门不同的宽度的与选择栅极最接近的NAND串栅极的NAND单元单元的方法。一些实施方案包括利用包含HBr和O 2的蚀刻以将图案扩展通过含碳层。图案化的含碳层可用于对NAND单元单元栅极进行图案化。一些实施方案包括具有图案化含碳层的结构，其限定具有与离选择栅极更远的其它NAND串栅极不同宽度的最接近选择栅极的NAND串栅极的NAND单元单元。

4. 发明申请

US20110159685A1 Methods Of Forming Electrically Insulative Materials, Methods Of Forming Low k Dielectric Regions, And Methods Of Forming Semiconductor Constructions 有权
标题翻译：形成电绝缘材料的方法，形成低k介电区域的方法和形成半导体结构的方法
公开(公告)号：US20110159685A1
公开(公告)日：2011-06-30
申请号：US13043902
申请日：2011-03-09
申请人： Alex J. Schrinsky
发明人： Alex J. Schrinsky
IPC分类号： H01L21/3205
CPC分类号： H01L21/32115 , H01L21/3212 , H01L21/7682 , H01L21/76837 , H01L21/76885
摘要： Some embodiments include methods of forming low k dielectric regions between electrically conductive lines. A construction may be formed to have a plurality of spaced apart electrically conductive lines, and to have sacrificial material between the electrically conductive lines. The sacrificial material may be removed. Subsequently, electrically insulative material may be deposited over and between the lines. The deposition of the insulative material may occur under conditions in which bread-loafing of the insulative material creates bridges of the insulative material across gas-filled gaps between the lines. The gas-filled gaps may be considered to correspond to low k dielectric regions between the electrically conductive lines. In some embodiments the sacrificial material may be carbon. In some embodiments, the deposited insulative material may be a low k dielectric material, and in other embodiments the deposited insulative material may not be a low k dielectric material.
摘要翻译：一些实施例包括在导电线之间形成低k电介质区域的方法。可以形成具有多个间隔开的导电线并且在导电线之间具有牺牲材料的结构。牺牲材料可以被去除。随后，电绝缘材料可以沉积在线之间和之间。绝缘材料的沉积可能发生在绝缘材料的面包布条在绝缘材料之间穿过填充间隙之间的绝缘材料的桥梁的情况下发生。气体填充的间隙可以被认为对应于导电线之间的低k电介质区域。在一些实施例中，牺牲材料可以是碳。在一些实施例中，沉积的绝缘材料可以是低k电介质材料，并且在其它实施例中，所沉积的绝缘材料可以不是低k电介质材料。

5. 发明申请

US20100291771A1 Methods Of Forming Patterns On Substrates 有权
标题翻译：在基板上形成图案的方法
公开(公告)号：US20100291771A1
公开(公告)日：2010-11-18
申请号：US12467687
申请日：2009-05-18
申请人： Baosuo Zhou , Alex J. Schrinsky
发明人： Baosuo Zhou , Alex J. Schrinsky
IPC分类号： H01L21/3065
CPC分类号： H01L21/31138 , H01L21/0337 , H01L21/0338 , H01L21/31116 , H01L21/31122 , H01L21/31144 , H01L21/32139 , H01L27/11526 , H01L27/11534
摘要： Methods of forming a pattern on a substrate include forming carbon-comprising material over a base material, and spaced first features over the carbon-comprising material. Etching is conducted only partially into the carbon-comprising material and spaced second features are formed within the carbon-comprising material which comprise the partially etched carbon-comprising material. Spacers can be formed along sidewalls of the spaced second features. The carbon-comprising material can be etched through to the base material using the spacers as a mask. Spaced third features can be formed which comprise the anisotropically etched spacers and the carbon-comprising material.
摘要翻译：在基材上形成图案的方法包括在基材上形成含碳材料，并且在包含碳的材料上间隔第一特征。蚀刻仅部分地进入含碳材料，并且在包含部分蚀刻的含碳材料的含碳材料内形成间隔开的第二特征。间隔物可以沿着间隔开的第二特征的侧壁形成。可以使用间隔件作为掩模，将含碳材料蚀刻到基材上。可以形成包括各向异性蚀刻间隔物和含碳材料的间隔的第三特征。

6. 发明授权

US07927964B2 Methods of forming electrically insulative materials, methods of forming low k dielectric regions, and methods of forming semiconductor constructions 有权
标题翻译：形成电绝缘材料的方法，形成低k电介质区域的方法，以及形成半导体结构的方法
公开(公告)号：US07927964B2
公开(公告)日：2011-04-19
申请号：US12270530
申请日：2008-11-13
申请人： Alex J. Schrinsky
发明人： Alex J. Schrinsky
IPC分类号： H01L21/76
CPC分类号： H01L21/32115 , H01L21/3212 , H01L21/7682 , H01L21/76837 , H01L21/76885
摘要： Some embodiments include methods of forming low k dielectric regions between electrically conductive lines. A construction may be formed to have a plurality of spaced apart electrically conductive lines, and to have sacrificial material between the electrically conductive lines. The sacrificial material may be removed. Subsequently, electrically insulative material may be deposited over and between the lines. The deposition of the insulative material may occur under conditions in which bread-loafing of the insulative material creates bridges of the insulative material across gas-filled gaps between the lines. The gas-filled gaps may be considered to correspond to low k dielectric regions between the electrically conductive lines. In some embodiments the sacrificial material may be carbon. In some embodiments, the deposited insulative material may be a low k dielectric material, and in other embodiments the deposited insulative material may not be a low k dielectric material.
摘要翻译：一些实施例包括在导电线之间形成低k电介质区域的方法。可以形成具有多个间隔开的导电线并且在导电线之间具有牺牲材料的结构。牺牲材料可以被去除。随后，电绝缘材料可以沉积在线之间和之间。绝缘材料的沉积可能发生在绝缘材料的面包布条在绝缘材料之间穿过填充间隙之间的绝缘材料的桥梁的情况下发生。气体填充的间隙可以被认为对应于导电线之间的低k电介质区域。在一些实施例中，牺牲材料可以是碳。在一些实施例中，沉积的绝缘材料可以是低k电介质材料，并且在其它实施例中，所沉积的绝缘材料可以不是低k电介质材料。

7. 发明申请

US20080169496A1 Methods of forming NAND cell units 失效
标题翻译：形成NAND单元的方法
公开(公告)号：US20080169496A1
公开(公告)日：2008-07-17
申请号：US11652903
申请日：2007-01-12
申请人： David J. Keller , Hongbin Zhu , Alex J. Schrinsky
发明人： David J. Keller , Hongbin Zhu , Alex J. Schrinsky
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/115 , H01L21/31122 , H01L21/31144 , H01L21/32139 , H01L27/11521 , H01L27/11524
摘要： Some embodiments include methods of forming a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate. Some embodiments include utilization of an etch comprising HBr and O2 to extend a pattern through a carbon-containing layer. The patterned carbon-containing layer may be used to pattern NAND cell unit gates. Some embodiments include structures having a patterned carbon-containing layer defining a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate.
摘要翻译：一些实施例包括形成具有与离选择栅极更远的其它NAND串门不同的宽度的与选择栅极最接近的NAND串栅极的NAND单元单元的方法。一些实施方案包括利用包含HBr和O 2 2的蚀刻来将图案延伸穿过含碳层。图案化的含碳层可用于对NAND单元单元栅极进行图案化。一些实施方案包括具有图案化含碳层的结构，其限定具有与离选择栅极更远的其它NAND串栅极不同宽度的最接近选择栅极的NAND串栅极的NAND单元单元。

8. 发明授权

US08309424B2 Methods of forming electrically insulative materials, methods of forming low k dielectric regions, and methods of forming semiconductor constructions 有权
标题翻译：形成电绝缘材料的方法，形成低k电介质区域的方法，以及形成半导体结构的方法
公开(公告)号：US08309424B2
公开(公告)日：2012-11-13
申请号：US13043902
申请日：2011-03-09
申请人： Alex J. Schrinsky
发明人： Alex J. Schrinsky
IPC分类号： H01L21/76
CPC分类号： H01L21/32115 , H01L21/3212 , H01L21/7682 , H01L21/76837 , H01L21/76885
摘要： Some embodiments include methods of forming low k dielectric regions between electrically conductive lines. A construction may be formed to have a plurality of spaced apart electrically conductive lines, and to have sacrificial material between the electrically conductive lines. The sacrificial material may be removed. Subsequently, electrically insulative material may be deposited over and between the lines. The deposition of the insulative material may occur under conditions in which bread-loafing of the insulative material creates bridges of the insulative material across gas-filled gaps between the lines. The gas-filled gaps may be considered to correspond to low k dielectric regions between the electrically conductive lines. In some embodiments the sacrificial material may be carbon. In some embodiments, the deposited insulative material may be a low k dielectric material, and in other embodiments the deposited insulative material may not be a low k dielectric material.
摘要翻译：一些实施例包括在导电线之间形成低k电介质区域的方法。可以形成具有多个间隔开的导电线并且在导电线之间具有牺牲材料的结构。牺牲材料可以被去除。随后，电绝缘材料可以沉积在线之间和之间。绝缘材料的沉积可能发生在绝缘材料的面包布条在绝缘材料之间穿过填充间隙之间的绝缘材料的桥梁的情况下发生。气体填充的间隙可以被认为对应于导电线之间的低k电介质区域。在一些实施例中，牺牲材料可以是碳。在一些实施例中，沉积的绝缘材料可以是低k电介质材料，并且在其它实施例中，所沉积的绝缘材料可以不是低k电介质材料。

9. 发明授权

US07898019B2 Semiconductor constructions having multiple patterned masking layers over NAND gate stacks 有权
标题翻译：在NAND门叠层上具有多个图案化掩模层的半导体结构
公开(公告)号：US07898019B2
公开(公告)日：2011-03-01
申请号：US12331059
申请日：2008-12-09
申请人： David J. Keller , Hongbin Zhu , Alex J. Schrinsky
发明人： David J. Keller , Hongbin Zhu , Alex J. Schrinsky
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L21/31122 , H01L21/31144 , H01L21/32139 , H01L27/11521 , H01L27/11524
摘要： Some embodiments include methods of forming a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate. Some embodiments include utilization of an etch comprising HBr and O2 to extend a pattern through a carbon-containing layer. The patterned carbon-containing layer may be used to pattern NAND cell unit gates. Some embodiments include structures having a patterned carbon-containing layer defining a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate.
摘要翻译：一些实施例包括形成具有与离选择栅极更远的其它NAND串门不同的宽度的与选择栅极最接近的NAND串栅极的NAND单元单元的方法。一些实施方案包括利用包含HBr和O 2的蚀刻以将图案扩展通过含碳层。图案化的含碳层可用于对NAND单元单元栅极进行图案化。一些实施方案包括具有图案化含碳层的结构，其限定具有与离选择栅极更远的其它NAND串栅极不同宽度的最接近选择栅极的NAND串栅极的NAND单元单元。

10. 发明申请

US20090090958A1 Semiconductor Constructions 有权
标题翻译：半导体建筑
公开(公告)号：US20090090958A1
公开(公告)日：2009-04-09
申请号：US12331059
申请日：2008-12-09
申请人： David J. Keller , Hongbin Zhu , Alex J. Schrinsky
发明人： David J. Keller , Hongbin Zhu , Alex J. Schrinsky
IPC分类号： H01L27/115
CPC分类号： H01L27/115 , H01L21/31122 , H01L21/31144 , H01L21/32139 , H01L27/11521 , H01L27/11524
摘要： Some embodiments include methods of forming a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate. Some embodiments include utilization of an etch comprising HBr and O2 to extend a pattern through a carbon-containing layer. The patterned carbon-containing layer may be used to pattern NAND cell unit gates. Some embodiments include structures having a patterned carbon-containing layer defining a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate.
摘要翻译：一些实施例包括形成具有与离选择栅极更远的其它NAND串门不同的宽度的与选择栅极最接近的NAND串栅极的NAND单元单元的方法。一些实施方案包括利用包含HBr和O 2的蚀刻以将图案扩展通过含碳层。图案化的含碳层可用于对NAND单元单元栅极进行图案化。一些实施方案包括具有图案化的含碳层的结构，其限定具有与离选择栅极更远的其它NAND串栅极不同宽度的最接近选择栅极的NAND串栅极的NAND单元单元。

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