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1. 发明申请

US20100291771A1 Methods Of Forming Patterns On Substrates 有权
标题翻译：在基板上形成图案的方法
公开(公告)号：US20100291771A1
公开(公告)日：2010-11-18
申请号：US12467687
申请日：2009-05-18
申请人： Baosuo Zhou , Alex J. Schrinsky
发明人： Baosuo Zhou , Alex J. Schrinsky
IPC分类号： H01L21/3065
CPC分类号： H01L21/31138 , H01L21/0337 , H01L21/0338 , H01L21/31116 , H01L21/31122 , H01L21/31144 , H01L21/32139 , H01L27/11526 , H01L27/11534
摘要： Methods of forming a pattern on a substrate include forming carbon-comprising material over a base material, and spaced first features over the carbon-comprising material. Etching is conducted only partially into the carbon-comprising material and spaced second features are formed within the carbon-comprising material which comprise the partially etched carbon-comprising material. Spacers can be formed along sidewalls of the spaced second features. The carbon-comprising material can be etched through to the base material using the spacers as a mask. Spaced third features can be formed which comprise the anisotropically etched spacers and the carbon-comprising material.
摘要翻译：在基材上形成图案的方法包括在基材上形成含碳材料，并且在包含碳的材料上间隔第一特征。蚀刻仅部分地进入含碳材料，并且在包含部分蚀刻的含碳材料的含碳材料内形成间隔开的第二特征。间隔物可以沿着间隔开的第二特征的侧壁形成。可以使用间隔件作为掩模，将含碳材料蚀刻到基材上。可以形成包括各向异性蚀刻间隔物和含碳材料的间隔的第三特征。

2. 发明授权

US09330934B2 Methods of forming patterns on substrates 有权
标题翻译：在基材上形成图案的方法
公开(公告)号：US09330934B2
公开(公告)日：2016-05-03
申请号：US12467687
申请日：2009-05-18
申请人： Baosuo Zhou , Alex J. Schrinsky
发明人： Baosuo Zhou , Alex J. Schrinsky
IPC分类号： H01L21/033 , H01L21/311 , H01L21/3213 , H01L27/115
CPC分类号： H01L21/31138 , H01L21/0337 , H01L21/0338 , H01L21/31116 , H01L21/31122 , H01L21/31144 , H01L21/32139 , H01L27/11526 , H01L27/11534
摘要： Methods of forming a pattern on a substrate include forming carbon-comprising material over a base material, and spaced first features over the carbon-comprising material. Etching is conducted only partially into the carbon-comprising material and spaced second features are formed within the carbon-comprising material which comprise the partially etched carbon-comprising material. Spacers can be formed along sidewalls of the spaced second features. The carbon-comprising material can be etched through to the base material using the spacers as a mask. Spaced third features can be formed which comprise the anisotropically etched spacers and the carbon-comprising material.
摘要翻译：在基材上形成图案的方法包括在基材上形成含碳材料，并且在包含碳的材料上间隔第一特征。蚀刻仅部分地进入含碳材料，并且在包含部分蚀刻的含碳材料的含碳材料内形成间隔开的第二特征。间隔物可以沿着间隔开的第二特征的侧壁形成。可以使用间隔件作为掩模，将含碳材料蚀刻到基材上。可以形成包括各向异性蚀刻间隔物和含碳材料的间隔的第三特征。

3. 发明授权

US08389407B2 Methods of patterning materials 有权
标题翻译：图案材料的方法
公开(公告)号：US08389407B2
公开(公告)日：2013-03-05
申请号：US13491466
申请日：2012-06-07
申请人： Vishal Sipani , Baosuo Zhou , Ming-Chuan Yang
发明人： Vishal Sipani , Baosuo Zhou , Ming-Chuan Yang
IPC分类号： H01L21/44
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/76816 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments include methods of forming openings. For instance, a construction may have a material over a plurality of electrically conductive lines. A plurality of annular features may be formed over the material, with the annular features crossing the lines. A patterned mask may be formed over the annular features, with the patterned mask leaving segments of the annular features exposed through a window in the patterned mask. The exposed segments of the annular features may define a plurality of openings, and such openings may be transferred into the material to form openings extending to the electrically conductive lines.
摘要翻译：一些实施例包括形成开口的方法。例如，结构可以具有多条导电线上的材料。可以在材料上方形成多个环形特征，其中环形特征与线交叉。图案化掩模可以形成在环形特征上，其中图案化掩模留下通过图案化掩模中的窗口暴露的环形特征的段。环形特征的暴露部分可以限定多个开口，并且这样的开口可以被转移到材料中以形成延伸到导电线的开口。

4. 发明申请

US20130009283A1 METHODS TO REDUCE THE CRITICAL DIMENSION OF SEMICONDUCTOR DEVICES AND RELATED SEMICONDUCTOR DEVICES 有权
标题翻译：降低半导体器件及相关半导体器件关键尺寸的方法
公开(公告)号：US20130009283A1
公开(公告)日：2013-01-10
申请号：US13619905
申请日：2012-09-14
申请人： Baosuo Zhou
发明人： Baosuo Zhou
IPC分类号： H01L29/06 , H01L21/311
CPC分类号： H01L21/0338 , H01L21/3088
摘要： A method of forming features on a target layer. The features have a critical dimension that is triple- or quadruple-reduced compared to the critical dimension of portions of a resist layer used as a mask. An intermediate layer is deposited over a target layer and the resist layer is formed over the intermediate layer. After patterning the resist layer, first spacers are formed on sidewalls of remaining portions of the resist layer, masking portions of the intermediate layer. Second spacers are formed on sidewalls of the portions of the intermediate layer. After removing the portions of the intermediate layer, the second spacers are used as a mask to form the features on the target layer. Integrated circuit devices are also disclosed.
摘要翻译：在目标层上形成特征的方法。与用作掩模的抗蚀剂层的部分的临界尺寸相比，这些特征具有三倍或四倍的临界尺寸。在目标层上沉积中间层，并且在中间层上形成抗蚀剂层。在图案化抗蚀剂层之后，第一间隔物形成在抗蚀剂层的剩余部分的侧壁上，中间层的掩蔽部分。第二间隔件形成在中间层的部分的侧壁上。在去除中间层的部分之后，将第二间隔物用作掩模以在目标层上形成特征。还公开了集成电路器件。

5. 发明申请

US20120045896A1 Methods Of Forming Openings And Methods Of Patterning A Material 有权
标题翻译：形成开口的方法和图案化材料的方法
公开(公告)号：US20120045896A1
公开(公告)日：2012-02-23
申请号：US12860765
申请日：2010-08-20
申请人： Vishal Sipani , Baosuo Zhou , Ming-Chuan Yang
发明人： Vishal Sipani , Baosuo Zhou , Ming-Chuan Yang
IPC分类号： H01L21/768 , H01L21/302
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/76816 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments include methods of forming openings. For instance, a construction may have a material over a plurality of electrically conductive lines. A plurality of annular features may be formed over the material, with the annular features crossing the lines. A patterned mask may be formed over the annular features, with the patterned mask leaving segments of the annular features exposed through a window in the patterned mask. The exposed segments of the annular features may define a plurality of openings, and such openings may be transferred into the material to form openings extending to the electrically conductive lines.
摘要翻译：一些实施例包括形成开口的方法。例如，结构可以具有多条导电线上的材料。可以在材料上方形成多个环形特征，其中环形特征与线交叉。图案化掩模可以形成在环形特征上，其中图案化掩模留下通过图案化掩模中的窗口暴露的环形特征的段。环形特征的暴露部分可以限定多个开口，并且这样的开口可以被转移到材料中以形成延伸到导电线的开口。

6. 发明授权

US07910483B2 Trim process for critical dimension control for integrated circuits 失效
标题翻译：用于集成电路的关键尺寸控制的修整过程
公开(公告)号：US07910483B2
公开(公告)日：2011-03-22
申请号：US12698407
申请日：2010-02-02
申请人： Mirzafer K Abatchev , Krupaker Murali Subramanian , Baosuo Zhou
发明人： Mirzafer K Abatchev , Krupaker Murali Subramanian , Baosuo Zhou
IPC分类号： H01L21/302
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/32139
摘要： Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over the first hard mask layer; providing a photoresist layer over the second hard mask layer; forming a pattern in the photoresist layer; transferring the pattern into the second hard mask layer; and trimming the second hard mask layer with the photoresist layer on top of the second hard mask layer. The top surface of the second hard mask layer is protected by the photoresist and the substrate is protected by the overlying first hard mask layer during the trim etch, which can therefore be aggressive.
摘要翻译：公开了采用用于集成电路的关键尺寸控制的修整工艺的衬底的蚀刻方法。在一个实施例中，蚀刻方法包括在目标层上提供第一硬掩模层; 在第一硬掩模层上提供第二硬掩模层; 在所述第二硬掩模层上提供光致抗蚀剂层; 在光致抗蚀剂层中形成图案; 将图案转移到第二硬掩模层中; 以及在所述第二硬掩模层的顶部上用所述光致抗蚀剂层修剪所述第二硬掩模层。第二硬掩模层的顶表面由光致抗蚀剂保护，并且衬底在修整蚀刻期间被上覆的第一硬掩模层保护，因此可以是侵蚀性的。

7. 发明授权

US07902074B2 Simplified pitch doubling process flow 有权
标题翻译：简化俯仰加倍流程
公开(公告)号：US07902074B2
公开(公告)日：2011-03-08
申请号：US11400603
申请日：2006-04-07
申请人： Ardavan Niroomand , Baosuo Zhou , Ramakanth Alapati
发明人： Ardavan Niroomand , Baosuo Zhou , Ramakanth Alapati
IPC分类号： H01L21/311
CPC分类号： H01L27/04 , H01L21/0338 , H01L21/3088 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels in a device array region. The method further comprises depositing an oxide material over the plurality of mandrels and over a device peripheral region. The method further comprises forming a pattern of photoresist material over the oxide material in the device peripheral region. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces in the device array region. The method further comprises selectively etching photoresist material from the device array region and from the device peripheral region.
摘要翻译：一种用于制造半导体器件的方法包括将光致抗蚀剂材料层图案化以在器件阵列区域中形成多个心轴。该方法还包括在多个心轴上并在器件外围区域上沉积氧化物材料。该方法还包括在器件外围区域中的氧化物材料上形成光致抗蚀剂材料的图案。该方法还包括从器件阵列区域中暴露的水平表面各向异性地蚀刻氧化物材料。该方法还包括从器件阵列区域和器件外围区域选择性地蚀刻光致抗蚀剂材料。

8. 发明申请

US20070212889A1 Trim process for critical dimension control for integrated circuits 失效
标题翻译：用于集成电路的关键尺寸控制的修整过程
公开(公告)号：US20070212889A1
公开(公告)日：2007-09-13
申请号：US11372825
申请日：2006-03-09
申请人： Mirzafer Abatchev , Krupakar Subramanian , Baosuo Zhou
发明人： Mirzafer Abatchev , Krupakar Subramanian , Baosuo Zhou
IPC分类号： H01L21/467
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/32139
摘要： Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over the first hard mask layer; providing a photoresist layer over the second hard mask layer; forming a pattern in the photoresist layer; transferring the pattern into the second hard mask layer; and trimming the second hard mask layer with the photoresist layer on top of the second hard mask layer. The top surface of the second hard mask layer is protected by the photoresist and the substrate is protected by the overlying first hard mask layer during the trim etch, which can therefore be aggressive.
摘要翻译：公开了采用用于集成电路的关键尺寸控制的修整工艺的衬底的蚀刻方法。在一个实施例中，蚀刻方法包括在目标层上提供第一硬掩模层; 在第一硬掩模层上提供第二硬掩模层; 在所述第二硬掩模层上提供光致抗蚀剂层; 在光致抗蚀剂层中形成图案; 将图案转移到第二硬掩模层中; 以及在所述第二硬掩模层的顶部上用所述光致抗蚀剂层修剪所述第二硬掩模层。第二硬掩模层的顶表面由光致抗蚀剂保护，并且衬底在修整蚀刻期间被上覆的第一硬掩模层保护，因此可以是侵蚀性的。

9. 发明授权

US08852851B2 Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same 有权
标题翻译：在形成半导体器件期间使用交替间隔物沉积的减径技术及包括其的系统
公开(公告)号：US08852851B2
公开(公告)日：2014-10-07
申请号：US11484271
申请日：2006-07-10
申请人： Baosuo Zhou , Mirzafer K. Abatchev , Ardavan Niroomand , Paul A. Morgan , Shuang Meng , Joseph N. Greeley , Brian J. Coppa
发明人： Baosuo Zhou , Mirzafer K. Abatchev , Ardavan Niroomand , Paul A. Morgan , Shuang Meng , Joseph N. Greeley , Brian J. Coppa
IPC分类号： H01L21/033 , H01L21/308
CPC分类号： H01L21/30625 , H01L21/0335 , H01L21/0337 , H01L21/0338 , H01L21/30604 , H01L21/3086 , H01L21/3088 , H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
摘要翻译：图案化层的方法使用一系列自对准间隔物增加在初始图案化层上形成的特征的密度。提供待蚀刻的层，然后在待蚀刻的层上形成例如使用光学光刻形成的初始牺牲图案形成层。根据实施例，图案化层可以被修整，然后形成并蚀刻一系列间隔层。间隔层的数量及其目标尺寸取决于所需的特征密度增加。还描述了一种过程中半导体器件和电子系统。

10. 发明授权

US08492278B2 Method of forming a plurality of spaced features 有权
公开(公告)号：US08492278B2
公开(公告)日：2013-07-23
申请号：US12749923
申请日：2010-03-30
申请人： Farrell Good , Baosuo Zhou , Xiaolong Fang , Fatma Arzum Simsek-Ege
发明人： Farrell Good , Baosuo Zhou , Xiaolong Fang , Fatma Arzum Simsek-Ege
IPC分类号： H01L21/311
CPC分类号： H01L21/768 , H01L21/0332 , H01L21/28273 , H01L21/28282 , H01L21/302 , H01L21/32139 , H01L27/11521 , H01L27/11568
摘要： A method of forming a plurality of spaced features includes forming sacrificial hardmask material over underlying material. The sacrificial hardmask material has at least two layers of different composition. Portions of the sacrificial hardmask material are removed to form a mask over the underlying material. Individual features of the mask have at least two layers of different composition, with one of the layers of each of the individual features having a tensile intrinsic stress of at least 400.0 MPa. The individual features have a total tensile intrinsic stress greater than 0.0 MPa. The mask is used while etching into the underlying material to form a plurality of spaced features comprising the underlying material. Other implementations are disclosed.

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