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1. 发明授权

US6060380A Antireflective siliconoxynitride hardmask layer used during etching processes in integrated circuit fabrication 有权
标题翻译：在集成电路制造中的蚀刻工艺期间使用的抗反射硅氧氮化物硬掩模层
公开(公告)号：US6060380A
公开(公告)日：2000-05-09
申请号：US187391
申请日：1998-11-06
申请人： Ramkumar Subramanian , Bhanwar Singh , Simon Chan , Fei Wang
发明人： Ramkumar Subramanian , Bhanwar Singh , Simon Chan , Fei Wang
IPC分类号： H01L21/311 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76811 , H01L21/31144 , H01L21/76813
摘要： A method for etching openings in an integrated circuit uses siliconoxynitride as a hardmask layer. Because of the relatively low reflectivity of siliconoxynitride, when a photoresist layer is deposited on the siliconoxynitride hardmask layer and is exposed to light, the photoresist layer is patterned more conformingly to a desired pattern. The present invention may be used to particular advantage for etching contiguous trench lines and via holes in a dual damascene etch process for small dimension integrated circuits.
摘要翻译：用于蚀刻集成电路中的开口的方法使用硅氧氮化物作为硬掩模层。由于硅氧氮化物的相对低的反射率，当光致抗蚀剂层沉积在硅氧氮化物硬掩模层上并暴露于光时，光致抗蚀剂层被图案更符合期望的图案。本发明可以用于在用于小尺寸集成电路的双镶嵌蚀刻工艺中蚀刻连续沟槽线和通孔的特别优点。

2. 发明授权

US08381613B2 Parking brake cable and adjust system having no lost cable travel 失效
标题翻译：驻车制动器电缆和调整系统没有电缆走线
公开(公告)号：US08381613B2
公开(公告)日：2013-02-26
申请号：US12832636
申请日：2010-07-08
申请人： Peter Revelis , Simon Chan , Mark Van Ryswyck
发明人： Peter Revelis , Simon Chan , Mark Van Ryswyck
IPC分类号： G05G1/04
CPC分类号： F16C1/14 , F16C2361/45 , Y10T74/20438 , Y10T74/20612
摘要： A self-adjusting parking brake actuator includes a brake lever that is movable between brake-released and brake-applied positions. In addition, the parking brake cable adjust system includes a self-adjustment assembly having a frame; a rack mounted for movement relative to the frame along a longitudinal direction of the rack in a tension direction and an opposite direction; a cable connector for operatively connecting the rack to a brake cable, a first resilient member biasing the rack relative to the frame along its longitudinal direction in the tensioning direction, a primary locking device configured to engage the rack and permit movement of the rack relative to the frame in the tensioning direction only; a secondary locking device moveable between (a) a locking to lock the primary locking device to prevent adjusting movement of the rack relative to the frame in the tensioning direction, and (b) a releasing position to permit the primary locking device to allow adjusting movement of the rack relative to the frame in the tensioning direction by the biasing of the resilient member; and a second resilient member biasing the secondary locking device to the locking position.
摘要翻译：自调节驻车制动器致动器包括可在制动释放和制动施加位置之间移动的制动杆。另外，驻车制动器电缆调节系统包括具有框架的自调节组件; 安装用于沿张紧方向和相反方向沿着所述齿条的纵向方向相对于所述框架移动的齿条; 电缆连接器，用于将机架可操作地连接到制动电缆;第一弹性构件，其沿着拉伸方向上的纵向方向相对于框架偏置框架;主锁定装置，构造成接合机架并允许机架相对于框架仅在张紧方向; 辅助锁定装置可以在（a）锁定以锁定主锁定装置之间移动以防止在张紧方向上调节齿条相对于框架的运动，以及（b）释放位置以允许主锁定装置允许调节运动通过弹性构件的偏置而相对于框架在张紧方向上的支架; 以及将所述辅助锁定装置偏置到所述锁定位置的第二弹性构件。

3. 发明申请

US20120006143A1 PARKING BRAKE CABLE AND ADJUST SYSTEM HAVING NO LOST CABLE TRAVEL 失效
标题翻译：停车制动电缆和调整系统没有失去电缆行驶
公开(公告)号：US20120006143A1
公开(公告)日：2012-01-12
申请号：US12832636
申请日：2010-07-08
申请人： Peter REVELIS , Simon Chan , Mark Van Ryswyck
发明人： Peter REVELIS , Simon Chan , Mark Van Ryswyck
IPC分类号： F16C1/12
CPC分类号： F16C1/14 , F16C2361/45 , Y10T74/20438 , Y10T74/20612
摘要： A self-adjusting parking brake actuator includes a brake lever that is movable between brake-released and brake-applied positions. In addition, the parking brake cable adjust system includes a self-adjustment assembly having a frame; a rack mounted for movement relative to the frame along a longitudinal direction of the rack in a tension direction and an opposite direction; a cable connector for operatively connecting the rack to a brake cable, a first resilient member biasing the rack relative to the frame along its longitudinal direction in the tensioning direction, a primary locking device configured to engage the rack and permit movement of the rack relative to the frame in the tensioning direction only; a secondary locking device moveable between (a) a locking to lock the primary locking device to prevent adjusting movement of the rack relative to the frame in the tensioning direction, and (b) a releasing position to permit the primary locking device to allow adjusting movement of the rack relative to the frame in the tensioning direction by the biasing of the resilient member; and a second resilient member biasing the secondary locking device to the locking position.
摘要翻译：自调节驻车制动器致动器包括可在制动释放和制动施加位置之间移动的制动杆。另外，驻车制动器电缆调节系统包括具有框架的自调节组件; 安装用于沿张紧方向和相反方向沿着所述齿条的纵向方向相对于所述框架移动的齿条; 电缆连接器，用于将机架可操作地连接到制动电缆;第一弹性构件，其沿着拉伸方向上的纵向方向相对于框架偏置框架;主锁定装置，构造成接合机架并允许机架相对于框架仅在张紧方向; 辅助锁定装置可以在（a）锁定以锁定主锁定装置之间移动以防止在张紧方向上调节齿条相对于框架的运动，以及（b）释放位置以允许主锁定装置允许调节运动通过弹性构件的偏置而相对于框架在张紧方向上的支架; 以及将所述辅助锁定装置偏置到所述锁定位置的第二弹性构件。

4. 发明申请

US20050124170A1 Strained semiconductor substrate and processes therefor 有权
标题翻译：应变半导体衬底及其工艺
公开(公告)号：US20050124170A1
公开(公告)日：2005-06-09
申请号：US10729479
申请日：2003-12-05
申请人： Mario Pelella , Simon Chan
发明人： Mario Pelella , Simon Chan
IPC分类号： C30B25/18 , H01L21/20 , H01L21/304 , H01L21/762 , H01L21/31
CPC分类号： H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/3043 , H01L29/7842
摘要： A method of manufacturing an integrated circuit (IC) can utilizes semiconductor substrate configured in accordance with a trench process. The substrate utilizes trenches in a base layer to induce stress in a layer. The substrate can include silicon. The trenches define pillars on a back side of a bulk substrate or base layer of a semiconductor-on-insulator (SOI) wafer.
摘要翻译：集成电路（IC）的制造方法可以利用根据沟槽工艺配置的半导体衬底。衬底利用基层中的沟槽以在层中引起应力。衬底可以包括硅。沟槽在绝缘体上半导体（SOI）晶片的体基板或基底层的背侧上限定支柱。

5. 发明授权

US6043153A Method for reducing electromigration in a copper interconnect 失效
标题翻译：减少铜互连中电迁移的方法
公开(公告)号：US6043153A
公开(公告)日：2000-03-28
申请号：US937915
申请日：1997-09-25
申请人： Takeshi Nogami , Simon Chan
发明人： Takeshi Nogami , Simon Chan
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76877 , H01L21/76841
摘要： A system and method for providing copper interconnect in a trench formed in a dielectric is disclosed. In one aspect, the method and system include providing a copper layer; removing a portion of the copper layer outside of the trench; annealing the copper layer; and providing a layer disposed above the copper layer. In another aspect, the method and system include providing a copper interconnect formed in a trench on a dielectric. The copper interconnect includes a copper layer disposed in the trench and a layer disposed above the copper layer. The copper layer has a bamboo structure at least one grain. The at least one grain has substantially one orientation.
摘要翻译：公开了一种用于在形成在电介质中的沟槽中提供铜互连的系统和方法。一方面，所述方法和系统包括提供铜层; 去除所述沟槽外部的所述铜层的一部分; 退火铜层; 并提供设置在铜层之上的层。在另一方面，该方法和系统包括提供形成在电介质上的沟槽中的铜互连。铜互连包括设置在沟槽中的铜层和设置在铜层上方的层。铜层至少有一颗竹结构。至少一个颗粒具有基本上一个取向。

6. 发明授权

US08735960B2 High ultraviolet light absorbance silicon oxynitride film for improved flash memory device performance 有权
标题翻译：高紫外光吸收氧氮化硅薄膜，用于改善闪存器件性能
公开(公告)号：US08735960B2
公开(公告)日：2014-05-27
申请号：US12313134
申请日：2008-11-17
申请人： Minh Q. Tran , Minh-Van Ngo , Alexander H. Nickel , Sung Jin Kim , Simon Chan , Ning Cheng
发明人： Minh Q. Tran , Minh-Van Ngo , Alexander H. Nickel , Sung Jin Kim , Simon Chan , Ning Cheng
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L23/485 , H01L29/66825 , H01L2924/0002 , H01L2924/00
摘要： An ultraviolet light absorbent silicon oxynitride layer overlies a memory cell including a pair of source/drains, a gate insulator, a floating gate, a dielectric layer, and a control gate. A conductor is disposed through the silicon oxynitride layer for electrical connection to the control gate, and another conductor is disposed through the silicon oxynitride layer for electrical connection to a source/drain.
摘要翻译：紫外线吸收剂氮氧化硅层覆盖包括一对源极/漏极，栅极绝缘体，浮动栅极，电介质层和控制栅极的存储单元。导电体通过硅氧氮化物层设置，用于与控制栅极电连接，并且另一个导体通过氧氮化硅层设置，用于电连接到源极/漏极。

7. 发明授权

US08618354B2 Generation of haploid plants and improved plant breeding 有权
公开(公告)号：US08618354B2
公开(公告)日：2013-12-31
申请号：US12898216
申请日：2010-10-05
申请人： Simon Chan , Ravi Maruthachalam
发明人： Simon Chan , Ravi Maruthachalam
IPC分类号： C12N15/82 , A01H5/10 , C12N15/29 , C12N15/62 , C07K14/415 , A01H1/08
CPC分类号： A01H1/08 , A01H1/02 , C07K14/415 , C12N15/8241 , C12N15/8261 , C12N15/8287 , Y02A40/146
摘要： Methods and compositions for generating haploid organisms are described.

8. 发明申请

US20050263753A1 Semiconductor substrate layer configured for inducement of compressive or expansive force 有权
标题翻译：构造成用于诱导压缩或膨胀力的半导体衬底层
公开(公告)号：US20050263753A1
公开(公告)日：2005-12-01
申请号：US11179282
申请日：2005-07-12
申请人： Mario Pelella , Simon Chan
发明人： Mario Pelella , Simon Chan
IPC分类号： C30B25/18 , H01L21/20 , H01L21/304 , H01L21/762 , H01L29/06
CPC分类号： H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/3043 , H01L29/7842
摘要： An integrated circuit (IC) utilizes a strained layer. The substrate can utilize trenches in a base layer to induce stress in a layer. The trenches define pillars on a back side of a bulk substrate or base layer of a semiconductor-on-insulator (SOI) wafer.
摘要翻译：集成电路（IC）利用应变层。衬底可以利用基层中的沟槽以在层中诱导应力。沟槽在绝缘体上半导体（SOI）晶片的体基板或基底层的背侧上限定支柱。

9. 发明申请

US20050158963A1 Method of forming planarized shallow trench isolation 审中-公开
标题翻译：形成平坦化浅沟槽隔离的方法
公开(公告)号：US20050158963A1
公开(公告)日：2005-07-21
申请号：US10759207
申请日：2004-01-20
申请人： Darin Chan , Simon Chan , Angela Hui
发明人： Darin Chan , Simon Chan , Angela Hui
IPC分类号： H01L21/762 , H01L21/76 , H01L21/336
CPC分类号： H01L21/76224
摘要： Planarized STI with minimized topography is formed by selectively etching back the dielectric trench fill with respect to the polish stop film prior to removing the polish stop film. Embodiments include etching back a silicon oxide trench filled to a depth of about 200 Å to about 1,500 Å, and then stripping a silicon nitride polish stop layer leaving a substantially planarized surface, thereby improving the accuracy of subsequent gate electrode patterning and reducing stringers.
摘要翻译：通过在去除抛光停止膜之前相对于抛光止挡膜选择性地蚀刻回介质沟槽填充物而形成具有最小化形貌的平坦化STI。实施例包括将填充至大约至大约深度的氧化硅沟槽刻蚀，然后剥离留下基本平坦化表面的氮化硅抛光停止层，从而提高随后的栅电极图案化和减少桁条的精度。

10. 发明申请

US20050048731A1 Siliciding spacer in integrated circuit technology 审中-公开
标题翻译：集成电路技术中的硅化间隔器
公开(公告)号：US20050048731A1
公开(公告)日：2005-03-03
申请号：US10654123
申请日：2003-09-02
申请人： Jeffrey Patton , Mehrdad Mahanpour , Thorsten Kammler , David Brown , Paul Besser , Simon Chan , Austin Frenkel
发明人： Jeffrey Patton , Mehrdad Mahanpour , Thorsten Kammler , David Brown , Paul Besser , Simon Chan , Austin Frenkel
IPC分类号： H01L21/336 , H01L21/4763
CPC分类号： H01L29/665 , H01L29/6656 , H01L29/6659
摘要： A method of forming an integrated circuit and a structure therefore is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. Shallow source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate. Deep source/drain junctions are formed in the semiconductor substrate using the sidewall spacer. A siliciding spacer is formed over the sidewall spacer after forming the shallow and deep source/drain junctions. A silicide is formed on the deep source/drain junctions adjacent the siliciding spacer, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the silicide.
摘要翻译：因此，提供了形成集成电路和结构的方法。在半导体衬底上形成栅极电介质，并且在栅极电介质上形成栅极。在半导体衬底中形成浅源极/漏极结。在栅极周围形成侧壁间隔物。使用侧壁间隔物在半导体衬底中形成深源极/漏极结。在形成浅的和深的源极/漏极结之后，在侧壁间隔物上形成硅化间隔物。在邻近硅化间隔物的深源极/漏极结上形成硅化物，并且在半导体衬底上沉积电介质层。然后在电介质层中形成与硅化物的接触。

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