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1. 发明申请

US20050216873A1 Method of checking the layout versus the schematic of multi-fingered MOS transistor layouts using a sub-circuit based extraction 失效
标题翻译：使用基于子电路的提取来检查布局与多指MOS晶体管布局的示意图的方法
公开(公告)号：US20050216873A1
公开(公告)日：2005-09-29
申请号：US10807478
申请日：2004-03-23
申请人： Raminderpal Singh , Yue Tan , Jean-Oliver Plouchart , Lawrence Wagner , Mohamed Talbi , John Safran , Kun Wu
发明人： Raminderpal Singh , Yue Tan , Jean-Oliver Plouchart , Lawrence Wagner , Mohamed Talbi , John Safran , Kun Wu
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5022
摘要： A sub-circuit based extraction method which extracts a multi-finger MOS transistor directly as a sub-circuit is described. By adding three marking layers, the method provides the layout extracted netlist with a complete list of device geometric parameters corresponding to the device properties as presented in the sub-circuit model based schematic netlist. By performing a layout-versus-schematic comparison based on all geometric parameters extracted, the layout checking is performed in a complete and accurate way where each device parameter is checked against the corresponding design schematic. This complete and accurate geometric parameter comparison enhances the confidence level of the layout physical verification.
摘要翻译：描述了一种基于子电路的提取方法，其直接提取多指状MOS晶体管作为子电路。通过添加三个标记层，该方法为布局提取的网表提供了与基于子电路模型的示意图网表中所示的设备属性对应的设备几何参数的完整列表。通过基于提取的所有几何参数执行布局与原理图比较，以完整和准确的方式执行布局检查，其中根据相应的设计原理图检查每个设备参数。这种完整和准确的几何参数比较增强了布局物理验证的置信度。

2. 发明授权

US07139990B2 Method of checking the layout versus the schematic of multi-fingered MOS transistor layouts using a sub-circuit based extraction 失效
标题翻译：使用基于子电路的提取来检查布局与多指MOS晶体管布局的示意图的方法
公开(公告)号：US07139990B2
公开(公告)日：2006-11-21
申请号：US10807478
申请日：2004-03-23
申请人： Raminderpal Singh , Yue Tan , Jean-Oliver Plouchart , Lawrence F. Wagner, Jr. , Mohamed Talbi , John M. Safran , Kun Wu
发明人： Raminderpal Singh , Yue Tan , Jean-Oliver Plouchart , Lawrence F. Wagner, Jr. , Mohamed Talbi , John M. Safran , Kun Wu
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5022
摘要： A sub-circuit based extraction method which extracts a multi-finger MOS transistor directly as a sub-circuit is described. By adding three marking layers, the method provides the layout extracted netlist with a complete list of device geometric parameters corresponding to the device properties as presented in the sub-circuit model based schematic netlist. By performing a layout-versus-schematic comparison based on all geometric parameters extracted, the layout checking is performed in a complete and accurate way where each device parameter is checked against the corresponding design schematic. This complete and accurate geometric parameter comparison enhances the confidence level of the layout physical verification.
摘要翻译：描述了一种基于子电路的提取方法，其直接提取多指状MOS晶体管作为子电路。通过添加三个标记层，该方法为布局提取的网表提供了与基于子电路模型的示意图网表中所示的设备属性对应的设备几何参数的完整列表。通过基于提取的所有几何参数执行布局与原理图比较，以完整和准确的方式执行布局检查，其中根据相应的设计原理图检查每个设备参数。这种完整和准确的几何参数比较增强了布局物理验证的置信度。

3. 发明授权

US07765021B2 Method to check model accuracy during wafer patterning simulation 失效
标题翻译：在晶圆图案模拟期间检查模型精度的方法
公开(公告)号：US07765021B2
公开(公告)日：2010-07-27
申请号：US12015077
申请日：2008-01-16
申请人： Scott M. Mansfield , Lars W. Liebmann , Mohamed Talbi
发明人： Scott M. Mansfield , Lars W. Liebmann , Mohamed Talbi
IPC分类号： G06F19/00 , G06F17/50 , G06K9/00
CPC分类号： G03F7/70508 , G03F1/36 , G03F1/68 , G03F7/705
摘要： A method, and computer program product and system for performing the method, is provided for designing a mask used in the manufacture of semiconductor integrated circuits, in which a model of the lithographic process is used during the mask design process. More particularly, the on-wafer process model is a function of optical image parameters that are calibrated using measurements from a test pattern. An uncertainty metric for the predicted response simulated by the on-wafer process model is computed for a given evaluation point of interest as a function of a distance metric between the collective optical image parameters simulated at the given evaluation point and the collective optical image parameters at the calibration data points. The uncertainty metric preferably is also a function of the sensitivity of the on-wafer process model response to changes in the optical image parameters.
摘要翻译：提供了一种用于执行该方法的方法和计算机程序产品和系统，用于设计在半导体集成电路的制造中使用的掩模，其中在掩模设计过程中使用光刻处理的模型。更具体地，在晶片上的工艺模型是使用来自测试图案的测量校准的光学图像参数的函数。对于给定的感兴趣评估点，计算由晶片上过程模型模拟的预测响应的不确定性度量，作为在给定评估点处模拟的总体光学图像参数与集体光学图像参数之间的距离度量的函数校准数据点。不确定性度量优选地也是晶片上工艺模型响应对光学图像参数变化的灵敏度的函数。

4. 发明申请

US20090182448A1 METHOD TO CHECK MODEL ACCURACY DURING WAFER PATTERNING SIMULATION 失效
标题翻译：在WAFER模式中检查模型精度的方法
公开(公告)号：US20090182448A1
公开(公告)日：2009-07-16
申请号：US12015077
申请日：2008-01-16
申请人： Scott M. Mansfield , Lars W. Liebmann , Mohamed Talbi
发明人： Scott M. Mansfield , Lars W. Liebmann , Mohamed Talbi
IPC分类号： G06F17/00
CPC分类号： G03F7/70508 , G03F1/36 , G03F1/68 , G03F7/705
摘要： A method, and computer program product and system for performing the method, is provided for designing a mask used in the manufacture of semiconductor integrated circuits, in which a model of the lithographic process is used during the mask design process. More particularly, the on-wafer process model is a function of optical image parameters that are calibrated using measurements from a test pattern. An uncertainty metric for the predicted response simulated by the on-wafer process model is computed for a given evaluation point of interest as a function of a distance metric between the collective optical image parameters simulated at the given evaluation point and the collective optical image parameters at the calibration data points. The uncertainty metric preferably is also a function of the sensitivity of the on-wafer process model response to changes in the optical image parameters.
摘要翻译：提供了一种用于执行该方法的方法和计算机程序产品和系统，用于设计在半导体集成电路的制造中使用的掩模，其中在掩模设计过程中使用光刻处理的模型。更具体地，在晶片上的工艺模型是使用来自测试图案的测量校准的光学图像参数的函数。对于给定的感兴趣评估点，计算由晶片上过程模型模拟的预测响应的不确定性度量，作为在给定评估点处模拟的总体光学图像参数与集体光学图像参数之间的距离度量的函数校准数据点。不确定性度量优选地也是晶片上工艺模型响应对光学图像参数变化的灵敏度的函数。

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