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1. 发明授权

US5986473A Differential, mixed swing, tristate driver circuit for high performance and low power on-chip interconnects 失效
标题翻译：差分，混合摆幅，三态驱动电路，用于高性能和低功耗片上互连
公开(公告)号：US5986473A
公开(公告)日：1999-11-16
申请号：US1449
申请日：1997-12-31
申请人： Ram Kumar Krishnamurthy , Vivek De , Krishnamurthy Soumyanath
发明人： Ram Kumar Krishnamurthy , Vivek De , Krishnamurthy Soumyanath
IPC分类号： H03K19/0175 , H03K19/017 , H03K19/0185
CPC分类号： H03K19/01707 , H03K19/018521
摘要： A driver to provide low voltage swings on a bus with fast switching times, the driver comprising two pairs of pullup and pulldown nMOSFETs, each pair operated in complementary fashion to each other, each pair with a high voltage rail at a smaller voltage than the data input logic HIGH voltage, and where each substrate of the nMOSFETs are biased so as to reduce their threshold voltages.
摘要翻译：驱动器在总线上提供低电压摆幅，具有快速的开关时间，驱动器包括两对上拉和下拉nMOSFET，每对互为互补的方式互相连接，每对具有电压低于数据的高压轨输入逻辑高电压，并且其中nMOSFET的每个衬底被偏置以便降低它们的阈值电压。

2. 发明申请

US20120099630A1 PROGRAMMABLE ENGINE HAVING A RECONFIGURABLE ACCELERATOR DATA PATH FOR TESTING AND CALIBRATION OF ANALOG FRONT ENDS IN RADIO DEVICES 有权
标题翻译：具有可重构加速器数据路径的可编程发动机，用于在无线电设备中测试和校准模拟前端
公开(公告)号：US20120099630A1
公开(公告)日：2012-04-26
申请号：US12910129
申请日：2010-10-22
申请人： Marian K. Verhelst , Hasnain Lakdawala , Krishnamurthy Soumyanath , Masoud Sajadieh
发明人： Marian K. Verhelst , Hasnain Lakdawala , Krishnamurthy Soumyanath , Masoud Sajadieh
IPC分类号： H04B17/00
CPC分类号： H04B17/16
摘要： Briefly, in accordance with one or more embodiments, a radio device comprises an analog front end comprising a radio to transmit and/or receive radio-frequency signals, and a programmable engine coupled to the analog front end. The programmable engine is capable of being programmed to perform one or more tests on the analog front end and includes a reconfigurable data path reconfigurable by the programmable engine to perform one or more tests on the analog front end.
摘要翻译：简而言之，根据一个或多个实施例，无线电设备包括模拟前端，其包括用于发射和/或接收射频信号的无线电装置，以及耦合到模拟前端的可编程引擎。可编程引擎能够被编程为对模拟前端执行一个或多个测试，并且包括由可编程引擎重新配置以在模拟前端执行一个或多个测试的可重构数据路径。

3. 发明授权

US07565393B2 Discrete time filter having gain for digital sampling receivers 失效
标题翻译：具有数字采样接收机增益的离散时间滤波器
公开(公告)号：US07565393B2
公开(公告)日：2009-07-21
申请号：US11169808
申请日：2005-06-29
申请人： Hasnain Lakdawala , Krishnamurthy Soumyanath , Stewart S. Taylor , Stefan H. Andersson
发明人： Hasnain Lakdawala , Krishnamurthy Soumyanath , Stewart S. Taylor , Stefan H. Andersson
IPC分类号： G06G7/02
CPC分类号： H03H15/00
摘要： A discrete time filter achieves gain by sampling a signal using capacitors arranged in a one configuration and then changing the capacitors to a series configuration to develop a filter output voltage. In at least one embodiment, a variable gain filter is achieved by varying the number of capacitors that are active in the filter.
摘要翻译：离散时间滤波器通过使用以一种配置布置的电容器对信号进行采样，然后将电容器改变为串联配置来产生滤波器输出电压来实现增益。在至少一个实施例中，通过改变在滤波器中有效的电容器的数量来实现可变增益滤波器。

4. 发明申请

US20090039981A1 System and Method for Controlling Resonance Frequency of Film Bulk Acoustic Resonator Devices 有权
标题翻译：用于控制膜体积声谐振器器件的谐振频率的系统和方法
公开(公告)号：US20090039981A1
公开(公告)日：2009-02-12
申请号：US11836538
申请日：2007-08-09
申请人： Hiroyuki Ito , Hasnain Lakdawala , Ashoke Ravi , Krishnamurthy Soumyanath
发明人： Hiroyuki Ito , Hasnain Lakdawala , Ashoke Ravi , Krishnamurthy Soumyanath
IPC分类号： H03H9/13
CPC分类号： H03H19/004 , H03H9/02007 , H03H2009/02204
摘要： Disclosed is a system and method for controlling a resonance frequency of a Film Bulk Acoustic Resonator (FBAR) device. The system includes at least one switching capacitor coupled to the FBAR device and a modulator. The at least one switching capacitor includes at least one capacitor and a switch configuration disposed in series with the FBAR device and the at least one capacitor, which is switch configuration capable of opening and closing connection of the at least one capacitor with the FBAR device. The modulator is coupled to the switch configuration, which generates a switching condition signal based on the manufacturing variation in the FBAR device and the environmental effects on the FBAR device. The switch configuration performs opening and closing of the connection of the at least one capacitor and the FBAR device based on the switching condition signal.
摘要翻译：公开了一种用于控制膜体声波谐振器（FBAR）装置的谐振频率的系统和方法。该系统包括耦合到FBAR器件和调制器的至少一个开关电容器。所述至少一个开关电容器包括至少一个电容器和与所述FBAR器件和所述至少一个电容器串联布置的开关配置，所述至少一个电容器是能够打开和关闭所述至少一个电容器与所述FBAR器件的连接的开关配置。调制器耦合到开关配置，其根据FBAR器件的制造变化和对FBAR器件的环境影响产生开关条件信号。开关配置基于开关条件信号来执行至少一个电容器和FBAR器件的连接的打开和闭合。

5. 发明申请

US20070008208A1 Filter with gain 有权
公开(公告)号：US20070008208A1
公开(公告)日：2007-01-11
申请号：US11178625
申请日：2005-07-11
申请人： Hasnain Lakdawala , Ashoke Ravi , Georgios Palaskas , Stefan Andersson , Krishnamurthy Soumyanath
发明人： Hasnain Lakdawala , Ashoke Ravi , Georgios Palaskas , Stefan Andersson , Krishnamurthy Soumyanath
IPC分类号： H03M1/12
CPC分类号： H03H15/02
摘要： Embodiments of a filter with gain are presented herein.

6. 发明授权

US07161404B2 Single event upset hardened latch 有权
标题翻译：单个事件镦粗硬化闩锁
公开(公告)号：US07161404B2
公开(公告)日：2007-01-09
申请号：US10742436
申请日：2003-12-19
申请人： Peter Hazucha , Krishnamurthy Soumyanath
发明人： Peter Hazucha , Krishnamurthy Soumyanath
IPC分类号： H03K3/289
CPC分类号： H03K3/356156 , H03K3/012 , H03K3/0375 , H03K3/356173
摘要： A hardened latch capable of providing protection against single event upsets (SEUs) is disclosed. The hardened latch includes a first latch and a second latch that mirrors a subset of gates of the first latch. The second latch is inserted in the feedback path of the keeper circuit of the first latch and is cross-coupled with the gates of the keeper circuit of the first latch. The latch is hardened against single event upsets and an arbitrary number of successive SEUs attacking a single node, provided that the time between successive SEUs is larger than the recovery time of the latch. An alternate embodiment of the hardened latch includes a split buffer output. This embodiment is capable of reducing the propagation of erroneous transients. Another alternate embodiment of the hardened latch includes a Miller C buffer output. This embodiment is capable of reducing the propagation of erroneous transients below the level achievable in a hardened latch employing a split buffer output.
摘要翻译：公开了一种能够提供针对单个事件扰乱（SEU）的保护的硬化锁存器。硬化的锁存器包括第一锁存器和第二锁存器，其对第一锁存器的门的子集进行镜像。第二锁存器插入在第一锁存器的保持器电路的反馈路径中，并且与第一锁存器的保持器电路的栅极交叉耦合。如果连续的SEU之间的时间大于锁存器的恢复时间，则锁存器会针对单个事件扰乱和任意数量的连续的SEU进行加固。硬化锁存器的替代实施例包括分离缓冲器输出。该实施例能够减少错误瞬变的传播。硬化锁存器的另一替代实施例包括米勒C缓冲器输出。该实施例能够将错误瞬变的传播降低到使用分离缓冲器输出的硬化锁存器中可实现的电平以下。

7. 发明授权

US07049855B2 Area efficient waveform evaluation and DC offset cancellation circuits 有权
公开(公告)号：US07049855B2
公开(公告)日：2006-05-23
申请号：US09896345
申请日：2001-06-28
申请人： Krishnamurthy Soumyanath , Luiz Franca-Neto
发明人： Krishnamurthy Soumyanath , Luiz Franca-Neto
IPC分类号： G01R19/00
CPC分类号： H03L7/0891 , G01R19/02 , G01R19/04 , H03F1/30 , H03L7/093 , H03L7/183 , H03L7/23
摘要： Analog circuits for providing one or more waveform parameters, e.g., the DC offset or average, of an analog input signal. Separate biasing is not necessarily required. Some embodiments comprise field-effect-transistors (FETs) configured in various diode-connected configurations that take advantage of leakage currents through the FETs so that long resistors or large capacitors are not necessarily required. One embodiment comprises two diode-connected FETs to provide an unbiased DC offset voltage of an analog input signal.

8. 发明授权

US06204696B1 Domino circuits with high performance and high noise immunity 有权
标题翻译：具有高性能和高抗噪声能力的多米诺电路
公开(公告)号：US06204696B1
公开(公告)日：2001-03-20
申请号：US09158410
申请日：1998-09-22
申请人： Ram K. Krishnamurthy , Krishnamurthy Soumyanath
发明人： Ram K. Krishnamurthy , Krishnamurthy Soumyanath
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： In some embodiments, the invention includes a domino circuit having a precharge circuit including a source follower nFET device coupled to a domino stage conductor. An evaluation path circuit is also coupled to the domino stage conductor. A hysteretic output stage receives a signal from the domino stage conductor and provide therefrom an evaluated output signal. In other embodiments, the invention includes a domino circuit having a predischarge circuit coupled to a domino stage conductor. An evaluation path circuit includes source follower nFET devices coupled to the domino stage conductor. A hysteretic output stage receives a signal from the domino stage conductor and provides therefrom an evaluated output signal. In still other embodiments, the invention includes a domino circuit having a precharge circuit including coupled to a domino stage conductor. An evaluation path circuit is coupled to the domino stage conductor. An output stage includes an inverter to receive a signal from the domino stage conductor and to provide an evaluated output signal on an output conductor, the output stage including a duplicate evaluation path circuit coupled to an output conductor.
摘要翻译：在一些实施例中，本发明包括具有预充电电路的多米诺骨牌电路，该预充电电路包括耦合到多米诺骨牌导体的源极跟随器nFET器件。评估路径电路也耦合到多米诺骨牌导体。迟滞输出级接收来自多米诺骨牌级导体的信号并从其提供评估的输出信号。在其他实施例中，本发明包括具有耦合到多米诺骨牌导体的预放电电路的多米诺骨牌电路。评估路径电路包括耦合到多米诺骨牌导体的源极跟随器nFET器件。滞后输出级接收来自多米诺骨牌级导体的信号并从其提供评估的输出信号。在其他实施例中，本发明包括具有预充电电路的多米诺骨牌电路，其包括耦合到多米诺骨牌导体。评估路径电路耦合到多米诺骨牌导体。输出级包括反相器，用于从多米诺骨架导体接收信号并在输出导体上提供评估输出信号，输出级包括耦合到输出导体的重复评估路径电路。

9. 发明申请

US20070001754A1 Discrete time filter having gain for digital sampling receivers 失效
标题翻译：具有数字采样接收机增益的离散时间滤波器
公开(公告)号：US20070001754A1
公开(公告)日：2007-01-04
申请号：US11169808
申请日：2005-06-29
申请人： Hasnain Lakdawala , Krishnamurthy Soumyanath , Stewart Taylor , Stefan Anderson
发明人： Hasnain Lakdawala , Krishnamurthy Soumyanath , Stewart Taylor , Stefan Anderson
IPC分类号： H03K5/00
CPC分类号： H03H15/00
摘要： A discrete time filter achieves gain by sampling a signal using capacitors arranged in a one configuration and then changing the capacitors to a series configuration to develop a filter output voltage. In at least one embodiment, a variable gain filter is achieved by varying the number of capacitors that are active in the filter.
摘要翻译：离散时间滤波器通过使用以一种配置布置的电容器对信号进行采样，然后将电容器改变为串联配置来产生滤波器输出电压来实现增益。在至少一个实施例中，通过改变在滤波器中有效的电容器的数量来实现可变增益滤波器。

10. 发明授权

US07119628B2 Adaptively extending tunable range of frequency in a closed loop 有权
标题翻译：在闭环中自适应地扩展频率的可调范围
公开(公告)号：US07119628B2
公开(公告)日：2006-10-10
申请号：US10985511
申请日：2004-11-10
申请人： Ashoke Ravi , Krishnamurthy Soumyanath
发明人： Ashoke Ravi , Krishnamurthy Soumyanath
IPC分类号： H03L7/08
CPC分类号： H03L7/18 , H03L7/0898 , H03L7/093 , H03L7/107
摘要： A semiconductor device or a circuit includes a controllable oscillator and circuitry that senses a voltage which may control the controllable oscillator and digitally controls a gain compensation, adaptively compensating for a drop in a gain against overall loop gain within a closed loop. In one embodiment, a single supply source may be used to power the closed loop while a variable gain stage that is digitally controllable may adjust the gain in a feed-forward manner based on the drop.
摘要翻译：半导体器件或电路包括可控振荡器和电路，其感测可控制可控振荡器并且数字控制增益补偿的电压，自适应地补偿增益中的下降与闭环内的整体环路增益。在一个实施例中，可以使用单个供电源为闭环供电，而可数字控制的可变增益级可以基于该下降以前馈方式调节增益。

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