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1. 发明授权

US06597623B2 Low power architecture for register files 有权
标题翻译：注册文件的低功耗体系结构
公开(公告)号：US06597623B2
公开(公告)日：2003-07-22
申请号：US09896349
申请日：2001-06-28
申请人： Ram Krishnamurthy , Ganesh Balamurugan
发明人： Ram Krishnamurthy , Ganesh Balamurugan
IPC分类号： G11C800
CPC分类号： G11C8/10 , G06F9/30141
摘要： A low power architecture for register files is provided. A decoder receives a specified bit address divided into a first input and a second input. The decoder is split into a first stage and a second stage. A pre-decoder in the first stage receives the first input, identifies a local bitline that is accessed, and outputs a first signal to a register file array. A post decoder in the second stage receives the second input and the first signal, processes the identification of the local bitline, and generates a second signal to be sent to the register file array. A delay synchronizes the first signal and the second signal so that both signals reach the register file array simultaneously.
摘要翻译：提供了一种用于注册文件的低功耗架构。解码器接收分成第一输入和第二输入的指定位地址。解码器被分成第一阶段和第二阶段。第一级的预解码器接收第一输入，识别被访问的本地位线，并将第一信号输出到寄存器文件阵列。第二级的后解码器接收第二输入和第一信号，处理本地位线的识别，并产生要发送到寄存器文件阵列的第二信号。延迟同步第一信号和第二信号，使得两个信号同时到达寄存器文件阵列。

2. 发明申请

US20140204490A1 DISTRIBUTED ELECTROSTATIC DISCHARGE PROTECTION FOR AN ON-PACKAGE INPUT/OUTPUT ARCHITECTURE 有权
标题翻译：分布式输入/输出结构的分布式静电放电保护
公开(公告)号：US20140204490A1
公开(公告)日：2014-07-24
申请号：US13995111
申请日：2011-12-22
申请人： Todd W. Mellinger , Michael E. Griffith , Ganesh Balamurugan , Thomas P. Thomas
发明人： Todd W. Mellinger , Michael E. Griffith , Ganesh Balamurugan , Thomas P. Thomas
IPC分类号： H02H9/04 , G06F1/16
CPC分类号： H02H9/046 , G06F1/16 , G06F1/1613 , H01L27/0255 , H03K19/00361
摘要： An on-package interface. A first set of single-ended transmitter circuits on a first die. A first set of single-ended receiver circuits on a second die. The receiver circuits have a termination circuit comprising an inverter and a resistive feedback element. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines are matched.
摘要翻译：一个封装接口。第一组第一组单端发射机电路。第二组芯片上的第一组单端接收器电路。接收器电路具有包括反相器和电阻反馈元件的终端电路。多条导线耦合第一组发射机电路和第一组接收机电路。多条导线的长度相匹配。

3. 发明申请

US20140089549A1 NON-LINEAR TERMINATION FOR AN ON-PACKAGE INPUT/OUTPUT ARCHITECTURE 有权
标题翻译：用于封装输入/输出结构的非线性终止
公开(公告)号：US20140089549A1
公开(公告)日：2014-03-27
申请号：US13995110
申请日：2011-12-22
申请人： Todd W. Mellinger , Michael E. Griffith , Ganesh Balamurugan , Thomas P. Thomas , Rajesh Kumar
发明人： Todd W. Mellinger , Michael E. Griffith , Ganesh Balamurugan , Thomas P. Thomas , Rajesh Kumar
IPC分类号： G06F13/36
CPC分类号： G06F13/4086 , G06F13/14 , G06F13/36 , Y02D10/14 , Y02D10/151
摘要： An on-package interface. A first set of single-ended transmitter circuits on a first die. A first set of single-ended receiver circuits on a second die. The receiver circuits have a termination circuit comprising an inverter and a resistive feedback element. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines arc matched.
摘要翻译：一个封装接口。第一组第一组单端发射机电路。第二组芯片上的第一组单端接收器电路。接收器电路具有包括反相器和电阻反馈元件的终端电路。多条导线耦合第一组发射机电路和第一组接收机电路。多个导线的长度匹配。

4. 发明申请

US20050134369A1 Method and apparatus to perform on-die waveform capture 有权
标题翻译：执行管芯上波形捕获的方法和装置
公开(公告)号：US20050134369A1
公开(公告)日：2005-06-23
申请号：US10743349
申请日：2003-12-23
申请人： Bryan Casper , Aaron Martin , James Jaussi , Stephen Mooney , Ganesh Balamurugan
发明人： Bryan Casper , Aaron Martin , James Jaussi , Stephen Mooney , Ganesh Balamurugan
IPC分类号： H03F1/02
CPC分类号： H03K5/19
摘要： An integrated circuit is provided that includes a first port to receive a first signal from a first channel and a first device coupled to the first port to modify a channel response of the first signal received from the first channel. A waveform capture device may be coupled to the first device to capture a waveform of a signal modified by the first device.
摘要翻译：提供一种集成电路，其包括从第一信道接收第一信号的第一端口和耦合到第一端口的第一设备，以修改从第一信道接收的第一信号的信道响应。波形捕获装置可以耦合到第一装置以捕获由第一装置修改的信号的波形。

5. 发明申请

US20050053125A1 Adaptive equalization using a conditional update sign-sign least mean square algorithm 有权
标题翻译：使用条件更新符号最小均方算法进行自适应均衡
公开(公告)号：US20050053125A1
公开(公告)日：2005-03-10
申请号：US10660228
申请日：2003-09-10
申请人： Ganesh Balamurugan , Bryan Casper , James Jaussi , Stephen Mooney
发明人： Ganesh Balamurugan , Bryan Casper , James Jaussi , Stephen Mooney
IPC分类号： H03H21/00 , H04L25/03 , H03K5/159
CPC分类号： H03H21/0043 , H03H21/0001 , H03H2021/0065 , H04L25/03038 , H04L25/03885 , H04L2025/03477 , H04L2025/03617
摘要： An adaptive equalizer finite impulse response (FIR) filter for high-speed communication channels with modest complexity, where the filter is iteratively updated during a training sequence by a circuit performing the update: {overscore (h)}(t+1)={overscore (h)}(t)+μ[sgn{d(t)}−sgn{z(t)−Kd(t)}]sgn{{overscore (x)}(t)}, where {overscore (h)}(t) is the filter vector representing the filter taps of the FIR filter, {overscore (x)}(t) is the data vector representing present and past samples of the received data x(t), d(t) is the desired data used for training, z(t) is the output of the FIR filter, μ determines the memory or window size of the adaptation, and K is a scale factor taking into account practical limitations of the communication channel, receiver, and equalizer. Furthermore, a procedure and circuit structure is provided for calibrating the scale factor K.
摘要翻译：用于具有适度复杂度的高速通信信道的自适应均衡器有限脉冲响应（FIR）滤波器，其中在训练序列期间通过执行更新的电路迭代地更新滤波器：{overscore（h（t + 1）= {overscore（ h（t）+ mu [sgn {d（t）} - sgn {z（t）-Kd（t）}] sgn {{overscore（x（t）}，其中{overscore（h（t）表示FIR滤波器的滤波器抽头的向量{overscore（x（t））是表示接收数据x（t）的当前和过去样本的数据向量，d（t）是用于训练的期望数据，z ）是FIR滤波器的输出，mu确定适配的存储器或窗口大小，K是考虑到通信信道，接收机和均衡器的实际限制的比例因子，并且提供了一个过程和电路结构用于校准比例因子K.

6. 发明授权

US06388940B1 Leakage-tolerant circuit and method for large register files 有权
标题翻译：大容量寄存器文件的漏电电路及方法
公开(公告)号：US06388940B1
公开(公告)日：2002-05-14
申请号：US09672177
申请日：2000-09-27
申请人： Atila Alvandpour , Ganesh Balamurugan , Krishnamurthy Soumyanath
发明人： Atila Alvandpour , Ganesh Balamurugan , Krishnamurthy Soumyanath
IPC分类号： G11C800
CPC分类号： G11C7/12 , G11C11/419
摘要： A novel circuit technique for reducing leakage currents through the read-path of large register files in which a negative gate-source voltage is forced on a critical pass transistor between a cell read transistor and a local bitline such that when the cell is in a first state, the leakage current from a dynamic node of the cell read transistor is reduced. The reduced leakage current increases the robustness and performance of the read operation.
摘要翻译：一种新颖的电路技术，用于减小通过大寄存器堆的读路径的漏电流，其中在栅极读取晶体管和局部位线之间的临界传输晶体管上施加负栅极 - 源极电压，使得当单元处于第一状态，来自单元读取晶体管的动态节点的漏电流减小。减小的漏电流增加了读操作的鲁棒性和性能。

7. 发明授权

US08015429B2 Clock and data recovery (CDR) method and apparatus 有权
标题翻译：时钟和数据恢复（CDR）方法和设备
公开(公告)号：US08015429B2
公开(公告)日：2011-09-06
申请号：US12165428
申请日：2008-06-30
申请人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
发明人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
IPC分类号： G06F1/12 , G06F1/04 , H03K9/00
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/091 , H04L7/0004
摘要： Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.
摘要翻译：公开了用于时钟和数据恢复的方法和装置的实施例。在一些实施例中，公开了一种用于从设备的输入数据流恢复数据的方法，所述方法包括在初始化阶段期间使具有输入数据流的数据时钟（DCK）同步; 在所述初始化阶段期间，使所述输入数据流的边缘时钟信号（ECK）至少部分地基于所述ECK和所述同步DCK之间的相位关系同步; 并且在初始化阶段期间，利用同步的ECK对输入数据流的上升沿进行采样，以产生转换电平参考电压。也可以公开和要求保护附加的变型和实施例。

8. 发明申请

US20100164539A1 SYSTEM AND APPARATUS OF RECONFIGURABLE TRANSCEIVER DESIGN FOR MULTI-MODE SIGNALING 有权
标题翻译：用于多模式信号的可重构收发器设计的系统和装置
公开(公告)号：US20100164539A1
公开(公告)日：2010-07-01
申请号：US12347858
申请日：2008-12-31
申请人： Ganesh Balamurugan , Bryan Casper
发明人： Ganesh Balamurugan , Bryan Casper
IPC分类号： H03K17/16
CPC分类号： H03K19/018585
摘要： A reconfigurable transceiver is claimed for a wide range of I/O systems. The reconfigurable transmitter of the reconfigurable transceiver is capable of transmitting multi-level signals in single-ended and differential modes by current and voltage mode signaling. The signal for transmission can be pre-emphasized for all transmitting modes. The reconfigurable transceiver can dynamically scale bandwidth and power consumption based on performance metrics.
摘要翻译：对于广泛的I / O系统要求可重新配置的收发器。可重配置收发器的可重构发射机能够通过电流和电压模式信令在单端和差模中传输多电平信号。可以对所有发送模式预先强调要传输的信号。可重新配置的收发器可以根据性能指标动态调整带宽和功耗。

9. 发明授权

US07286006B2 Sign-sign least means square filter 有权
标题翻译：符号最小的意思是方形滤波器
公开(公告)号：US07286006B2
公开(公告)日：2007-10-23
申请号：US10879417
申请日：2004-06-28
申请人： James E. Jaussi , Bryan K. Casper , Ganesh Balamurugan , Stephen R. Mooney
发明人： James E. Jaussi , Bryan K. Casper , Ganesh Balamurugan , Stephen R. Mooney
IPC分类号： H03K5/00
CPC分类号： H03H21/0043 , H03H21/0001 , H03H2021/0065
摘要： In some embodiments, an adaptive filter employs two adaptation modes, where during one adaptation mode the adaptive filter is updated only when the received training sample is a first binary value and during the other adaptation mode the adaptive filter is updated only when the received sample is a second binary value. Each adaptation mode provides a set of filter weights, and these two sets of filter weights are averaged to provide an adapted set of filter weights. The use of two adaptation mode allows for a clock boundary in which the digital portion of the filter operates at a lower clock rate than the analog portion. In other embodiments, a filter architecture is described for providing the algebraic signs of the received data samples, important for sign-sign least means square filtering algorithms. In other embodiments, a filter architecture is described in which efficient use is made of voltage-to-current converters so as to achieve a high throughput rate during filtering. Embodiments of the present invention have application to channel equalization.
摘要翻译：在一些实施例中，自适应滤波器采用两种适应模式，其中在一个自适应模式期间，只有当所接收的训练样本是第一二进制值时才自动滤波器被更新，并且在另一自适应模式期间，仅当所接收的样本是第二个二进制值。每个适配模式提供一组滤波器权重，并且将这两组滤波器权重进行平均以提供一组适用的滤波器权重。使用两个适配模式允许滤波器的数字部分以比模拟部分更低的时钟速率工作的时钟边界。在其他实施例中，描述了用于提供接收数据样本的代数符号的滤波器架构，对于符号最小均方滤波算法而言是重要的。在其他实施例中，描述了一种滤波器架构，其中有效地使用电压 - 电流转换器，以便在滤波期间实现高吞吐率。本发明的实施例具有对信道均衡的应用。

10. 发明申请

US20050286623A1 Adaptive filter structure with two adaptation modes 审中-公开
标题翻译：具有两种自适应模式的自适应滤波器结构
公开(公告)号：US20050286623A1
公开(公告)日：2005-12-29
申请号：US10879948
申请日：2004-06-28
申请人： James Jaussi , Bryan Casper , Ganesh Balamurugan , Stephen Mooney
发明人： James Jaussi , Bryan Casper , Ganesh Balamurugan , Stephen Mooney
IPC分类号： H03H15/00 , H03H21/00 , H03K5/159 , H04L25/03
CPC分类号： H03H15/00 , H03H21/0001 , H03H2015/007 , H04L25/03038 , H04L2025/03726
摘要： In some embodiments, an adaptive filter employs two adaptation modes, where during one adaptation mode the adaptive filter is updated only when the received training sample is a first binary value and during the other adaptation mode the adaptive filter is updated only when the received sample is a second binary value. Each adaptation mode provides a set of filter weights, and these two sets of filter weights are averaged to provide an adapted set of filter weights. The use of two adaptation mode allows for a clock boundary in which the digital portion of the filter operates at a lower clock rate than the analog portion. In other embodiments, a filter architecture is described for providing the algebraic signs of the received data samples, important for sign-sign least means square filtering algorithms. In other embodiments, a filter architecture is described in which efficient use is made of voltage-to-current converters so as to achieve a high throughput rate during filtering. Embodiments of the present invention have application to channel equalization.
摘要翻译：在一些实施例中，自适应滤波器采用两种适应模式，其中在一个自适应模式期间，只有当所接收的训练样本是第一二进制值时才自动滤波器被更新，并且在另一自适应模式期间，仅当所接收的样本是第二个二进制值。每个适配模式提供一组滤波器权重，并且将这两组滤波器权重进行平均以提供一组适用的滤波器权重。使用两个适配模式允许滤波器的数字部分以比模拟部分更低的时钟速率工作的时钟边界。在其他实施例中，描述了用于提供接收数据样本的代数符号的滤波器架构，对于符号最小均方滤波算法而言是重要的。在其他实施例中，描述了一种滤波器架构，其中有效地使用电压 - 电流转换器，以便在滤波期间实现高吞吐率。本发明的实施例具有对信道均衡的应用。

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