专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07286006B2 Sign-sign least means square filter 有权
标题翻译：符号最小的意思是方形滤波器
公开(公告)号：US07286006B2
公开(公告)日：2007-10-23
申请号：US10879417
申请日：2004-06-28
申请人： James E. Jaussi , Bryan K. Casper , Ganesh Balamurugan , Stephen R. Mooney
发明人： James E. Jaussi , Bryan K. Casper , Ganesh Balamurugan , Stephen R. Mooney
IPC分类号： H03K5/00
CPC分类号： H03H21/0043 , H03H21/0001 , H03H2021/0065
摘要： In some embodiments, an adaptive filter employs two adaptation modes, where during one adaptation mode the adaptive filter is updated only when the received training sample is a first binary value and during the other adaptation mode the adaptive filter is updated only when the received sample is a second binary value. Each adaptation mode provides a set of filter weights, and these two sets of filter weights are averaged to provide an adapted set of filter weights. The use of two adaptation mode allows for a clock boundary in which the digital portion of the filter operates at a lower clock rate than the analog portion. In other embodiments, a filter architecture is described for providing the algebraic signs of the received data samples, important for sign-sign least means square filtering algorithms. In other embodiments, a filter architecture is described in which efficient use is made of voltage-to-current converters so as to achieve a high throughput rate during filtering. Embodiments of the present invention have application to channel equalization.
摘要翻译：在一些实施例中，自适应滤波器采用两种适应模式，其中在一个自适应模式期间，只有当所接收的训练样本是第一二进制值时才自动滤波器被更新，并且在另一自适应模式期间，仅当所接收的样本是第二个二进制值。每个适配模式提供一组滤波器权重，并且将这两组滤波器权重进行平均以提供一组适用的滤波器权重。使用两个适配模式允许滤波器的数字部分以比模拟部分更低的时钟速率工作的时钟边界。在其他实施例中，描述了用于提供接收数据样本的代数符号的滤波器架构，对于符号最小均方滤波算法而言是重要的。在其他实施例中，描述了一种滤波器架构，其中有效地使用电压 - 电流转换器，以便在滤波期间实现高吞吐率。本发明的实施例具有对信道均衡的应用。

2. 发明授权

US07289557B2 Adaptive equalization using a conditional update sign-sign least mean square algorithm 有权
标题翻译：使用条件更新符号最小均方算法进行自适应均衡
公开(公告)号：US07289557B2
公开(公告)日：2007-10-30
申请号：US10660228
申请日：2003-09-10
申请人： Ganesh Balamurugan , Bryan K. Casper , James E. Jaussi , Stephen R. Mooney
发明人： Ganesh Balamurugan , Bryan K. Casper , James E. Jaussi , Stephen R. Mooney
IPC分类号： H03D3/22 , H04L27/22
CPC分类号： H03H21/0043 , H03H21/0001 , H03H2021/0065 , H04L25/03038 , H04L25/03885 , H04L2025/03477 , H04L2025/03617
摘要： An adaptive equalizer finite impulse response (FIR) filter for high-speed communication channels with modest complexity, where the filter is iteratively updated during a training sequence by a circuit performing the update: h(t+1)= h(t)+μ[sgn{d(t)}−sgn{z(t)−Kd(t)}]sgn{ x(t)}, where h(t) is the filter vector representing the filter taps of the FIR filter, x(t) is the data vector representing present and past samples of the received data x(t), d(t) is the desired data used for training, z(t) is the output of the FIR filter, μ determines the memory or window size of the adaptation, and K is a scale factor taking into account practical limitations of the communication channel, receiver, and equalizer. Furthermore, a procedure and circuit structure is provided for calibrating the scale factor K.
摘要翻译：用于具有适度复杂度的高速通信信道的自适应均衡器有限脉冲响应（FIR）滤波器，其中通过执行更新的电路在训练序列期间迭代地更新滤波器：<？in-line-formula description =“In-line 公式“end =”lead“？> h（t + 1）= h（t）+ mu [sgn {d（t）} - t）-Kd（t）}] sgn { x（t）}，<？in-line-formula description =“In-line Formulas”end =“tail”？> OSTYLE =“SINGLE”> h（t）是表示FIR滤波器的滤波器抽头的滤波器向量，x（t）是表示接收数据的当前和过去采样的数据x（t） t），d（t）是用于训练的期望数据，z（t）是FIR滤波器的输出，mu决定适配的存储器或窗口大小，K是考虑到实际限制的比例因子通信信道，接收机和均衡器。此外，提供了用于校准比例因子K的过程和电路结构。

3. 发明授权

US07529296B2 Adaptive equalization method and circuit for continuous run-time adaptation 有权
标题翻译：用于连续运行时适应的自适应均衡方法和电路
公开(公告)号：US07529296B2
公开(公告)日：2009-05-05
申请号：US11232492
申请日：2005-09-21
申请人： James E. Jaussi , Bryan K. Casper , Ganesh Balamurugan , Stephen R. Mooney
发明人： James E. Jaussi , Bryan K. Casper , Ganesh Balamurugan , Stephen R. Mooney
IPC分类号： H03K5/159
CPC分类号： H04L25/03057 , H04L2025/03598 , H04L2025/03681
摘要： In some embodiments disclosed herein, equalizers in a receiver are adapted during normal operation, as they extract bit data from a received bit stream, to account for channel and/or circuit fluctuations.
摘要翻译：在本文公开的一些实施例中，接收机中的均衡器在正常操作期间被适配，因为它们从接收到的比特流中提取比特数据，以解决信道和/或电路波动。

4. 发明授权

US07313181B2 Calibration of scale factor in adaptive equalizers 有权
标题翻译：自适应均衡器中比例因子校准
公开(公告)号：US07313181B2
公开(公告)日：2007-12-25
申请号：US10660415
申请日：2003-09-10
申请人： Ganesh Balamurugan , Bryan K. Casper , James E. Jaussi , Stephen R. Mooney
发明人： Ganesh Balamurugan , Bryan K. Casper , James E. Jaussi , Stephen R. Mooney
IPC分类号： H03H7/30 , G06F17/10
CPC分类号： H04L25/03038 , H03H21/0001 , H03H2021/0065 , H04L2025/03477
摘要： An adaptive equalizer finite impulse response (FIR) filter for high-speed communication channels with modest complexity, where the filter is iteratively updated during a training sequence by a circuit performing the update: h(t+1)= h(t)+μ[sgn{d(t)}−sgn{z(t)−Kd(t)}]sgn{ x(t)}, where h(t) is the filter vector representing the filter taps of the FIR filter, x(t) is the data vector representing present and past samples of the received data x(t), d(t) is the desired data used for training, z(t) is the output of the FIR filter, μ determines the memory or window size of the adaptation, and K is a scale factor taking into account practical limitations of the communication channel, receiver, and equalizer. Furthermore, a procedure and circuit structure is provided for calibrating the scale factor K.
摘要翻译：用于具有适度复杂度的高速通信信道的自适应均衡器有限脉冲响应（FIR）滤波器，其中通过执行更新的电路在训练序列期间迭代地更新滤波器： h（t + 1 ）= h（t）+ mu [sgn {d（t-sgn {z（t）-Kd（t）sgn { x（t）}，其中 h（t）是表示FIR滤波器的滤波器抽头的滤波器向量， x（t）是表示接收到的当前和过去样本的数据向量数据x（t），d（t）是用于训练的期望数据，z（t）是FIR滤波器的输出，μ确定适配的存储器或窗口大小，K是考虑到的比例因子通信信道，接收机和均衡器的实际限制。此外，提供了用于校准比例因子K的过程和电路结构。

5. 发明授权

US07275004B2 Method and apparatus to perform on-die waveform capture 有权
标题翻译：执行管芯上波形捕获的方法和装置
公开(公告)号：US07275004B2
公开(公告)日：2007-09-25
申请号：US10743349
申请日：2003-12-23
申请人： Bryan K. Casper , Aaron K. Martin , James E. Jaussi , Stephen R. Mooney , Ganesh Balamurugan
发明人： Bryan K. Casper , Aaron K. Martin , James E. Jaussi , Stephen R. Mooney , Ganesh Balamurugan
IPC分类号： G06F19/00
CPC分类号： H03K5/19
摘要： An integrated circuit is provided that includes a first port to receive a first signal from a first channel and a first device coupled to the first port to modify a channel response of the first signal received from the first channel. A waveform capture device may be coupled to the first device to capture a waveform of a signal modified by the first device.
摘要翻译：提供一种集成电路，其包括从第一信道接收第一信号的第一端口和耦合到第一端口的第一设备，以修改从第一信道接收到的第一信号的信道响应。波形捕获装置可以耦合到第一装置以捕获由第一装置修改的信号的波形。

6. 发明授权

US08015429B2 Clock and data recovery (CDR) method and apparatus 有权
标题翻译：时钟和数据恢复（CDR）方法和设备
公开(公告)号：US08015429B2
公开(公告)日：2011-09-06
申请号：US12165428
申请日：2008-06-30
申请人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
发明人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
IPC分类号： G06F1/12 , G06F1/04 , H03K9/00
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/091 , H04L7/0004
摘要： Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.
摘要翻译：公开了用于时钟和数据恢复的方法和装置的实施例。在一些实施例中，公开了一种用于从设备的输入数据流恢复数据的方法，所述方法包括在初始化阶段期间使具有输入数据流的数据时钟（DCK）同步; 在所述初始化阶段期间，使所述输入数据流的边缘时钟信号（ECK）至少部分地基于所述ECK和所述同步DCK之间的相位关系同步; 并且在初始化阶段期间，利用同步的ECK对输入数据流的上升沿进行采样，以产生转换电平参考电压。也可以公开和要求保护附加的变型和实施例。

7. 发明授权

US08375242B2 Clock and data recovery (CDR) method and apparatus 有权
标题翻译：时钟和数据恢复（CDR）方法和设备
公开(公告)号：US08375242B2
公开(公告)日：2013-02-12
申请号：US13196871
申请日：2011-08-02
申请人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
发明人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
IPC分类号： G06F1/12 , G06F1/04 , H04L27/00
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/091 , H04L7/0004
摘要： Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.
摘要翻译：公开了用于时钟和数据恢复的方法和装置的实施例。在一些实施例中，公开了一种用于从设备的输入数据流恢复数据的方法，所述方法包括在初始化阶段期间使具有输入数据流的数据时钟（DCK）同步; 在所述初始化阶段期间，使所述输入数据流的边缘时钟信号（ECK）至少部分地基于所述ECK和所述同步DCK之间的相位关系同步; 并且在初始化阶段期间，利用同步的ECK对输入数据流的上升沿进行采样，以产生转换电平参考电压。也可以公开和要求保护附加的变型和实施例。

8. 发明申请

US20110289341A1 CLOCK AND DATA RECOVERY (CDR) METHOD AND APPARATUS 有权
标题翻译：时钟和数据恢复（CDR）方法和装置
公开(公告)号：US20110289341A1
公开(公告)日：2011-11-24
申请号：US13196871
申请日：2011-08-02
申请人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
发明人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
IPC分类号： G06F1/12 , G06F1/04
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/091 , H04L7/0004
摘要： Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.
摘要翻译：公开了用于时钟和数据恢复的方法和装置的实施例。在一些实施例中，公开了一种用于从设备的输入数据流恢复数据的方法，所述方法包括在初始化阶段期间使具有输入数据流的数据时钟（DCK）同步; 在所述初始化阶段期间，使所述输入数据流的边缘时钟信号（ECK）至少部分地基于所述ECK和所述同步DCK之间的相位关系同步; 并且在初始化阶段期间，利用同步的ECK对输入数据流的上升沿进行采样，以产生转换电平参考电压。也可以公开和要求保护附加的变型和实施例。

9. 发明申请

US20090327788A1 CLOCK AND DATA RECOVERY (CDR) METHOD AND APPARATUS 有权
标题翻译：时钟和数据恢复（CDR）方法和装置
公开(公告)号：US20090327788A1
公开(公告)日：2009-12-31
申请号：US12165428
申请日：2008-06-30
申请人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
发明人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
IPC分类号： G06F1/12
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/091 , H04L7/0004
摘要： Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.
摘要翻译：公开了用于时钟和数据恢复的方法和装置的实施例。在一些实施例中，公开了一种用于从设备的输入数据流恢复数据的方法，所述方法包括在初始化阶段期间使具有输入数据流的数据时钟（DCK）同步; 在所述初始化阶段期间，使所述输入数据流的边缘时钟信号（ECK）至少部分地基于所述ECK和所述同步DCK之间的相位关系同步; 并且在初始化阶段期间，利用同步的ECK对输入数据流的上升沿进行采样，以产生转换电平参考电压。也可以公开和要求保护附加的变型和实施例。

10. 发明申请

US20140204490A1 DISTRIBUTED ELECTROSTATIC DISCHARGE PROTECTION FOR AN ON-PACKAGE INPUT/OUTPUT ARCHITECTURE 有权
标题翻译：分布式输入/输出结构的分布式静电放电保护
公开(公告)号：US20140204490A1
公开(公告)日：2014-07-24
申请号：US13995111
申请日：2011-12-22
申请人： Todd W. Mellinger , Michael E. Griffith , Ganesh Balamurugan , Thomas P. Thomas
发明人： Todd W. Mellinger , Michael E. Griffith , Ganesh Balamurugan , Thomas P. Thomas
IPC分类号： H02H9/04 , G06F1/16
CPC分类号： H02H9/046 , G06F1/16 , G06F1/1613 , H01L27/0255 , H03K19/00361
摘要： An on-package interface. A first set of single-ended transmitter circuits on a first die. A first set of single-ended receiver circuits on a second die. The receiver circuits have a termination circuit comprising an inverter and a resistive feedback element. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines are matched.
摘要翻译：一个封装接口。第一组第一组单端发射机电路。第二组芯片上的第一组单端接收器电路。接收器电路具有包括反相器和电阻反馈元件的终端电路。多条导线耦合第一组发射机电路和第一组接收机电路。多条导线的长度相匹配。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式