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1. 发明授权

US08048330B2 Method of forming an interlayer dielectric material having different removal rates during CMP 有权
标题翻译：在CMP期间形成具有不同去除速率的层间电介质材料的方法
公开(公告)号：US08048330B2
公开(公告)日：2011-11-01
申请号：US12127921
申请日：2008-05-28
申请人： Ralf Richter , Thomas Foltyn , Anthony Mowry
发明人： Ralf Richter , Thomas Foltyn , Anthony Mowry
IPC分类号： B44C1/22 , H01L21/304
CPC分类号： H01L29/7843 , H01L21/02164 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/31612 , H01L21/76801 , H01L21/76819 , H01L21/76825 , H01L29/665 , H01L29/66772 , H01L29/78654
摘要： By providing an interlayer dielectric material with different removal rates, a desired minimum material height above gate electrode structures of sophisticated transistor devices of the 65 nm technology or 45 nm technology may be obtained. The reduced removal rate above the gate electrode may thus provide enhanced process robustness during the planarization of the interlayer dielectric layer stack prior to the formation of contact elements.
摘要翻译：通过提供具有不同去除速率的层间电介质材料，可以获得在65nm技术或45nm技术的复杂晶体管器件的栅电极结构之上所需的最小材料高度。因此，在形成接触元件之前，在层间电介质层叠层的平坦化期间，栅电极之上的减小的去除速率可以提供增强的工艺稳定性。

2. 发明申请

US20090170319A1 METHOD OF FORMING AN INTERLAYER DIELECTRIC MATERIAL HAVING DIFFERENT REMOVAL RATES DURING CMP 有权
标题翻译：在CMP期间形成具有不同去除速率的中间层介电材料的方法
公开(公告)号：US20090170319A1
公开(公告)日：2009-07-02
申请号：US12127921
申请日：2008-05-28
申请人： Ralf Richter , Thomas Foltyn , Anthony Mowry
发明人： Ralf Richter , Thomas Foltyn , Anthony Mowry
IPC分类号： H01L21/304
CPC分类号： H01L29/7843 , H01L21/02164 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/31612 , H01L21/76801 , H01L21/76819 , H01L21/76825 , H01L29/665 , H01L29/66772 , H01L29/78654
摘要： By providing an interlayer dielectric material with different removal rates, a desired minimum material height above gate electrode structures of sophisticated transistor devices of the 65 nm technology or 45 nm technology may be obtained. The reduced removal rate above the gate electrode may thus provide enhanced process robustness during the planarization of the interlayer dielectric layer stack prior to the formation of contact elements.
摘要翻译：通过提供具有不同去除速率的层间电介质材料，可以获得在65nm技术或45nm技术的复杂晶体管器件的栅电极结构之上所需的最小材料高度。因此，在形成接触元件之前，在层间电介质层叠层的平坦化期间，栅电极之上的减小的去除速率可以提供增强的工艺稳定性。

3. 发明申请

US20090108466A1 SEMICONDUCTOR DEVICE AND METHOD FOR PATTERNING VERTICAL CONTACTS AND METAL LINES IN A COMMON ETCH PROCESS 有权
标题翻译：用于在常见蚀刻过程中绘制垂直接触和金属线的半导体器件和方法
公开(公告)号：US20090108466A1
公开(公告)日：2009-04-30
申请号：US12103765
申请日：2008-04-16
申请人： Ralf Richter , Robert Seidel , Juergen Boemmels , Thomas Foltyn
发明人： Ralf Richter , Robert Seidel , Juergen Boemmels , Thomas Foltyn
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/7681 , H01L21/76811 , H01L21/76816
摘要： Interlayer connections, i.e., vertical connections, may be formed on the basis of a hard mask material, which may be positioned below, within or above an interlayer dielectric material, wherein one lateral dimension is defined by a trench mask, thereby obtaining a desired interlayer connection in a common patterning process. Furthermore, the thickness of at least certain portions of the metal lines may be adjusted with a high degree of flexibility, thereby providing the possibility of significantly reducing the overall resistivity of metal lines in metal levels, in which device performance may significantly depend on resistivity rather than parasitic capacitance.
摘要翻译：中间层连接（即垂直连接）可以基于硬掩模材料形成，硬掩模材料可以位于层间电介质材料的内部或之上，其中一个横向尺寸由沟槽掩模限定，从而获得所需的中间层连接在共同的图案化过程中。此外，金属线的至少某些部分的厚度可以以高度的柔性来调节，从而提供了显着降低金属线中金属线的整体电阻率的可能性，其中器件性能可能显着地取决于电阻率比寄生电容。

4. 发明申请

US20120220119A1 SEMICONDUCTOR DEVICE AND METHOD FOR PATTERNING VERTICAL CONTACTS AND METAL LINES IN A COMMON ETCH PROCESS 有权
标题翻译：用于在常见蚀刻过程中绘制垂直接触和金属线的半导体器件和方法
公开(公告)号：US20120220119A1
公开(公告)日：2012-08-30
申请号：US13468083
申请日：2012-05-10
申请人： Ralf Richter , Robert Seidel , Juergen Boemmels , Thomas Foltyn
发明人： Ralf Richter , Robert Seidel , Juergen Boemmels , Thomas Foltyn
IPC分类号： H01L21/768 , H01L21/308
CPC分类号： H01L21/7681 , H01L21/76811 , H01L21/76816
摘要： Interlayer connections, i.e., vertical connections, may be formed on the basis of a hard mask material, which may be positioned below, within or above an interlayer dielectric material, wherein one lateral dimension is defined by a trench mask, thereby obtaining a desired interlayer connection in a common patterning process. Furthermore, the thickness of at least certain portions of the metal lines may be adjusted with a high degree of flexibility, thereby providing the possibility of significantly reducing the overall resistivity of metal lines in metal levels, in which device performance may significantly depend on resistivity rather than parasitic capacitance.
摘要翻译：中间层连接（即垂直连接）可以基于硬掩模材料形成，硬掩模材料可以位于层间电介质材料的内部或之上，其中一个横向尺寸由沟槽掩模限定，从而获得所需的中间层连接在共同的图案化过程中。此外，金属线的至少某些部分的厚度可以以高度的柔性来调节，从而提供了显着降低金属线中金属线的整体电阻率的可能性，其中器件性能可能显着地取决于电阻率比寄生电容。

5. 发明授权

US08741770B2 Semiconductor device and method for patterning vertical contacts and metal lines in a common etch process 有权
标题翻译：在普通蚀刻工艺中用于图案化垂直接触和金属线的半导体器件和方法
公开(公告)号：US08741770B2
公开(公告)日：2014-06-03
申请号：US13468083
申请日：2012-05-10
申请人： Ralf Richter , Robert Seidel , Juergen Boemmels , Thomas Foltyn
发明人： Ralf Richter , Robert Seidel , Juergen Boemmels , Thomas Foltyn
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/7681 , H01L21/76811 , H01L21/76816
摘要： Interlayer connections, i.e., vertical connections, may be formed on the basis of a hard mask material, which may be positioned below, within or above an interlayer dielectric material, wherein one lateral dimension is defined by a trench mask, thereby obtaining a desired interlayer connection in a common patterning process. Furthermore, the thickness of at least certain portions of the metal lines may be adjusted with a high degree of flexibility, thereby providing the possibility of significantly reducing the overall resistivity of metal lines in metal levels, in which device performance may significantly depend on resistivity rather than parasitic capacitance.
摘要翻译：中间层连接（即垂直连接）可以基于硬掩模材料形成，硬掩模材料可以位于层间电介质材料的内部或之上，其中一个横向尺寸由沟槽掩模限定，从而获得所需的中间层连接在共同的图案化过程中。此外，金属线的至少某些部分的厚度可以以高度的柔性来调节，从而提供了显着降低金属线中金属线的整体电阻率的可能性，其中器件性能可能显着地取决于电阻率比寄生电容。

6. 发明授权

US08212184B2 Cold temperature control in a semiconductor device 有权
标题翻译：半导体器件中的冷温度控制
公开(公告)号：US08212184B2
公开(公告)日：2012-07-03
申请号：US12390816
申请日：2009-02-23
申请人： Anthony Mowry , Casey Scott , Maciej Wiatr , Ralf Richter
发明人： Anthony Mowry , Casey Scott , Maciej Wiatr , Ralf Richter
IPC分类号： H05B1/00 , H01L35/00
CPC分类号： H01L23/345 , H01L23/34 , H01L27/0248 , H01L27/0629 , H01L2924/0002 , H01L2924/00
摘要： Operation of complex integrated circuits at low temperatures may be enhanced by providing active heating elements within the integrated circuit so as to raise the temperature of at least critical circuit portions at respective operational phases, such as upon power-up. Consequently, enhanced cold temperature performance may be obtained on the basis of existing process elements in order to provide design stability without requiring extensive circuit simulation or redesign of well-established circuit architectures.
摘要翻译：可以通过在集成电路内提供主动加热元件来提高复杂集成电路在低温下的操作，以便在诸如上电时在各个操作阶段提高至少关键电路部分的温度。因此，可以在现有工艺元件的基础上获得增强的冷温度性能，以便提供设计稳定性，而不需要广泛的电路仿真或重新设计已建立的电路架构。

7. 发明授权

US08198190B2 Semiconductor device and method for patterning vertical contacts and metal lines in a common etch process 有权
标题翻译：在普通蚀刻工艺中用于图案化垂直接触和金属线的半导体器件和方法
公开(公告)号：US08198190B2
公开(公告)日：2012-06-12
申请号：US12103765
申请日：2008-04-16
申请人： Ralf Richter , Robert Seidel , Juergen Boemmels , Thomas Foltyn
发明人： Ralf Richter , Robert Seidel , Juergen Boemmels , Thomas Foltyn
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/7681 , H01L21/76811 , H01L21/76816
摘要： Interlayer connections, i.e., vertical connections, may be formed on the basis of a hard mask material, which may be positioned below, within or above an interlayer dielectric material, wherein one lateral dimension is defined by a trench mask, thereby obtaining a desired interlayer connection in a common patterning process. Furthermore, the thickness of at least certain portions of the metal lines may be adjusted with a high degree of flexibility, thereby providing the possibility of significantly reducing the overall resistivity of metal lines in metal levels, in which device performance may significantly depend on resistivity rather than parasitic capacitance.
摘要翻译：中间层连接（即垂直连接）可以基于硬掩模材料形成，硬掩模材料可以位于层间电介质材料的内部或之上，其中一个横向尺寸由沟槽掩模限定，从而获得所需的中间层连接在共同的图案化过程中。此外，金属线的至少某些部分的厚度可以以高度的柔性来调节，从而提供了显着降低金属线中金属线的整体电阻率的可能性，其中器件性能可能显着地取决于电阻率比寄生电容。

8. 发明申请

US20090295457A1 COLD TEMPERATURE CONTROL IN A SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件中的温度控制
公开(公告)号：US20090295457A1
公开(公告)日：2009-12-03
申请号：US12390816
申请日：2009-02-23
申请人： Anthony Mowry , Casey Scott , Maciej Wiatr , Ralf Richter
发明人： Anthony Mowry , Casey Scott , Maciej Wiatr , Ralf Richter
IPC分类号： H01L35/00
CPC分类号： H01L23/345 , H01L23/34 , H01L27/0248 , H01L27/0629 , H01L2924/0002 , H01L2924/00
摘要： Operation of complex integrated circuits at low temperatures may be enhanced by providing active heating elements within the integrated circuit so as to raise the temperature of at least critical circuit portions at respective operational phases, such as upon power-up. Consequently, enhanced cold temperature performance may be obtained on the basis of existing process elements in order to provide design stability without requiring extensive circuit simulation or redesign of well-established circuit architectures.
摘要翻译：可以通过在集成电路内提供主动加热元件来提高复杂集成电路在低温下的操作，以便在诸如上电时在各个操作阶段提高至少关键电路部分的温度。因此，可以在现有工艺元件的基础上获得增强的冷温度性能，以便提供设计稳定性，而不需要广泛的电路仿真或重新设计已建立的电路架构。

9. 发明授权

US09034744B2 Replacement gate approach for high-k metal gate stacks by avoiding a polishing process for exposing the placeholder material 有权
标题翻译：通过避免用于暴露占位符材料的抛光工艺，用于高k金属栅极堆叠的替代栅极方法
公开(公告)号：US09034744B2
公开(公告)日：2015-05-19
申请号：US12942200
申请日：2010-11-09
申请人： Ralf Richter , Jens Heinrich , Andy Wei
发明人： Ralf Richter , Jens Heinrich , Andy Wei
IPC分类号： H01L29/772 , H01L21/8238 , H01L21/768 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823842 , H01L21/76819 , H01L21/823807 , H01L29/66545 , H01L29/66583 , H01L29/7833 , H01L29/7843
摘要： In a replacement gate approach, the exposure of the placeholder material of the gate electrode structures may be accomplished on the basis of an etch process, thereby avoiding the introduction of process-related non-uniformities, which are typically associated with a complex polishing process for exposing the top surface of the placeholder material. In some illustrative embodiments, the placeholder material may be exposed by an etch process based on a sacrificial mask material.
摘要翻译：在替代栅极方法中，栅极电极结构的占位符材料的暴露可以基于蚀刻工艺来实现，从而避免引入与工艺相关的非均匀性，这通常与复杂的抛光工艺相关暴露占位符材料的顶面。在一些说明性实施例中，占位符材料可以通过基于牺牲掩模材料的蚀刻工艺曝光。

10. 发明授权

US08951907B2 Semiconductor devices having through-contacts and related fabrication methods 有权
标题翻译：具有通孔和相关制造方法的半导体器件
公开(公告)号：US08951907B2
公开(公告)日：2015-02-10
申请号：US12968068
申请日：2010-12-14
申请人： Ralf Richter , Jens Heinrich , Holger Schuehrer
发明人： Ralf Richter , Jens Heinrich , Holger Schuehrer
IPC分类号： H01L21/4763 , H01L21/768 , H01L21/285 , H01L23/485
CPC分类号： H01L21/76808 , H01L21/28512 , H01L21/76802 , H01L21/76897 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Apparatus for semiconductor device structures and related fabrication methods are provided. One method for fabricating a semiconductor device structure involves forming a layer of dielectric material overlying a doped region formed in a semiconductor substrate adjacent to a gate structure and forming a conductive contact in the layer of dielectric material. The conductive contact overlies and electrically connects to the doped region. The method continues by forming a second layer of dielectric material overlying the conductive contact, forming a voided region in the second layer overlying the conductive contact, forming a third layer of dielectric material overlying the voided region, and forming another voided region in the third layer overlying at least a portion of the voided region in the second layer. The method continues by forming a conductive material that fills both voided regions to contact the conductive contact.
摘要翻译：提供了半导体器件结构和相关制造方法的装置。一种用于制造半导体器件结构的方法包括形成覆盖在与栅极结构相邻的半导体衬底中形成的掺杂区域的介电材料层，并在该介电材料层中形成导电接触。导电接触覆盖并电连接到掺杂区域。该方法继续通过形成覆盖导电接触的第二层介电材料，在覆盖导电接触的第二层中形成空隙区域，形成覆盖空隙区域的第三层电介质材料，以及在第三层中形成另一个空隙区域覆盖第二层中的空隙区域的至少一部分。该方法通过形成填充两个空隙区域以接触导电触点的导电材料而继续。

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