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    • 1. 发明申请
    • Input circuit for an electronic circuit
    • 电子电路的输入电路
    • US20050239433A1
    • 2005-10-27
    • US11093870
    • 2005-03-30
    • Ralf KleinUllrich Menczigar
    • Ralf KleinUllrich Menczigar
    • G11C7/10H03K5/24H04B1/00H04B1/06H04B1/16
    • G11C7/1084G11C7/1078H03K5/2481
    • The invention relates to an input circuit for an electronic circuit, for receiving and assessing an input signal and for driving the input signal to a downstream circuit. The input circuit includes a first reception circuit which is configured to receive and drive the input signal and has a first current consumption characteristic, the current consumption of the first reception circuit depending on the input signal to be driven, a second reception circuit which is configured to receive and drive the input signal and has a second current consumption characteristic, the current consumption of the second reception circuit depending on the input signal to be driven, wherein the first reception circuit and the second reception circuit may be activated separately, and a control circuit configured to activate either the first reception circuit or the second reception circuit and to deactivate the respective other reception circuit on the basis of the driven input signal.
    • 本发明涉及一种用于电子电路的输入电路,用于接收和评估输入信号并将输入信号驱动到下游电路。 输入电路包括:第一接收电路,被配置为接收和驱动输入信号,并具有第一电流消耗特性,第一接收电路的电流消耗取决于要驱动的输入信号,第二接收电路被配置 接收和驱动输入信号并具有第二电流消耗特性,第二接收电路的电流消耗取决于要驱动的输入信号,其中第一接收电路和第二接收电路可以单独激活,并且控制 电路,被配置为激活第一接收电路或第二接收电路,并且基于所驱动的输入信号去激活相应的其他接收电路。
    • 2. 发明授权
    • Reducing current consumption for input circuit of an electronic circuit
    • 减少电子电路输入电路的电流消耗
    • US07564723B2
    • 2009-07-21
    • US11093870
    • 2005-03-30
    • Ralf KleinUllrich Menczigar
    • Ralf KleinUllrich Menczigar
    • G11C7/00
    • G11C7/1084G11C7/1078H03K5/2481
    • The invention relates to an input circuit for an electronic circuit, for receiving and assessing an input signal and for driving the input signal to a downstream circuit. The input circuit includes a first reception circuit which is configured to receive and drive the input signal and has a first current consumption characteristic, the current consumption of the first reception circuit depending on the input signal to be driven, a second reception circuit which is configured to receive and drive the input signal and has a second current consumption characteristic, the current consumption of the second reception circuit depending on the input signal to be driven, wherein the first reception circuit and the second reception circuit may be activated separately, and a control circuit configured to activate either the first reception circuit or the second reception circuit and to deactivate the respective other reception circuit on the basis of the driven input signal.
    • 本发明涉及一种用于电子电路的输入电路,用于接收和评估输入信号并将输入信号驱动到下游电路。 输入电路包括:第一接收电路,被配置为接收和驱动输入信号,并具有第一电流消耗特性,第一接收电路的电流消耗取决于要驱动的输入信号,第二接收电路被配置 接收和驱动输入信号并具有第二电流消耗特性,第二接收电路的电流消耗取决于要驱动的输入信号,其中第一接收电路和第二接收电路可以单独激活,并且控制 电路,被配置为激活第一接收电路或第二接收电路,并且基于所驱动的输入信号去激活相应的其他接收电路。
    • 10. 发明授权
    • Delay adjustment circuit
    • 延时调节电路
    • US06717447B1
    • 2004-04-06
    • US10271955
    • 2002-10-15
    • Thoai-Thai LeRalf Klein
    • Thoai-Thai LeRalf Klein
    • H03L700
    • H03L7/0814H03K2005/00058H03K2005/00234
    • A delay adjustment circuit for decreasing a phase shift between a system clock and a feedback clock from a semiconductor's internal clock. The circuit includes a difference-pulse generator that provides an interim clock 180 degrees out of phase with the feedback clock when the feedback clock is leading the system clock, and equal to the feedback clock otherwise. The difference-pulse generator also provides a difference-pulse signal that is at logic high for a period of time by which the system clock and an inversion of the interim clock are phase shifted. The circuit also includes a delay control unit and a delay unit which delay the interim clock by the period of time. The resulting delayed interim clock, which is 180 degrees out of phase with the system clock, is inverted to provide an internal clock in phase with the system clock.
    • 一种延迟调整电路,用于减少来自半导体内部时钟的系统时钟和反馈时钟之间的相移。 电路包括差分脉冲发生器,当反馈时钟引导系统时钟时,差分脉冲发生器提供与反馈时钟180度异相的中间时钟,否则等于反馈时钟。 差分脉冲发生器还提供在一段时间内处于逻辑高的差分脉冲信号,通过该时间段,系统时钟和中间时钟的反相相移。 该电路还包括一个延迟控制单元和延迟单元,该延迟单元将临时时钟延迟一段时间。 所产生的与系统时钟相差180度的延迟中间时钟被反相,以提供与系统时钟同相的内部时钟。