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1. 发明申请

US20070242497A1 Dynamic control of back gate bias in a FinFET SRAM cell 失效
标题翻译： FinFET SRAM单元中背栅偏置的动态控制
公开(公告)号：US20070242497A1
公开(公告)日：2007-10-18
申请号：US11402400
申请日：2006-04-12
申请人： Rajiv Joshi , Keunwoo Kim , Edward Nowak , Richard Williams
发明人： Rajiv Joshi , Keunwoo Kim , Edward Nowak , Richard Williams
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： The present invention provides dynamic control of back gate bias on pull-up pFETs in a FinFET SRAM cell. A method according to the present invention includes providing a bias voltage to a back gate of at least one transistor in the SRAM cell, and dynamically controlling the bias voltage based on an operational mode (e.g., Read, Half-Select, Write, Standby) of the SRAM cell.
摘要翻译：本发明提供对FinFET SRAM单元中的上拉pFET的背栅极偏置的动态控制。根据本发明的方法包括向SRAM单元中的至少一个晶体管的背栅提供偏置电压，并且基于操作模式（例如，读取，半选择，写入，待机）动态地控制偏置电压，的SRAM单元。

2. 发明申请

US20060274569A1 Semiconductor device including back-gated transistors and method of fabricating the device 有权
公开(公告)号：US20060274569A1
公开(公告)日：2006-12-07
申请号：US11142248
申请日：2005-06-02
申请人： Rajiv Joshi , Keunwoo Kim , Edward Nowak , Richard Williams
发明人： Rajiv Joshi , Keunwoo Kim , Edward Nowak , Richard Williams
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L27/0207 , H01L27/11 , H01L27/1104 , H01L29/66795 , H01L29/785
摘要： A memory cell (e.g., static random access memory (SRAM) cell) includes a plurality of back-gated n-type field effect transistors (nFETs), and a plurality of double-gated p-type field effect transistors (pFETs) operatively coupled to the plurality of nFETs.

3. 发明申请

US20050218427A1 Method for making a FET channel 有权
标题翻译：制造FET通道的方法
公开(公告)号：US20050218427A1
公开(公告)日：2005-10-06
申请号：US11137811
申请日：2005-05-24
申请人： Rajiv Joshi , Richard Williams
发明人： Rajiv Joshi , Richard Williams
IPC分类号： H01L20060101 , H01L21/336 , H01L21/8244 , H01L21/84 , H01L27/01 , H01L27/11 , H01L27/12 , H01L29/06 , H01L29/786 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/785 , H01L21/84 , H01L21/845 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/42392 , H01L29/66795 , H01L29/78687 , Y10S257/903
摘要： A channel 16 of a FinFET 10 has a channel core 24 and a channel envelope 32, each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and SixGe1-x, wherein 78
摘要翻译： FinFET 10的通道16具有沟道芯24和沟道封套32，每个沟道芯32由限定不同晶格结构的半导体材料制成以利用应变硅特性。栅极通过栅极电介质耦合到沟道封套。示例性材料是Si和Si x Ge 1-x x，其中78

4. 发明申请

US20080105898A1 FET Channel Having a Strained Lattice Structure Along Multiple Surfaces 审中-公开
标题翻译：具有沿多个表面的应变晶格结构的FET通道
公开(公告)号：US20080105898A1
公开(公告)日：2008-05-08
申请号：US11969992
申请日：2008-01-07
申请人： Rajiv Joshi , Richard Williams
发明人： Rajiv Joshi , Richard Williams
IPC分类号： H01L29/778
CPC分类号： H01L29/785 , H01L21/84 , H01L21/845 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/42392 , H01L29/66795 , H01L29/78687 , Y10S257/903
摘要： A channel 16 of a FinFET 10 has a channel core 24 and a channel envelope 32, each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and SiXGe1−x, wherein 78
摘要翻译： FinFET 10的通道16具有沟道芯24和沟道封套32，每个沟道芯32由限定不同晶格结构的半导体材料制成以利用应变硅特性。栅极通过栅极电介质耦合到沟道封套。示例性材料是Si和Si X 1 x 1-x x，其中78

5. 发明申请

US20050017377A1 FET channel having a strained lattice structure along multiple surfaces 有权
标题翻译： FET通道沿着多个表面具有应变格子结构
公开(公告)号：US20050017377A1
公开(公告)日：2005-01-27
申请号：US10626760
申请日：2003-07-21
申请人： Rajiv Joshi , Richard Williams
发明人： Rajiv Joshi , Richard Williams
IPC分类号： H01L20060101 , H01L21/336 , H01L21/8244 , H01L21/84 , H01L27/01 , H01L27/11 , H01L27/12 , H01L29/06 , H01L29/786 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/785 , H01L21/84 , H01L21/845 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/42392 , H01L29/66795 , H01L29/78687 , Y10S257/903
摘要： A channel 16 of a FinFET 10 has a channel core 24 and a channel envelope 32, each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and SixGe1-x, wherein 78
摘要翻译： FinFET 10的通道16具有沟道芯24和沟道封套32，每个沟道芯32由限定不同晶格结构的半导体材料制成以利用应变硅特性。栅极通过栅极电介质耦合到沟道封套。示例性材料是Si和SixGe1-x，其中78

6. 发明申请

US20080105900A1 FET Channel Having a Strained Lattice Structure Along Multiple Surfaces 审中-公开
标题翻译：具有沿多个表面的应变晶格结构的FET通道
公开(公告)号：US20080105900A1
公开(公告)日：2008-05-08
申请号：US11970011
申请日：2008-01-07
申请人： Rajiv Joshi , Richard Williams
发明人： Rajiv Joshi , Richard Williams
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L21/84 , H01L21/845 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/42392 , H01L29/66795 , H01L29/78687 , Y10S257/903
摘要： A channel 16 of a FinFET 10 has a channel core 24 and a channel envelope 32, each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and SixGe1-x, wherein 78
摘要翻译： FinFET 10的通道16具有沟道芯24和沟道封套32，每个沟道芯32由限定不同晶格结构的半导体材料制成以利用应变硅特性。栅极通过栅极电介质耦合到沟道封套。示例性材料是Si和Si x Ge 1-x x，其中78

7. 发明申请

US20070111406A1 FET Channel Having a Strained Lattice Structure Along Multiple Surfaces 审中-公开
标题翻译：具有沿多个表面的应变晶格结构的FET通道
公开(公告)号：US20070111406A1
公开(公告)日：2007-05-17
申请号：US11621290
申请日：2007-01-09
申请人： Rajiv Joshi , Richard Williams
发明人： Rajiv Joshi , Richard Williams
IPC分类号： H01L21/8232
CPC分类号： H01L29/785 , H01L21/84 , H01L21/845 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/42392 , H01L29/66795 , H01L29/78687 , Y10S257/903
摘要： A channel 16 of a FinFET 10 has a channel core 24 and a channel envelope 32, each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and SixGel1-x, wherein 78
摘要翻译： FinFET 10的通道16具有沟道芯24和沟道封套32，每个沟道芯32由限定不同晶格结构的半导体材料制成以利用应变硅特性。栅极通过栅极电介质耦合到沟道封套。示例性材料是Si和Si 1-x 1-x N，其中78

8. 发明申请

US20080083951A1 FETS WITH SELF-ALIGNED BODIES AND BACKGATE HOLES 审中-公开
标题翻译：具有自对准体和背部孔的FET
公开(公告)号：US20080083951A1
公开(公告)日：2008-04-10
申请号：US11869766
申请日：2007-10-10
申请人： Brent Anderson , Andres Bryant , Edward Nowak , Richard Williams
发明人： Brent Anderson , Andres Bryant , Edward Nowak , Richard Williams
IPC分类号： H01L27/12
CPC分类号： H01L29/78612 , H01L29/66772 , H01L29/78621 , H01L29/78648
摘要： Embodiments of the invention disclose a design structure for a FET with a shallow source/drain region, a deep channel region, a gate stack and a back gate that is surrounded by dielectric. The FET structure also includes halo or pocket implants that extend through the entire depth of the channel region. Because a portion of the halo and well doping of the channel is deeper than the source/drain depth, better threshold voltage and process control is achieved. A back-gated FET structure is also provided having a first dielectric layer in this structure that runs under the shallow source/drain region between the channel region and the back gate. This first dielectric layer extends from under the source/drain regions on either side of the back gate and is in contact with a second dielectric such that the back gate is bounded on each side or isolated by dielectric.
摘要翻译：本发明的实施例公开了具有浅电源/漏极区域，深沟道区域，栅极叠层和被电介质包围的背栅的FET的设计结构。 FET结构还包括延伸通过通道区域的整个深度的晕或凹坑植入物。因为沟道的一部分光晕和阱掺杂比源极/漏极深度更深，所以实现了更好的阈值电压和过程控制。还提供了后栅化FET结构，其具有在该结构中的第一介电层，其在沟道区域和后栅极之间的浅源极/漏极区域下方延伸。该第一电介质层从背栅的两侧的源极/漏极区下方延伸并与第二电介质接触，使得后栅极在每一侧上界定或通过电介质隔离。

9. 发明申请

US20060240610A1 Structure and method for dual-gate FET with SOI substrate 失效
标题翻译：具有SOI衬底的双栅极FET的结构和方法
公开(公告)号：US20060240610A1
公开(公告)日：2006-10-26
申请号：US11265464
申请日：2005-11-02
申请人： Edward Nowak , Richard Williams
发明人： Edward Nowak , Richard Williams
IPC分类号： H01L21/8234
CPC分类号： H01L29/785 , H01L29/41791 , H01L29/42384 , H01L29/66795 , H01L2029/7858
摘要： A method of forming a dual gate fin-type field effect transistor (FinFET) structure patterns silicon fins over an insulator and patterns a gate conductor at an angle to the fins. The gate conductor is formed laterally adjacent to and over center portions of the fins. The gate conductor is planarized such that the gate conductor is separated into distinct gate conductor portions that are separated by the fins. These gate conductor portions include front gates and back gates. The front gates and the back gates alternate along the structure, such that each fin has a front gate on one side and a back gate on the opposite side. Then front gate wiring is formed to the front gates and back gate wiring is formed to the back gates.
摘要翻译：形成双栅极鳍型场效应晶体管（FinFET）结构的方法在绝缘体上形成硅散热片，并以与鳍片成角度的方式形成栅极导体。栅极导体横向地形成在鳍片的中心部分附近并且越过其中心部分。栅极导体被平坦化，使得栅极导体分离成由鳍分开的不同的栅极导体部分。这些栅极导体部分包括前门和后门。前门和后门沿着结构交替，使得每个鳍具有一侧的前门和相对侧上的后门。然后，前栅极布线形成于前栅极，并且后栅极布线形成于后栅极。

10. 发明申请

US20070040236A1 DISCRETE ON-CHIP SOI RESISTORS 有权
标题翻译：分离片上SOI电阻
公开(公告)号：US20070040236A1
公开(公告)日：2007-02-22
申请号：US11161911
申请日：2005-08-22
申请人： Edward Nowak , Richard Williams
发明人： Edward Nowak , Richard Williams
IPC分类号： H01L29/00
CPC分类号： H01L29/8605 , H01L27/016 , H01L27/0802 , H01L29/66166
摘要： A semiconductor resistor, method of making the resistor and method of making an IC including resistors. Buried wells are formed in the silicon substrate of a silicon on insulator (SOI) wafer. At least one trench is formed in the buried wells. Resistors are formed along the sidewalls of the trench and, where multiple trenches form pillars, in the pillars between the trenches by doping the sidewalls with an angled implant. Resistor contacts are formed to the buried well at opposite ends of the trenches and pillars, if any.
摘要翻译：半导体电阻器，制造电阻器的方法和制造包括电阻器的IC的方法。掩埋阱形成在绝缘体上硅（SOI）晶片的硅衬底中。在埋井中形成至少一个沟槽。电阻器沿着沟槽的侧壁形成，并且在多个沟槽形成支柱的情况下，通过用成角度的植入物掺杂侧壁，在沟槽之间的支柱中形成电阻器。如果有的话，在沟槽和支柱的相对两端形成电阻触点到掩埋井。

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