专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090152983A1 Integrated acoustic bandgap devices for energy confinement and methods of fabricating same 有权
标题翻译：用于能量限制的集成声带隙装置及其制造方法
公开(公告)号：US20090152983A1
公开(公告)日：2009-06-18
申请号：US12002524
申请日：2007-12-17
申请人： Rajarishi Sinha , Peter Ledel Gammel , Marco Mastrapasqua , Hugo Safar
发明人： Rajarishi Sinha , Peter Ledel Gammel , Marco Mastrapasqua , Hugo Safar
IPC分类号： H03H9/15 , H03H3/02
CPC分类号： H01L27/02 , H03H9/0557 , H03H9/175 , H03H9/564 , H03H9/589
摘要： The present invention is directed to monolithic integrated circuits incorporating an oscillator element that is particularly suited for use in timing applications. The oscillator element includes a resonator element having a piezoelectric material disposed between a pair of electrodes. The oscillator element also includes an acoustic confinement structure that may be disposed on either side of the resonator element. The acoustic confinement element includes alternating sets of low and high acoustic impedance materials. A temperature compensation layer may be disposed between the piezoelectric material and at least one of the electrodes. The oscillator element is monolithically integrated with an integrated circuit element through an interconnection. The oscillator element and the integrated circuit element may be fabricated sequentially or concurrently.
摘要翻译：本发明涉及包含特别适用于定时应用的振荡器元件的单片集成电路。振荡器元件包括具有设置在一对电极之间的压电材料的谐振元件。振荡器元件还包括可以设置在谐振器元件的任一侧的声学限制结构。声学限制元件包括交替的低和高声阻抗材料组。温度补偿层可以设置在压电材料和至少一个电极之间。振荡器元件通过互连与集成电路元件单片集成。振荡器元件和集成电路元件可以顺序地或同时地制造。

2. 发明申请

US20120098611A1 INTEGRATED ACOUSTIC BANDGAP DEVICES FOR ENERGY CONFINEMENT AND METHODS OF FABRICATING SAME 有权
标题翻译：用于能量约束的集成声学带状装置及其制造方法
公开(公告)号：US20120098611A1
公开(公告)日：2012-04-26
申请号：US13339505
申请日：2011-12-29
申请人： Rajarishi Sinha , Peter Ledel Gammel , Marco Mastrapasqua , Hugo Safar
发明人： Rajarishi Sinha , Peter Ledel Gammel , Marco Mastrapasqua , Hugo Safar
IPC分类号： H03B5/32 , H03H9/17
CPC分类号： H01L27/02 , H03H9/0557 , H03H9/175 , H03H9/564 , H03H9/589
摘要： The present invention is directed to monolithic integrated circuits incorporating an oscillator element that is particularly suited for use in timing applications. The oscillator element includes a resonator element having a piezoelectric material disposed between a pair of electrodes. The oscillator element also includes an acoustic confinement structure that may be disposed on either side of the resonator element. The acoustic confinement element includes alternating sets of low and high acoustic impedance materials. A temperature compensation layer may be disposed between the piezoelectric material and at least one of the electrodes. The oscillator element is monolithically integrated with an integrated circuit element through an interconnection. The oscillator element and the integrated circuit element may be fabricated sequentially or concurrently.
摘要翻译：本发明涉及包含特别适用于定时应用的振荡器元件的单片集成电路。振荡器元件包括具有设置在一对电极之间的压电材料的谐振元件。振荡器元件还包括可以设置在谐振器元件的任一侧的声学限制结构。声学限制元件包括交替的低和高声阻抗材料组。温度补偿层可以设置在压电材料和至少一个电极之间。振荡器元件通过互连与集成电路元件单片集成。振荡器元件和集成电路元件可以顺序地或同时地制造。

3. 发明授权

US08564174B2 Integrated acoustic bandgap devices for energy confinement and methods of fabricating same 有权
公开(公告)号：US08564174B2
公开(公告)日：2013-10-22
申请号：US13339505
申请日：2011-12-29
申请人： Rajarishi Sinha , Peter Ledel Gammel , Marco Mastrapasqua , Hugo Safar
发明人： Rajarishi Sinha , Peter Ledel Gammel , Marco Mastrapasqua , Hugo Safar
IPC分类号： H03H9/17
CPC分类号： H01L27/02 , H03H9/0557 , H03H9/175 , H03H9/564 , H03H9/589
摘要： The present invention is directed to monolithic integrated circuits incorporating an oscillator element that is particularly suited for use in timing applications. The oscillator element includes a resonator element having a piezoelectric material disposed between a pair of electrodes. The oscillator element also includes an acoustic confinement structure that may be disposed on either side of the resonator element. The acoustic confinement element includes alternating sets of low and high acoustic impedance materials. A temperature compensation layer may be disposed between the piezoelectric material and at least one of the electrodes. The oscillator element is monolithically integrated with an integrated circuit element through an interconnection. The oscillator element and the integrated circuit element may be fabricated sequentially or concurrently.

4. 发明授权

US08089195B2 Integrated acoustic bandgap devices for energy confinement and methods of fabricating same 有权
标题翻译：用于能量限制的集成声带隙装置及其制造方法
公开(公告)号：US08089195B2
公开(公告)日：2012-01-03
申请号：US12002524
申请日：2007-12-17
申请人： Rajarishi Sinha , Peter Ledel Gammel , Marco Mastrapasqua , Hugo Safar
发明人： Rajarishi Sinha , Peter Ledel Gammel , Marco Mastrapasqua , Hugo Safar
IPC分类号： H03H9/17
CPC分类号： H01L27/02 , H03H9/0557 , H03H9/175 , H03H9/564 , H03H9/589
摘要： The present invention is directed to monolithic integrated circuits incorporating an oscillator element that is particularly suited for use in timing applications. The oscillator element includes a resonator element having a piezoelectric material disposed between a pair of electrodes. The oscillator element also includes an acoustic confinement structure that may be disposed on either side of the resonator element. The acoustic confinement element includes alternating sets of low and high acoustic impedance materials. A temperature compensation layer may be disposed between the piezoelectric material and at least one of the electrodes. The oscillator element is monolithically integrated with an integrated circuit element through an interconnection. The oscillator element and the integrated circuit element may be fabricated sequentially or concurrently.
摘要翻译：本发明涉及包含特别适用于定时应用的振荡器元件的单片集成电路。振荡器元件包括具有设置在一对电极之间的压电材料的谐振元件。振荡器元件还包括可以设置在谐振器元件的任一侧的声学限制结构。声学限制元件包括交替的低和高声阻抗材料组。温度补偿层可以设置在压电材料和至少一个电极之间。振荡器元件通过互连与集成电路元件单片集成。振荡器元件和集成电路元件可以顺序地或同时地制造。

5. 发明申请

US20050156234A1 Control of hot carrier injection in a metal-oxide semiconductor device 有权
标题翻译：在金属氧化物半导体器件中控制热载流子注入
公开(公告)号：US20050156234A1
公开(公告)日：2005-07-21
申请号：US10977732
申请日：2004-10-29
申请人： Peter Gammel , Isik Kizilyalli , Marco Mastrapasqua , Muhammed Shibib , Zhijian Xie , Shuming Xu
发明人： Peter Gammel , Isik Kizilyalli , Marco Mastrapasqua , Muhammed Shibib , Zhijian Xie , Shuming Xu
IPC分类号： H01L21/336 , H01L29/40 , H01L29/41 , H01L29/76 , H01L29/78 , H01L31/113
CPC分类号： H01L29/402 , H01L29/41 , H01L29/7835
摘要： An MOS device is formed including a semiconductor layer of a first conductivity type, and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A drift region is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. An insulating layer is formed on at least a portion of the upper surface of the semiconductor layer and above at least a portion of the drift region. A gate is formed on the insulating layer and at least partially between the first and second source/drain regions. The MOS device further includes a shielding structure formed on the insulating layer above at least a portion of the drift region. The shielding structure is configured such that an amount of hot carrier injection degradation in the MOS device is controlled as a function of an amount of coverage of the shielding structure over an upper surface of the drift region.
摘要翻译：形成MOS器件，其包括第一导电类型的半导体层，以及形成在靠近半导体层的上表面的半导体层中的第二导电类型的第一和第二源极/漏极区域，第一和第二源极/漏极区域相对于彼此间隔开。在靠近半导体层的上表面的半导体层中至少部分地在第一和第二源/漏区之间形成漂移区。绝缘层形成在半导体层的上表面的至少一部分上方和漂移区的至少一部分上方。栅极形成在绝缘层上并且至少部分地在第一和第二源/漏区之间。 MOS器件还包括形成在漂移区的至少一部分上方的绝缘层上的屏蔽结构。屏蔽结构被配置为使得MOS器件中的热载流子注入劣化量被控制为在漂移区域的上表面上的屏蔽结构的覆盖量的函数。

6. 发明申请

US20080003703A1 CONTROL OF HOT CARRIER INJECTION IN A METAL-OXIDE SEMICONDUCTOR DEVICE 有权
标题翻译：金属氧化物半导体器件中热载体注入的控制
公开(公告)号：US20080003703A1
公开(公告)日：2008-01-03
申请号：US11853417
申请日：2007-09-11
申请人： Peter Gammel , Isik Kizilyalli , Marco Mastrapasqua , Muhammed Shibib , Zhijian Xie , Shuming Xu
发明人： Peter Gammel , Isik Kizilyalli , Marco Mastrapasqua , Muhammed Shibib , Zhijian Xie , Shuming Xu
IPC分类号： H01L21/66
CPC分类号： H01L29/402 , H01L29/41 , H01L29/7835
摘要： In a metal-oxide semiconductor device including first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, a drift region formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions, an insulating layer formed on at least a portion of the upper surface of the semiconductor layer, and a gate formed on the insulating layer and at least partially between the first and second source/drain regions, a method for controlling an amount of hot carrier injection degradation in the device includes the steps of: forming a shielding structure on the insulating layer above at least a portion of the drift region and substantially between the gate and the second source/drain region; and adjusting an amount of coverage of the shielding structure over an upper surface of the drift region so as to minimize the amount of hot-carrier injection degradation while maintaining a breakdown voltage in the device which is greater than or equal to a prescribed value.
摘要翻译：在包括形成在靠近半导体层的上表面的第二导电类型的半导体层中的第一导电类型的第一和第二源极/漏极区域的金属氧化物半导体器件中，形成在靠近上部的半导体层中的漂移区域半导体层的表面，并且至少部分地在第一和第二源极/漏极区之间，形成在半导体层的上表面的至少一部分上的绝缘层和形成在绝缘层上的栅极，并且至少部分地在第一和/ 第一和第二源极/漏极区域，用于控制器件中热载流子注入劣化量的方法包括以下步骤：在绝缘层上形成屏蔽结构，该屏蔽结构位于漂移区域的至少一部分上方并且基本上在栅极和第二源极/漏极区域; 以及调整所述屏蔽结构在所述漂移区域的上表面上的覆盖范围，以便在保持所述器件中的击穿电压大于或等于规定值的同时使热载流子注入劣化的量最小化。

7. 发明授权

US6011722A Method for erasing and programming memory devices 有权
标题翻译：擦除和编程存储器件的方法
公开(公告)号：US6011722A
公开(公告)日：2000-01-04
申请号：US170819
申请日：1998-10-13
申请人： Jeffrey Devin Bude , Marco Mastrapasqua
发明人： Jeffrey Devin Bude , Marco Mastrapasqua
IPC分类号： G11C16/04 , G11C16/00 , G11C16/34
CPC分类号： G11C16/3445 , G11C16/3436 , G11C16/3459
摘要： A method for programming and/or erasing an array of stacked gate memory devices such as EPROM and EEPROM devices in a NOR array is disclosed. In the method, either a program verify or an erase verify is performed intermittently with the programming of a device or the erasure of the array. During the program-verify, one of either a negative V.sub.CS is applied to the deselected devices in the array, a negative V.sub.BS is applied to both the selected and deselected devices in the array, or both conditions are applied. Performing the program verify or erase verify in this manner is efficient and accurate. During the programming step, it is also advantageous if one of either a negative V.sub.CS is applied to the deselected devices in the array, a negative V.sub.BS is applied to the selected devices in the array, or both. With the application of a negative V.sub.CS to the deselected devices during programming, if there are any over-erased devices in the array, the presence of the over-erased devices will not adversely affect the programming of the devices.
摘要翻译：公开了一种用于在NOR阵列中编程和/或擦除诸如EPROM和EEPROM装置的堆叠栅极存储器件阵列的方法。在该方法中，通过对设备的编程或阵列的擦除来间歇地执行程序验证或擦除验证。在程序验证期间，负VCS中的一个应用于阵列中未被选择的器件，负VBS被应用于阵列中的选定和取消选择的器件，或者两个条件都被应用。以这种方式执行程序验证或擦除验证是高效和准确的。在编程步骤期间，如果将负VCS中的一个应用于阵列中的取消选择的器件，则将负VBS应用于阵列中的所选器件，或两者都是有利的。通过在编程期间向取消选择的器件应用负VCS，如果阵列中存在任何过度擦除的器件，则过擦除器件的存在将不会对器件的编程产生不利影响。

8. 发明授权

US06509242B2 Heterojunction bipolar transistor 有权
公开(公告)号：US06509242B2
公开(公告)日：2003-01-21
申请号：US09759120
申请日：2001-01-12
申请人： Michel Ranjit Frei , Clifford Alan King , Yi Ma , Marco Mastrapasqua , Kwok K Ng
发明人： Michel Ranjit Frei , Clifford Alan King , Yi Ma , Marco Mastrapasqua , Kwok K Ng
IPC分类号： H01L21331
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A heterojunction bipolar transistor includes an emitter or collector region of doped silicon, a base region including silicon-germanium, and a spacer. The emitter or collector region form a heterojunction with the base region. The spacer is positioned to electrically insulate the emitter or collector region from an external region. The spacer includes a silicon dioxide layer physically interposed between the emitter or collector region and the remainder of the spacer.

9. 发明授权

US06303940B1 Charge injection transistor using high-k dielectric barrier layer 有权
标题翻译：使用高k电介质阻挡层的电荷注入晶体管
公开(公告)号：US06303940B1
公开(公告)日：2001-10-16
申请号：US09339894
申请日：1999-06-25
申请人： Isik C. Kizilyalli , Marco Mastrapasqua
发明人： Isik C. Kizilyalli , Marco Mastrapasqua
IPC分类号： H01L2906
CPC分类号： C23C14/083 , C23C14/5806 , C23C14/5873 , H01L21/28211 , H01L21/31612 , H01L21/31629 , H01L28/60 , H01L29/513 , H01L29/517 , H01L29/7606
摘要： The present invention relates to a heterojunction structure based upon the oxide/high-k dielectric barrier. In exemplary embodiment, a silicon layer has a silicon dioxide layer thereon, and a high-k dielectric material disposed on the oxide layer. Thereafter, a metal layer, serving as the gate metal for the device is disposed on the high-k dielectric. The silicon dioxide layer has a relatively high barrier height, but has a relatively small thickness, and relative to the high-k dielectric, the barrier height differential fosters real space transfer. In this structure, the high barrier height of the silicon dioxide layer results in higher mobility and thereby greater substrate current. By virtue of the relative thick layer of high-k dielectric, leakage current is significantly reduced. Thus, the high-k dielectric material/oxide interface gives the needed barrier thickness to prevent leakage, but enables tunneling of hot electrons through the silicon dioxide into the metal layer with a sufficient applied voltage.
摘要翻译：本发明涉及基于氧化物/高k电介质屏障的异质结结构。在示例性实施例中，硅层在其上具有二氧化硅层，以及设置在氧化物层上的高k电介质材料。此后，在高k电介质上设置用作器件的栅极金属的金属层。二氧化硅层具有较高的势垒高度，但具有相对较小的厚度，并且相对于高k电介质，势垒高度差异促进了实际的空间传递。在该结构中，二氧化硅层的高势垒高度导致较高的迁移率，从而导致更大的衬底电流。由于高k电介质的相对厚层，漏电流明显降低。因此，高k介电材料/氧化物界面提供所需的阻挡层厚度以防止泄漏，但是能够以足够的施加电压将热电子穿过二氧化硅进入金属层。

10. 发明授权

US6144073A Monolithically-integrated static random access memory device 有权
标题翻译：单片集成静态随机存取存储器件
公开(公告)号：US6144073A
公开(公告)日：2000-11-07
申请号：US311822
申请日：1999-05-13
申请人： Gerhard Hobler , Marco Mastrapasqua , Mark Richard Pinto , Enrico Sangiori
发明人： Gerhard Hobler , Marco Mastrapasqua , Mark Richard Pinto , Enrico Sangiori
IPC分类号： H01L27/11 , H01L27/01 , H01L27/12 , H01L29/76 , H01L29/94 , H01L31/0392
CPC分类号： H01L27/1104
摘要： A monolithically-integrated SRAM cell is described for reducing the cell size, i.e., at least two of a plurality of transistors comprising the SRAM cell are monolithically integrated to define a first transistor and a second transistor, wherein the drain of the first transistor functions as the gate of the second transistor and the drain of the second transistor functions as the gate of the first transistor. This integration eliminates the need for gate-to-drain connections of previous devices.
摘要翻译：描述了用于减小单元尺寸的单片集成SRAM单元，即，包括SRAM单元的多个晶体管中的至少两个单体集成以限定第一晶体管和第二晶体管，其中第一晶体管的漏极用作第二晶体管的栅极和第二晶体管的漏极用作第一晶体管的栅极。该集成消除了以前器件的栅极到漏极连接的需要。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式