专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4301381A TTL-Compatible address latch with field effect transistors 失效
标题翻译： TTL兼容地址锁存与场效应晶体管
公开(公告)号：US4301381A
公开(公告)日：1981-11-17
申请号：US66595
申请日：1979-08-14
申请人： Rainer Clemen , Joerg Gschwendtner , Werner Haug
发明人： Rainer Clemen , Joerg Gschwendtner , Werner Haug
IPC分类号： G11C11/41 , G11C11/408 , G11C11/413 , H03K3/356 , H03K5/02 , H03K5/15 , H03K19/0185 , H03K5/00
CPC分类号： H03K3/356017 , G11C11/4082 , H03K19/01855 , H03K3/356086
摘要： Disclosed is a field effect transistor (FET) circuit for accepting a bipolar transistor logic level input signal and providing FET logic level output signals (both in-phase and out-of-phase components). The FET circuit includes a gated latch with means for pre-charging first and second nodes to an FET logic up level. One of the two nodes is brought to a slightly higher or lower level (depending on the binary value of the input), thereby producing a latent imbalance in the latch. A gating signal causes the latch to switch into the state pre-set by the latent imbalance.
摘要翻译：公开了一种用于接受双极晶体管逻辑电平输入信号并提供FET逻辑电平输出信号（同相和异相分量）的场效应晶体管（FET）电路。 FET电路包括门控锁存器，其具有用于将第一和第二节点预充电到FET逻辑上电平的装置。两个节点中的一个被带到稍高或更低的电平（取决于输入的二进制值），从而在锁存器中产生潜在的不平衡。门控信号使锁存器转变为由潜在不平衡预先设定的状态。

2. 发明授权

US4238841A Dynamic semiconductor memory read/write access circuit 失效
标题翻译：动态半导体存储器读/写存取电路
公开(公告)号：US4238841A
公开(公告)日：1980-12-09
申请号：US103796
申请日：1979-12-14
申请人： Rainer Clemen , Joerg Gschwendtner , Werner Haug
发明人： Rainer Clemen , Joerg Gschwendtner , Werner Haug
IPC分类号： G11C11/409 , G11C11/403 , G11C11/404 , G11C11/4096 , G11C11/40
CPC分类号： G11C11/4096 , G11C11/403 , G11C11/404
摘要： To the known sense latch already existing in a bit line pair in an FET memory, and to the two bit switches in each bit line another latch is arranged in series which furthermore is coupled to the common data input and output via a write driver on the one side and a read driver on the other. Both latches are of an identical structure and controlled by the same pulses in the read as well as in the write phase. The data path via the write driver and the read driver up to, or from, the additional latch is respectively designed as unidirectional double rail line, and selectively connectable via the bit switches with the bidirectional double rail line to the respective bit line pair.
摘要翻译：对于已经存在于FET存储器中的位线对中的已知检测锁存器，并且对于每个位线中的两位开关，另一个锁存器被串联布置，此外还通过写入驱动器将数据输入和输出耦合到公共数据另一边是一个读驱动器。两个锁存器具有相同的结构，并由读取和写入阶段中的相同脉冲控制。通过写入驱动器和读取驱动器的数据路径分别被设计为单向双轨线路，并且可以经由位开关与双向双轨线路选择性地连接到相应的位线对。

3. 发明授权

US4494018A Bootstrapped level shift interface circuit with fast rise and fall times 失效
标题翻译：引导电平移位接口电路具有快速上升和下降时间
公开(公告)号：US4494018A
公开(公告)日：1985-01-15
申请号：US374113
申请日：1982-05-03
申请人： Rainer Clemen , Werner Haug
发明人： Rainer Clemen , Werner Haug
IPC分类号： G11C8/06 , G11C11/407 , G11C11/4076 , G11C11/417 , H03K19/017 , H03K19/094 , H03K5/02 , H03K19/20
CPC分类号： H03K19/094 , G11C11/4076 , G11C11/417 , G11C8/06 , H03K19/01714
摘要： An input circuit for a field effect transistor (FET) storage is described which consists of a bootstrap inverter which by a dynamically operating charge-up circuit is supplemented for charging up the bootstrap node to the full operating voltage, and which can be directly controlled with TTL levels without a level converter consisting of bipolar transistors being inserted. For that purpose, the input electrode of the bootstrap capacitor of the dynamically operating charge-up circuit is connected to the output of an inverter following the input circuit. Furthermore a discharge branch is provided for the node of the dynamically operating charge-up circuit. With its other end, together with the gate of the charge-up field effect transistor of the dynamic charge-up circuit, the discharge branch is connected to the output of another inverter following the first one. It is thus assured that when owing to the bootstrap effect the potential of the bootstrap node rises over the value VH of the operating voltage, this node cannot be discharged via the FET's in the charge-up circuit to the positive pole of the operating voltage source. This would counteract the rise of the potential of the bootstrap node so that the potential and the output of the input circuit would rise only slowly, and would not reach the full value VH of the operating voltage.
摘要翻译：描述了用于场效应晶体管（FET）存储器的输入电路，其由自举逆变器组成，其通过动态操作的充电电路被补充，用于将引导节点充电到完全工作电压，并且可以直接由没有插入双极晶体管的电平转换器的TTL电平。为此，动态操作的充电电路的自举电容器的输入电极连接到输入电路之后的反相器的输出端。此外，为动态操作的充电电路的节点提供放电支路。另一方面，与动态充电电路的充电场效应晶体管的栅极一起，放电支路与第一个反相器的输出端连接。因此确保了当自举效应时，自举节点的电位上升超过工作电压的值VH，该节点不能通过充电电路中的FET放电到工作电压源的正极。这将抵消引导节点的电位的上升，使得输入电路的电位和输出仅缓慢上升，并且不能达到工作电压的全值VH。

4. 发明授权

US4122361A Delay circuit with field effect transistors 失效
标题翻译：具有场效应晶体管的延迟电路
公开(公告)号：US4122361A
公开(公告)日：1978-10-24
申请号：US740456
申请日：1976-11-10
申请人： Rainer Clemen , Werner Haug , Robert Schnadt
发明人： Rainer Clemen , Werner Haug , Robert Schnadt
IPC分类号： G11C5/00 , G11C27/02 , H03H7/30 , H03H11/26 , H03K5/00 , H03K5/13 , H03K5/133 , H03K5/153 , H03K17/28 , H03K17/60 , H03K5/159
CPC分类号： G11C5/00 , G11C27/026 , H03H11/26 , H03H7/30 , H03K5/133 , H03K5/153 , H03K2005/00195
摘要： Utilization of a chip internal clock driver, for capacitive loads such as MOS circuits, which provides in response to an external clock phase adjustable and delayed secondary clock pulses. The delay circuit is an inverter circuit which uses a precharged coupling capacitor whose potential is dynamically increased (boosted) by capacitive coupling the input pulse to approximately twice the supply voltage and which capacitor is subsequently discharged by a constant current thus defining a delay time in a more extended and more precise range.
摘要翻译：利用芯片内部时钟驱动器，用于诸如MOS电路的电容性负载，其响应于外部时钟相位可调节和延迟的次级时钟脉冲而提供。延迟电路是使用预充电耦合电容器的逆变器电路，其电位通过将输入脉冲电容耦合到电源电压的大约两倍而被动态地增加（升压），并且随后通过恒定电流放电电容，从而在更广泛和更精确的范围。

5. 发明授权

US5796284A High-precision voltage dependent timing delay circuit 失效
标题翻译：高精度电压相关定时延时电路
公开(公告)号：US5796284A
公开(公告)日：1998-08-18
申请号：US765416
申请日：1996-12-16
申请人： Rainer Clemen , Wolfdieter Loehlein , Harald Mielich
发明人： Rainer Clemen , Wolfdieter Loehlein , Harald Mielich
IPC分类号： G11C7/06 , G11C7/22 , H03K5/13 , H03K5/133 , H03K19/003 , H03H11/26
CPC分类号： H03K5/133 , G11C7/06 , G11C7/067 , G11C7/22 , H03K19/00323
摘要： For high-speed single-ended sensing of the small signal delivered from a (static) RAM or ROM cell, a voltage dependent timing delay circuit is disclosed which prevents early triggering of the set signal of the sense amplifier (SSA 66) when applying a high voltage screen test (i.e. 1.5 times V.sub.DD) to the cell. The timing of the SSA signal is achieved by a high precision delay chain comprising inverters, which is loaded by a voltage dependent current sink (70) coupled to the output of the chain. The inverter delay chain controls the input (SE0) for a driver for the SSA line (66). The current sink may be a pull down NFET (70) which is only activated when the supply voltage is above a determined switching threshold therefor. The gate voltage of the NFET is controlled by a bias control circuit (72) in such a manner that during operation at typical voltage levels, the NFET is deactivated, whereas at higher operating voltage levels (such as 1.5 * V.sub.DD) the NFET is turned on, thereby sinking current from the input (SE0) to the driver for the SSA line. The SSA signal is consequently delayed preventing the early triggering thereof.
摘要翻译： PCT No.PCT / EP95 / 03041 Sec。 371日期1996年12月16日第 102（e）日期1996年12月16日PCT提交1995年7月31日PCT公布。公开号WO97 / 05700 日期1997年2月13日对于从（静态）RAM或ROM单元传送的小信号的高速单端感测，公开了一种电压相关的定时延迟电路，其防止早期触发读出放大器（SSA）的设置信号 66）当对电池进行高电压屏蔽测试（即1.5倍VDD）时。 SSA信号的定时由包括反相器的高精度延迟链来实现，该反相器由耦合到链路的输出的与电压相关的电流吸收器（70）加载。变频器延时链控制用于SSA线路（66）的驱动器的输入（SE0）。电流吸收器可以是下拉NFET（70），其仅当电源电压高于确定的转换阈值时被激活。 NFET的栅极电压由偏置控制电路（72）控制，使得在典型电压电平下工作时，NFET被去激活，而在较高的工作电压电平（例如1.5 * VDD）下，NFET被转换从而从输入端（SE0）向SSA线路的驱动器吸收电流。 SSA信号因此被延迟，从而阻止其早期触发。

6. 发明授权

US4276487A FET driver circuit with short switching times 失效
标题翻译： FET驱动电路，开关时间短
公开(公告)号：US4276487A
公开(公告)日：1981-06-30
申请号：US27128
申请日：1979-04-04
申请人： Luis M. Arzubi , Rainer Clemen , Jorg Gschwendtner
发明人： Luis M. Arzubi , Rainer Clemen , Jorg Gschwendtner
IPC分类号： H03K19/096 , H03K17/06 , H03K19/0185 , H03K19/094 , H03K17/04 , H03K17/284 , H03K17/687 , H03K19/017
CPC分类号： H03K19/018557
摘要： A field effect transistor driver circuit responsive to a single input pusle generates a highly loadable output clock pulse with short rise and fall times, the rising edge being shifted relative to said input pulse by a controllable delay time but the trailing edge remaining practically undelayed. This advantageous pulse form is achieved through an improved controlling of a bootstrap output stage. Two preceding stages, i.e., a transmission gate and a delay stage supply two out-of-phase control pulses with high amplitudes and steep edges. Of essential importance is the novel delay stage which is designed as push-pull stage with a load FET and a driver FET. The gate of the load FET is controlled by the output pulse of the bootstrap stage 2 fed back via a third FET and by a capacitively coupled-in input pulse at the drain, whereas the gate of driver FET is controlled from the bootstrapped output of the transmission gate. The connecting point of load and driver FET represents the output of the delay stage. For the quick switching-on and delayed but speedy switching-off of the driver FET's of the bootstrap output stage a pulse equal in amplitude to the input pulse is generated. That pulse rising with equal speed and falling steeply after delay. The delay stage also controls advantageously the gate recharging of the isolation FET of transmission gate.
摘要翻译：响应于单个输入引脚的场效应晶体管驱动器电路产生具有短的上升和下降时间的高度可加载的输出时钟脉冲，所述上升沿相对于所述输入脉冲移动可控延迟时间，但是后沿几乎保持不变。这种有利的脉冲形式通过改进的自举输出级的控制来实现。两个前级，即传输门和延迟级提供具有高幅度和陡峭边缘的两个异相控制脉冲。最重要的是新颖的延迟级，其设计为具有负载FET和驱动器FET的推挽级。负载FET的栅极由通过第三FET反馈的自举阶段2的输出脉冲和漏极处的电容耦合输入脉冲控制，而驱动器FET的栅极由传输门负载和驱动器FET的连接点表示延迟级的输出。为了快速接通和延迟但快速关闭自举输出级的驱动器FET，产生幅度等于输入脉冲的脉冲。该脉冲以相同的速度上升，延迟后急剧下降。延迟级还有利地控制了传输门的隔离FET的栅极再充电。

7. 发明授权

US4406956A FET Circuit for converting TTL to FET logic levels 失效
标题翻译： FET电路，用于将TTL转换为FET逻辑电平
公开(公告)号：US4406956A
公开(公告)日：1983-09-27
申请号：US177298
申请日：1980-08-11
申请人： Rainer Clemen , Walter Fischer , Werner O. Haug
发明人： Rainer Clemen , Walter Fischer , Werner O. Haug
IPC分类号： H03K5/02 , H03K19/0185 , H03K19/092 , H03K19/094
CPC分类号： H03K19/018507
摘要： This invention relates to a field effect transistor level converter for converting bipolar transistor logic levels to field effect transistor logic levels. First and second field effect transistors have their source and gate electrodes connected in common. The bipolar input signal is received at the common source connection while the gate electrodes receive a fixed reference potential that is equal to the threshold voltage VT plus the lowest possible high binary level of the bipolar input logic. The drain electrode of the first field effect transistor is connected to the output terminal of the level converter and the source electrode of a source follower transistor. The drain electrode of the second transistor is connected to a load device and to the gate of the source follower transistor which has its drain electrode connected to VH. This arrangement produces at the first output terminal a potential swing of approximately 0 to 7 volts in response to an input signal in the range of 0.8 to 2.0 volts.
摘要翻译：本发明涉及用于将双极晶体管逻辑电平转换为场效应晶体管逻辑电平的场效应晶体管电平转换器。第一和第二场效应晶体管的源极和栅极共同连接。双极性输入信号在公共源极连接处被接收，而栅电极接收等于阈值电压VT加上双极性输入逻辑的最低可能的高二进制电平的固定参考电位。第一场效应晶体管的漏电极连接到电平转换器的输出端和源极跟随器晶体管的源电极。第二晶体管的漏电极连接到负载器件和源极跟随器晶体管的栅极，其漏极连接到VH。这种布置在第一输出端产生响应于0.8至2.0伏范围内的输入信号的大约0至7伏特的电位摆动。

8. 发明授权

US5949723A Fast single ended sensing with configurable half-latch 失效
标题翻译：具有可配置半锁存器的快速单端感测
公开(公告)号：US5949723A
公开(公告)日：1999-09-07
申请号：US126241
申请日：1998-07-30
申请人： Rainer Clemen , Herald Mielich , Jurgen Pille
发明人： Rainer Clemen , Herald Mielich , Jurgen Pille
IPC分类号： G11C7/06 , G11C11/419 , G11C29/12 , G11C7/00
CPC分类号： G11C7/065 , G11C11/419 , G11C7/067
摘要： For high-speed single-ended sensing of the signal from a (multi-port) SRAM cell, a configurable half-latch with 2 PFET feedback pathes is proposed, which can be set up either as a bleeder device in the system mode or as keeper devices in the test modes, controlled by a DC signal (TEST). The bleeder and keepers are attached to the bit line and gated by a small ratioed inverter serving as sense amplifier. In case of system mode, a low control signal is applied to the source of the bleeder to limit the bit line up-level to a threshold below the supply voltage Vdd. Thus, discharging the bit line when reading a `0` is fast. Reading a `1` is also fast by skewing the inverter to a PFET/NFET ratio below 1. For chip testing, the control signal is set high to enable the keepers which restore the bit line close to the supply voltage, even when large subthreshold currents try to discharge it via the unselected cells. This turns off the PFET of the inverter, thereby minimizing the DC current. The new approach improves the access time by about 10%, since no speed must be sacrificed for low-power operation during reliability tests at high voltage (1.5.times. to 2.times. Vdd) and temperature.
摘要翻译：对于来自（多端口）SRAM单元的信号的高速单端感测，提出了具有2个PFET反馈纹理的可配置半锁存器，其可以被设置为系统模式中的泄放装置或者作为在测试模式下，由直流信号（TEST）控制。放电器和保持器连接到位线并由用作读出放大器的小比例变换器门控。在系统模式的情况下，将低控制信号施加到放电器的源极以将位线上限限制到低于电源电压Vdd的阈值。因此，读取“0”时放电位线很快。通过将反相器偏置为低于1的PFET / NFET比例，读取“1”也很快。对于芯片测试，控制信号设置为高电平，以使能够将位线恢复到电源电压附近的保持器，即使在大的亚阈值电流试图通过未选择的电池放电。这将关闭逆变器的PFET，从而最小化直流电流。新的方法将访问时间提高了约10％，因为在高电压（1.5x至2x Vdd）和温度的可靠性测试期间，低功耗操作不能牺牲速度。

9. 发明授权

US5473574A Multi-port static random access memory with fast write-thru scheme 失效
标题翻译：具有快速写入方案的多端口静态随机存取存储器
公开(公告)号：US5473574A
公开(公告)日：1995-12-05
申请号：US14031
申请日：1993-02-05
申请人： Rainer Clemen , Klaus Getzlaff
发明人： Rainer Clemen , Klaus Getzlaff
IPC分类号： G11C11/41 , G11C8/16 , G11C8/00
CPC分类号： G11C8/16
摘要： A fast write-thru scheme is proposed for use in a multi-port static random access memory. This is achieved by operating the read and write ports of the SRAM circuitry in two separate but interleaved stages. In a first stage, a write path is set up comprising a write address decoder, an AND gate connected to a clock signal, the AND gate enabling a write port coupled to the latch of a memory cell. In the second stage, a read path is set up comprising a read address decoder selecting a read port, through which data is read from the cell latch to a data out buffer. To minimize the write-thru access time, the synchronous read path controlled by the read address is interleaved with the write path triggered by a write clock (CE), so that the read address is delayed with respect to the clock and the write addresses. Thus the write-thru access time becomes independent from the write time needed for overwriting the multi-port SRAM cell and equal to the read address access time achieved in a fully static or synchronous read operation.
摘要翻译：提出了一种用于多端口静态随机存取存储器的快速写入方案。这是通过将SRAM电路的读和写端口操作在两个单独但交错的级中来实现的。在第一阶段，设置写入路径，其包括写入地址解码器，连接到时钟信号的与门，该与门使能耦合到存储器单元的锁存器的写入端口。在第二阶段中，设置读取路径，该读取路径包括选择读取端口的读取地址解码器，通过该读取端口将数据从单元锁存器读取到数据输出缓冲器。为了最小化写入访问时间，由读取地址控制的同步读取路径与由写入时钟（CE）触发的写入路径交错，使得读取地址相对于时钟和写入地址被延迟。因此，写入访问时间与覆盖多端口SRAM单元所需的写入时间无关，并且等于在完全静态或同步读取操作中实现的读取地址访问时间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式