专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4301381A TTL-Compatible address latch with field effect transistors 失效
标题翻译： TTL兼容地址锁存与场效应晶体管
公开(公告)号：US4301381A
公开(公告)日：1981-11-17
申请号：US66595
申请日：1979-08-14
申请人： Rainer Clemen , Joerg Gschwendtner , Werner Haug
发明人： Rainer Clemen , Joerg Gschwendtner , Werner Haug
IPC分类号： G11C11/41 , G11C11/408 , G11C11/413 , H03K3/356 , H03K5/02 , H03K5/15 , H03K19/0185 , H03K5/00
CPC分类号： H03K3/356017 , G11C11/4082 , H03K19/01855 , H03K3/356086
摘要： Disclosed is a field effect transistor (FET) circuit for accepting a bipolar transistor logic level input signal and providing FET logic level output signals (both in-phase and out-of-phase components). The FET circuit includes a gated latch with means for pre-charging first and second nodes to an FET logic up level. One of the two nodes is brought to a slightly higher or lower level (depending on the binary value of the input), thereby producing a latent imbalance in the latch. A gating signal causes the latch to switch into the state pre-set by the latent imbalance.
摘要翻译：公开了一种用于接受双极晶体管逻辑电平输入信号并提供FET逻辑电平输出信号（同相和异相分量）的场效应晶体管（FET）电路。 FET电路包括门控锁存器，其具有用于将第一和第二节点预充电到FET逻辑上电平的装置。两个节点中的一个被带到稍高或更低的电平（取决于输入的二进制值），从而在锁存器中产生潜在的不平衡。门控信号使锁存器转变为由潜在不平衡预先设定的状态。

2. 发明授权

US4238841A Dynamic semiconductor memory read/write access circuit 失效
标题翻译：动态半导体存储器读/写存取电路
公开(公告)号：US4238841A
公开(公告)日：1980-12-09
申请号：US103796
申请日：1979-12-14
申请人： Rainer Clemen , Joerg Gschwendtner , Werner Haug
发明人： Rainer Clemen , Joerg Gschwendtner , Werner Haug
IPC分类号： G11C11/409 , G11C11/403 , G11C11/404 , G11C11/4096 , G11C11/40
CPC分类号： G11C11/4096 , G11C11/403 , G11C11/404
摘要： To the known sense latch already existing in a bit line pair in an FET memory, and to the two bit switches in each bit line another latch is arranged in series which furthermore is coupled to the common data input and output via a write driver on the one side and a read driver on the other. Both latches are of an identical structure and controlled by the same pulses in the read as well as in the write phase. The data path via the write driver and the read driver up to, or from, the additional latch is respectively designed as unidirectional double rail line, and selectively connectable via the bit switches with the bidirectional double rail line to the respective bit line pair.
摘要翻译：对于已经存在于FET存储器中的位线对中的已知检测锁存器，并且对于每个位线中的两位开关，另一个锁存器被串联布置，此外还通过写入驱动器将数据输入和输出耦合到公共数据另一边是一个读驱动器。两个锁存器具有相同的结构，并由读取和写入阶段中的相同脉冲控制。通过写入驱动器和读取驱动器的数据路径分别被设计为单向双轨线路，并且可以经由位开关与双向双轨线路选择性地连接到相应的位线对。

3. 发明授权

US4267465A Circuit for recharging the output nodes of field effect transistor circuits 失效
标题翻译：对场效应晶体管电路的输出节点进行充电的电路
公开(公告)号：US4267465A
公开(公告)日：1981-05-12
申请号：US003164
申请日：1979-01-15
申请人： Werner Haug , Joerg Gschwendtner , Robert Schnadt
发明人： Werner Haug , Joerg Gschwendtner , Robert Schnadt
IPC分类号： G11C11/417 , G11C11/412 , H03K3/356 , H03K5/00 , H03K3/26
CPC分类号： G11C11/412
摘要： A recharging circuit is provided to maintain a high potential for a longer time interval at the output node of a FET driver circuit. The recharging circuit consists of a first FET which is made periodically conductive via a capacitor and periodically recharges a capacitance at the output node. This capacitance is first charged by a strong pulse of the driver circuit. A second FET is provided to prevent a current flow through the first FET and thus the generation of a power dissipating current when the output potential of the driver circuit is low. The gate of the second FET is connected to a supply voltage. Thus, the second FET is conductive when a low potential exists at the output node, transferring that potential to the gate of the first FET which, in turn, does not become conductive since its gate to source voltage is less than its threshold voltage.
摘要翻译：提供充电电路以在FET驱动器电路的输出节点处保持较长时间间隔的高电位。再充电电路由第一FET构成，第一FET通过电容器周期性地导通，并在输出节点周期性地对电容进行充电。该电容首先由驱动电路的强脉冲充电。提供第二FET以防止电流流过第一FET，从而当驱动器电路的输出电位低时产生功率耗散电流。第二FET的栅极连接到电源电压。因此，当在输出节点处存在低电位时，第二FET导通，将该电位转移到第一FET的栅极，而栅极至栅极至源极电压小于其阈值电压，栅极仍然不会导通。

4. 发明授权

US4112512A Semiconductor memory read/write access circuit and method 失效
标题翻译：半导体存储器读/写存取电路及方法
公开(公告)号：US4112512A
公开(公告)日：1978-09-05
申请号：US863566
申请日：1977-12-22
申请人： Luis Maria Arzubi , Joerg Gschwendtner , Robert Schnadt
发明人： Luis Maria Arzubi , Joerg Gschwendtner , Robert Schnadt
IPC分类号： G11C11/409 , G11C11/404 , G11C11/4091 , G11C11/4096 , G11C11/4097 , G11C11/40
CPC分类号： G11C11/4091 , G11C11/404 , G11C11/4096 , G11C11/4097
摘要： A high performance semiconductor memory read/write data access circuit including a sense amplifier directly coupled to a pair of bit lines is provided with a pair of bit switching devices to enable data communication external to the memory. Control potentials and timing of switching signals are provided in such a manner that only one of the bit switches becomes conductive during reading and writing access to the memory.
摘要翻译：包括直接耦合到一对位线的读出放大器的高性能半导体存储器读/写数据存取电路设置有一对位切换装置，以使得能够在存储器外部进行数据通信。以这样的方式提供开关信号的控制电位和时序，使得只有一个位开关在对存储器的读取和写入访问期间变得导通。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式