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1. 发明授权

US07366891B2 Methods and apparatus to provide dual-mode drivers in processor systems 有权
标题翻译：在处理器系统中提供双模驱动的方法和装置
公开(公告)号：US07366891B2
公开(公告)日：2008-04-29
申请号：US11027520
申请日：2004-12-30
申请人： Rahul Khanna , Mallik Bulusu , Vincent Zimmer , Michael A. Rothman
发明人： Rahul Khanna , Mallik Bulusu , Vincent Zimmer , Michael A. Rothman
IPC分类号： G06F15/177
CPC分类号： G06F9/4403
摘要： Methods and apparatus to provide dual-mode drivers in a processor system are disclosed. An example method disclosed herein comprises including operating system (OS) agnostic mode services that are available during an OS agnostic mode to allow a single set of drivers to be used during boot mode and the OS agnostic mode. The example method further comprises including a dual-mode library that is capable of determining the current operating mode of the processor system and binding the drivers to available services accordingly.
摘要翻译：公开了在处理器系统中提供双模驱动器的方法和装置。本文公开的示例性方法包括在OS不可知模式期间可用的操作系统（OS）不可知模式服务，以允许在引导模式和OS不可知模式期间使用单组驱动器。该示例方法还包括包括能够确定处理器系统的当前操作模式并且相应地将驱动程序绑定到可用服务的双模式库。

2. 发明申请

US20060168590A1 Methods and apparatus to provide dual-mode drivers in processor systems 有权
标题翻译：在处理器系统中提供双模驱动的方法和装置
公开(公告)号：US20060168590A1
公开(公告)日：2006-07-27
申请号：US11027520
申请日：2004-12-30
申请人： Rahul Khanna , Mallik Bulusu , Vincent Zimmer , Michael Rothman
发明人： Rahul Khanna , Mallik Bulusu , Vincent Zimmer , Michael Rothman
IPC分类号： G06F9/46
CPC分类号： G06F9/4403
摘要： Methods and apparatus to provide dual-mode drivers in a processor system are disclosed. An example method disclosed herein comprises including operating system (OS) agnostic mode services that are available during an OS agnostic mode to allow a single set of drivers to be used during boot mode and the OS agnostic mode. The example method further comprises including a dual-mode library that is capable of determining the current operating mode of the processor system and binding the drivers to available services accordingly.
摘要翻译：公开了在处理器系统中提供双模驱动器的方法和装置。本文公开的示例性方法包括在OS不可知模式期间可用的操作系统（OS）不可知模式服务，以允许在引导模式和OS不可知模式期间使用单组驱动器。该示例方法还包括包括能够确定处理器系统的当前操作模式并且相应地将驱动程序绑定到可用服务的双模式库。

3. 发明申请

US20050240669A1 BIOS framework for accommodating multiple service processors on a single server to facilitate distributed/scalable server management 审中-公开
标题翻译：用于在单个服务器上容纳多个服务处理器以便于分布式/可扩展服务器管理的BIOS框架
公开(公告)号：US20050240669A1
公开(公告)日：2005-10-27
申请号：US10811755
申请日：2004-03-29
申请人： Rahul Khanna , Mallik Bulusu , Vincent Zimmer
发明人： Rahul Khanna , Mallik Bulusu , Vincent Zimmer
IPC分类号： G06F9/50 , G06F15/173
CPC分类号： G06F15/177 , G06F9/4405 , G06F9/4413 , G06F9/5055 , G06F11/3447 , G06F11/3495
摘要： BIOS framework for accommodating multiple service processors on a single server to facilitate distributed/scalable server management. During a pre-boot phase for a server, information is collected pertaining to service capabilities supported by each of a plurality of service processors used to service server management requests for a server, wherein the services supported by each service processor are performed via execution of service code associated with that service processor. The service capabilities are aggregated across all of the service processors, and a corresponding unified presentation of service capabilities is provided to a service consumer. End-users are enabled to provide preferences that define a usage order for like services hosted by different service processors within the same system. The BIOS framework can detect the addition or removal of hot-swap cards hosting one or more service processors and associated service code, and update the unified presentation of service capabilities to reflect new added service capabilities or remove previously existing service capabilities.
摘要翻译：用于在单个服务器上容纳多个服务处理器以便于分布式/可扩展服务器管理的BIOS框架。在服务器的预引导阶段期间，收集关于用于服务服务器的服务器管理请求的多个服务处理器中的每一个所支持的服务能力的信息，其中由每个服务处理器支持的服务通过服务执行与该服务处理器相关联的代码。服务能力在所有服务处理器之间进行聚合，并向服务使用者提供相应的服务能力统一呈现。最终用户能够提供定义同一系统内由不同服务处理器托管的类似服务的使用顺序的首选项。 BIOS框架可以检测托管一个或多个服务处理器和相关服务代码的热插拔卡的添加或删除，并更新服务功能的统一呈现以反映新的附加服务功能或删除先前存在的服务功能。

4. 发明申请

US20070006048A1 Method and apparatus for predicting memory failure in a memory system 审中-公开
标题翻译：用于预测存储器系统中的存储器故障的方法和装置
公开(公告)号：US20070006048A1
公开(公告)日：2007-01-04
申请号：US11169408
申请日：2005-06-29
申请人： Vincent Zimmer , Gundrala Goud , Rahul Khanna , Mallik Bulusu , Satish Rai , Michael Rothman
发明人： Vincent Zimmer , Gundrala Goud , Rahul Khanna , Mallik Bulusu , Satish Rai , Michael Rothman
IPC分类号： G06F11/00
CPC分类号： G06F11/008
摘要： A method for managing a memory system includes comparing one or more conditions of a memory with historical memory data that predicts a future state of the memory. According to one embodiment, updating the historical memory data includes accumulating operation data on the memory during its operation, generating updated historical memory data with the operation data, and updating the historical memory data with the updated historical memory data. Other embodiments are described and claimed.
摘要翻译：用于管理存储器系统的方法包括将存储器的一个或多个条件与预测存储器的未来状态的历史存储器数据进行比较。根据一个实施例，更新历史存储器数据包括在其操作期间在存储器上累积操作数据，用操作数据生成更新的历史存储器数据，以及用更新的历史存储器数据更新历史存储器数据。描述和要求保护其他实施例。

5. 发明申请

US20060129795A1 Interleaved boot block to support multiple processor architectures and method of use 有权
标题翻译：交叉引导块支持多种处理器架构和使用方法
公开(公告)号：US20060129795A1
公开(公告)日：2006-06-15
申请号：US11010167
申请日：2004-12-10
申请人： Mallik Bulusu , Vincent Zimmer , Rahul Khanna
发明人： Mallik Bulusu , Vincent Zimmer , Rahul Khanna
IPC分类号： G06F15/177
CPC分类号： G06F9/4401
摘要： A flash memory has an interleaved boot block compatible with multiple processor architectures. The interleaved boot block may include one boot block compatible with a first CPU architecture and another boot block compatible with a second CPU architecture. These two boot blocks may be combined in an interleaved manner in the flash memory so that during a boot process only one of the two boot blocks executes, although both are stored in the flash memory. By interleaving different boot blocks, a common socket computer system capable of supporting multiple processor architectures may be achieved without fully replacing an incompatible basic input/output system (BIOS). Further, the flash memory may contain an updatable portion in which any BIOS segments incompatible with a processor architecture may be updated via a recovery, or update, process.
摘要翻译：闪存具有与多种处理器架构兼容的交错引导块。交错的引导块可以包括与第一CPU架构兼容的一个引导块和与第二CPU架构兼容的另一启动块。这两个引导块可以以交错方式组合在闪速存储器中，使得在引导过程中，两个引导块中只有一个执行，尽管两者都存储在闪存中。通过交织不同的引导块，可以在不完全替换不兼容的基本输入/输出系统（BIOS）的情况下实现能够支持多处理器体系结构的公共套接字计算机系统。此外，闪存可以包含可更新部分，其中可以经由恢复或更新过程来更新与处理器架构不兼容的任何BIOS段。

6. 发明授权

US07587750B2 Method and system to support network port authentication from out-of-band firmware 失效
标题翻译：从带外固件支持网络端口认证的方法和系统
公开(公告)号：US07587750B2
公开(公告)日：2009-09-08
申请号：US10607678
申请日：2003-06-26
申请人： Vincent J. Zimmer , Rahul Khanna , Mallik Bulusu
发明人： Vincent J. Zimmer , Rahul Khanna , Mallik Bulusu
IPC分类号： H04L9/32 , G06F15/16
CPC分类号： H04L63/08 , G06F21/575 , G06F2221/2103 , H04L63/10
摘要： Methods and systems for performing network port authentication without requiring any operating system (OS) complicity are disclosed. Under one method, port authentication instructions are loaded into a protected memory space during a pre-boot of a supplicant system. In response to a port authentication request, the supplicant system's processor is switched to a hidden execution mode and executes the port authentication instructions to authenticate a network port hosted by an authenticator system to which the supplicant system is linked. One authentication process employs an authentication server that authenticates the supplicant via one of various authentication schemes, including an access challenge. Port authentication may also be performed via an out-of-band base management controller that operates independently from an operating system running on the supplicant.
摘要翻译：公开了用于执行网络端口认证而不需要任何操作系统（OS）并发的方法和系统。在一种方法下，在请求者系统的预引导期间，端口认证指令被加载到受保护的存储器空间中。响应于端口认证请求，请求者系统的处理器被切换到隐藏的执行模式，并且执行端口认证指令以验证由请求方系统链接到的认证器系统托管的网络端口。一个认证过程采用认证服务器，其通过各种认证方案之一来验证请求者，包括接入质询。端口认证还可以通过独立于在请求方上运行的操作系统操作的带外基本管理控制器来执行。

7. 发明授权

US07305544B2 Interleaved boot block to support multiple processor architectures and method of use 有权
标题翻译：交叉引导块支持多种处理器架构和使用方法
公开(公告)号：US07305544B2
公开(公告)日：2007-12-04
申请号：US11010167
申请日：2004-12-10
申请人： Mallik Bulusu , Vincent J. Zimmer , Rahul Khanna
发明人： Mallik Bulusu , Vincent J. Zimmer , Rahul Khanna
IPC分类号： G06F15/177 , G06F9/24
CPC分类号： G06F9/4401
摘要： A flash memory has an interleaved boot block compatible with multiple processor architectures. The interleaved boot block may include one boot block compatible with a first CPU architecture and another boot block compatible with a second CPU architecture. These two boot blocks may be combined in an interleaved manner in the flash memory so that during a boot process only one of the two boot blocks executes, although both are stored in the flash memory. By interleaving different boot blocks, a common socket computer system capable of supporting multiple processor architectures may be achieved without fully replacing an incompatible basic input/output system (BIOS). Further, the flash memory may contain an updatable portion in which any BIOS segments incompatible with a processor architecture may be updated via a recovery, or update, process.
摘要翻译：闪存具有与多种处理器架构兼容的交错引导块。交错的引导块可以包括与第一CPU架构兼容的一个引导块和与第二CPU架构兼容的另一启动块。这两个引导块可以以交错方式组合在闪速存储器中，使得在引导过程中，两个引导块中只有一个执行，尽管两者都存储在闪速存储器中。通过交织不同的引导块，可以在不完全替换不兼容的基本输入/输出系统（BIOS）的情况下实现能够支持多处理器体系结构的公共套接字计算机系统。此外，闪存可以包含可更新部分，其中可以经由恢复或更新过程来更新与处理器架构不兼容的任何BIOS段。

8. 发明申请

US20120025953A1 MULTI-SOCKET SERVER MANAGEMENT WITH RFID 有权
标题翻译：带RFID的多插座服务器管理
公开(公告)号：US20120025953A1
公开(公告)日：2012-02-02
申请号：US12848654
申请日：2010-08-02
申请人： Robert C. Swanson , Vincent J. Zimmer , Mallik Bulusu , Michael A. Rothman , Palsamy Sakthikumar
发明人： Robert C. Swanson , Vincent J. Zimmer , Mallik Bulusu , Michael A. Rothman , Palsamy Sakthikumar
IPC分类号： G06K7/01
CPC分类号： H04L45/02 , H04W4/80 , H04W84/18
摘要： Using radio frequency identification (RFID) tags embedded in processors within a computing system to assist in system initialization processing. The RFID tags provide a separate communication path to other components of the computing system during initialization processing, apart from the system interconnect. When the computing system is powered up, each processor in the system may cause its RFID tag to broadcast data regarding the processor's interconnect location and initialization status. The RFID tags may be sensed by a RFID receiver in the Platform Control Hub (PCH) of the computing system, and each processor's interconnect location and initialization status data may be stored in selected registers within the PCH. When the BIOS executes during system initialization processing, the BIOS may access these PCH registers to obtain the processor's data. The interconnect location and initialization status data may be used by the BIOS to select the optimal routing table and to configure the virtual network within the computing system based at least in part on the optimal routing table and the RFID tag data and without the need for interrogating each processor individually over the system interconnect.
摘要翻译：使用嵌入在计算系统内的处理器中的射频识别（RFID）标签来协助系统初始化处理。除了系统互连，RFID标签在初始化处理期间提供到计算系统的其他组件的单独的通信路径。当计算系统通电时，系统中的每个处理器可能使其RFID标签广播关于处理器的互连位置和初始化状态的数据。 RFID标签可以由计算系统的平台控制中心（PCH）中的RFID接收器感测，并且每个处理器的互连位置和初始化状态数据可以存储在PCH内的选定的寄存器中。当BIOS在系统初始化处理期间执行时，BIOS可以访问这些PCH寄存器以获得处理器的数据。 BIOS可以使用互连位置和初始化状态数据来选择最佳路由表并且至少部分地基于最佳路由表和RFID标签数据来配置计算系统内的虚拟网络，并且不需要询问每个处理器分别通过系统互连。

9. 发明申请

US20110307712A1 MULTI-OWNER DEPLOYMENT OF FIRMWARE IMAGES 有权
标题翻译：多媒体图像的多业务部署
公开(公告)号：US20110307712A1
公开(公告)日：2011-12-15
申请号：US12814246
申请日：2010-06-11
申请人： Palsamy Sakthikumar , Robert C. Swanson , Vincent J. Zimmer , Michael A. Rothman , Mallik Bulusu
发明人： Palsamy Sakthikumar , Robert C. Swanson , Vincent J. Zimmer , Michael A. Rothman , Mallik Bulusu
IPC分类号： H04L9/00
CPC分类号： G06F21/572 , G06F2221/2141
摘要： A method, apparatus, system, and computer program product for multi-owner deployment of firmware images. The method includes obtaining a signed firmware image that comprises a first code module signed by a first code owner and a second code module signed by a second code owner. The method further includes obtaining an updated first code module comprising updated code for the first code module, verifying that the updated first code module is signed by the first code owner, and updating the signed firmware image with the updated first code module in response to verifying that the updated first code module is signed by the first code owner. The signed firmware image may further comprise an access control list that authorizes updates to the first code module by the first code owner and updates to the second code module by the second code owner.
摘要翻译：一种用于多所有者部署固件映像的方法，设备，系统和计算机程序产品。该方法包括获得包括由第一代码所有者签名的第一代码模块和由第二代码所有者签名的第二代码模块的签名固件映像。所述方法还包括获得包括用于第一代码模块的更新代码的更新的第一代码模块，验证所更新的第一代码模块是否被第一代码所有者签名，以及响应于验证更新带有更新的第一代码模块的已签名固件映像更新的第一代码模块由第一代码所有者签名。签名的固件图像还可以包括访问控制列表，其授权第一代码所有者更新第一代码模块，并由第二代码所有者更新第二代码模块。

10. 发明申请

US20080244250A1 Instant on video 有权
标题翻译：即时视频
公开(公告)号：US20080244250A1
公开(公告)日：2008-10-02
申请号：US11731525
申请日：2007-03-30
申请人： Robert C. Swanson , Michael A. Rothman , Mallik Bulusu , Vincent J. Zimmer
发明人： Robert C. Swanson , Michael A. Rothman , Mallik Bulusu , Vincent J. Zimmer
IPC分类号： G06F9/00
CPC分类号： G06F9/4403 , G06F9/4401
摘要： In some embodiments, the invention involves speeding boot up of a platform by initializing the video card early on in the boot process. In an embodiment, processor cache memory is to be used as cache as RAM (CAR). Video graphics adapter (VGA) card initialization uses the CAR instead of system RAM to perform initialization. A portion of the firmware code, interrupt vector tables and handlers are mirrored in the CAR, from flash memory to mimic the behavior of system RAM during the video initialization. VGA initialization may occur before system RAM has initialized to enable early visual feedback to a user. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，本发明涉及通过在启动过程中提前初始化视频卡来加速平台的启动。在一个实施例中，将处理器高速缓冲存储器用作高速缓存作为RAM（CAR）。视频图形适配器（VGA）卡初始化使用CAR代替系统RAM执行初始化。固件代码，中断向量表和处理程序的一部分在CAR中从闪存镜像到模拟视频初始化期间系统RAM的行为。在系统RAM初始化之前可能会发生VGA初始化，以便能够为用户提供早期的视觉反馈。描述和要求保护其他实施例。

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