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1. 发明授权

US08456341B2 Three-level digital-to-analog converter 有权
标题翻译：三电平数模转换器
公开(公告)号：US08456341B2
公开(公告)日：2013-06-04
申请号：US13134301
申请日：2011-06-03
申请人： Rahmi Hezar , Baher Haroun , Halil Kiper , Mounir Fares , Ajay Kumar
发明人： Rahmi Hezar , Baher Haroun , Halil Kiper , Mounir Fares , Ajay Kumar
IPC分类号： H03M1/66
CPC分类号： H03M1/66 , H03M1/747 , H03M3/464
摘要： A system for processing a signal includes a detector configured to detect a two-level stream of bits; a converter configured to generate a three-level control signal based on two adjacent values within the two-level stream of bits; and a switch configured to determine which of three different paths to couple a current source to based on a value of the three-level control signal. Thus, based on adjacent values of the output stream a three-level control signal is generated which controls coupling of the current source to one of three different paths. This type of three-level digital-to-analog converter can be, for example, part of the feedback loop of an analog-to-digital converter. Similar techniques can also be utilized in a multi-segment digital-to-analog converter in which each segment of the DAC is controlled by a 3-level control signal and the DAC is implement using PMOS devices. The current source for each DAC segment is diverted to ground, the M-node, or the P-node depending on the value of the 3-level control signal.
摘要翻译：一种用于处理信号的系统包括：检测器，被配置为检测两级比特流; 转换器，被配置为基于所述两级比特流内的两个相邻值生成三电平控制信号; 以及开关，被配置为基于三电平控制信号的值来确定三个不同路径中的哪一个耦合电流源。因此，基于输出流的相邻值，生成三电平控制信号，其控制电流源与三个不同路径之一的耦合。这种类型的三电平数模转换器可以是例如模数转换器的反馈回路的一部分。类似技术也可以用在多段数模转换器中，其中DAC的每个段由3电平控制信号控制，并且使用PMOS器件来实现DAC。每个DAC段的电流源根据3电平控制信号的值转移到地，M节点或P节点。

2. 发明申请

US20120306678A1 Three-level digital-to-analog converter 有权
标题翻译：三电平数模转换器
公开(公告)号：US20120306678A1
公开(公告)日：2012-12-06
申请号：US13134301
申请日：2011-06-03
申请人： Rahmi Hezar , Baher Haroun , Halil Kiper , Mounir Fares , Ajay Kumar
发明人： Rahmi Hezar , Baher Haroun , Halil Kiper , Mounir Fares , Ajay Kumar
IPC分类号： H03M1/72
CPC分类号： H03M1/66 , H03M1/747 , H03M3/464
摘要： A system for processing a signal includes a detector configured to detect a two-level stream of bits; a converter configured to generate a three-level control signal based on two adjacent values within the two-level stream of bits; and a switch configured to determine which of three different paths to couple a current source to based on a value of the three-level control signal. Thus, based on adjacent values of the output stream a three-level control signal is generated which controls coupling of the current source to one of three different paths. This type of three-level digital-to-analog converter can be, for example, part of the feedback loop of an analog-to-digital converter. Similar techniques can also be utilized in a multi-segment digital-to-analog converter in which each segment of the DAC is controlled by a 3-level control signal and the DAC is implement using PMOS devices. The current source for each DAC segment is diverted to ground, the M-node, or the P-node depending on the value of the 3-level control signal.
摘要翻译：一种用于处理信号的系统包括：检测器，被配置为检测两级比特流; 转换器，被配置为基于所述两级比特流内的两个相邻值生成三电平控制信号; 以及开关，被配置为基于三电平控制信号的值来确定三个不同路径中的哪一个耦合电流源。因此，基于输出流的相邻值，生成三电平控制信号，其控制电流源与三个不同路径之一的耦合。这种类型的三电平数模转换器可以是例如模数转换器的反馈回路的一部分。类似的技术也可以用在多段数模转换器中，其中DAC的每个段由3电平控制信号控制，并且使用PMOS器件实现DAC。每个DAC段的电流源根据3电平控制信号的值转移到地，M节点或P节点。

3. 发明授权

US08483856B2 System and method for correcting phase noise in digital-to-analog converter or analog-to-digital converter 有权
标题翻译：用于校正数模转换器或模数转换器中的相位噪声的系统和方法
公开(公告)号：US08483856B2
公开(公告)日：2013-07-09
申请号：US12783290
申请日：2010-05-19
申请人： Rahmi Hezar , Baher Haroun
发明人： Rahmi Hezar , Baher Haroun
IPC分类号： G06F17/00
CPC分类号： H03M3/372 , H03M3/50
摘要： A circuit includes a digital oscillator, a phase lock loop (PLL), a digital signal generator, a correction circuit and a digital-to-analog converter DAC (DAC). The digital oscillator can output a reference clock signal. The PLL can output a system clock signal based on the reference clock signal. The digital signal generator can output a digital signal based on the system clock signal. The correction circuit can output a pre-distorted signal based on the reference clock signal, the system clock signal and the digital signal. The DAC can output an analog signal based on the pre-distorted signal and the system clock signal.
摘要翻译：电路包括数字振荡器，锁相环（PLL），数字信号发生器，校正电路和数模转换器DAC（DAC）。数字振荡器可以输出参考时钟信号。 PLL可以基于参考时钟信号输出系统时钟信号。数字信号发生器可以根据系统时钟信号输出数字信号。校正电路可以基于参考时钟信号，系统时钟信号和数字信号输出预失真信号。 DAC可以根据预失真信号和系统时钟信号输出模拟信号。

4. 发明申请

US20120286868A1 CLASS D POWER AMPLIFIER 有权
标题翻译： CLASS D功率放大器
公开(公告)号：US20120286868A1
公开(公告)日：2012-11-15
申请号：US13106611
申请日：2011-05-12
申请人： Baher Haroun , Joonhoi Hur , Lei Ding , Rahmi Hezar
发明人： Baher Haroun , Joonhoi Hur , Lei Ding , Rahmi Hezar
IPC分类号： H03F3/217
CPC分类号： H03F3/2173 , H03F1/26 , H03F2200/267 , H03F2200/297
摘要： A class D power amplifier (PA) is provided. The PA generally comprises a driver, output capacitor, a matching network, and a cancellation circuit. The driver has an input, an output, and a parasitic capacitance, and the input of the driver is configured to receive complementary first and second radio frequency (RF) signals, where there is a free-fly interval between consecutive pulses from the first and second RF signals. The output capacitor and cancellation circuit are each coupled to the output of the driver such that the cancellation circuit provides harmonic restoration at least during the free-fly interval, and the matching network is coupled to the output capacitor.
摘要翻译：提供D类功率放大器（PA）。 PA通常包括驱动器，输出电容器，匹配网络和消除电路。驱动器具有输入，输出和寄生电容，并且驱动器的输入被配置为接收互补的第一和第二射频（RF）信号，其中在来自第一和第二射频的连续脉冲之间存在自由间隔第二RF信号。输出电容器和消除电路各自耦合到驱动器的输出，使得消除电路至少在空闲间隔期间提供谐波恢复，并且匹配网络耦合到输出电容器。

5. 发明申请

US20110285433A1 SYSTEM AND METHOD FOR CORRECTING PHASE NOISE IN DIGITAL-TO-ANALOG CONVERTER OR ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译：用于校正数字到模拟转换器或模拟数字转换器中的相位噪声的系统和方法
公开(公告)号：US20110285433A1
公开(公告)日：2011-11-24
申请号：US12783290
申请日：2010-05-19
申请人： Rahmi Hezar , Baher Haroun
发明人： Rahmi Hezar , Baher Haroun
IPC分类号： H03L7/08
CPC分类号： H03M3/372 , H03M3/50
摘要： A circuit includes a digital oscillator, a phase lock loop (PLL), a digital signal generator, a correction circuit and a digital-to-analog converter DAC (DAC). The digital oscillator can output a reference clock signal. The PLL can output a system clock signal based on the reference clock signal. The digital signal generator can output a digital signal based on the system clock signal. The correction circuit can output a pre-distorted signal based on the reference clock signal, the system clock signal and the digital signal. The DAC can output an analog signal based on the pre-distorted signal and the system clock signal.
摘要翻译：电路包括数字振荡器，锁相环（PLL），数字信号发生器，校正电路和数模转换器DAC（DAC）。数字振荡器可以输出参考时钟信号。 PLL可以基于参考时钟信号输出系统时钟信号。数字信号发生器可以根据系统时钟信号输出数字信号。校正电路可以基于参考时钟信号，系统时钟信号和数字信号输出预失真信号。 DAC可以根据预失真信号和系统时钟信号输出模拟信号。

6. 发明申请

US20050162222A1 Amplifier using delta-sigma modulation 有权
标题翻译：使用Δ-Σ调制的放大器
公开(公告)号：US20050162222A1
公开(公告)日：2005-07-28
申请号：US10762819
申请日：2004-01-22
申请人： Rahmi Hezar , Baher Haroun
发明人： Rahmi Hezar , Baher Haroun
IPC分类号： H03F3/217 , H03F3/38
CPC分类号： H03F3/217 , H03F2200/331
摘要： An amplifier and a driver circuit therefor are presented for driving a load according to a system analog input. The amplifier comprises a passive delta-sigma modulator with a passive filter providing a first filtered signal according to a passive filter input and according to a feedback signal, a quantizer coupled with the passive filter and providing a quantized output according to the first filtered signal, and a switching system coupled with the the passive filter and the quantizer. The switching system selectively providing power to a load according to the quantized output and provides the feedback signal to the passive input, wherein a gain amplifier is provided in a feedback loop around the passive delta-sigma modulator.
摘要翻译：介绍放大器及其驱动电路，用于根据系统模拟输入驱动负载。该放大器包括无源Δ-Σ调制器，无源滤波器根据无源滤波器输入提供第一滤波信号，并根据反馈信号，与无源滤波器耦合的量化器，并根据第一滤波信号提供量化输出，以及与无源滤波器和量化器耦合的开关系统。开关系统根据量化的输出选择性地向负载提供电力，并将反馈信号提供给无源输入，其中增益放大器设置在无源Δ-Σ调制器周围的反馈回路中。

7. 发明申请

US20130148760A1 TRANSFORMER POWER COMBINER WITH FILTER RESPONSE 有权
标题翻译：具有过滤器响应的变压器动力组合器
公开(公告)号：US20130148760A1
公开(公告)日：2013-06-13
申请号：US13313971
申请日：2011-12-07
申请人： Rahmi Hezar , Lei Ding , Joonhoi Hur , Baher Haroun
发明人： Rahmi Hezar , Lei Ding , Joonhoi Hur , Baher Haroun
IPC分类号： H04L25/49
CPC分类号： H03F3/211 , H03F3/24 , H04L25/4902
摘要： A method for generating an amplified radio frequency (RF) signal is provided. In-phase (I) and quadrature (Q) signals are received and interleaved so as to generate a time-interleaved signal. Delayed time-interleaved signals are then generated from the time interleaved signal, and each of the delayed time-interleaved signals is amplified so as to generate a plurality of amplified signals. The amplified signals are then combined with a transformer, where the delayed time-interleaved signals are arranged to generate a filter response with the transformer.
摘要翻译：提供了一种用于产生放大射频（RF）信号的方法。接收和交织同相（I）和正交（Q）信号，以产生时间交织的信号。然后从时间交织信号产生延迟的时间交织信号，并且每个延迟时间交织的信号被放大以产生多个放大的信号。然后将放大的信号与变压器组合，其中延迟的时间交织信号被布置成产生与变压器的滤波器响应。

8. 发明授权

US06930624B2 Continuous time fourth order delta sigma analog-to-digital converter 有权
标题翻译：连续时间四阶Δ西格玛模数转换器
公开(公告)号：US06930624B2
公开(公告)日：2005-08-16
申请号：US10699585
申请日：2003-10-31
申请人： Rahmi Hezar , Baher Haroun
发明人： Rahmi Hezar , Baher Haroun
IPC分类号： H03M3/00 , H03M3/02
CPC分类号： H03M3/322 , H03M3/43 , H03M3/454
摘要： A fourth order delta sigma analog-to-digital converter is presented, comprising a passive delta sigma modulator including a passive filter, a quantizer, and a digital-to-analog converter in a first feedback loop, and an active filter having a large gain factor in a second feedback loop around the passive delta-sigma modulator.
摘要翻译：提出了一种第四级ΔΣ模数转换器，包括在第一反馈回路中包括无源滤波器，量化器和数模转换器的无源Δ-Σ调制器和具有大增益的有源滤波器在被动Δ-Σ调制器周围的第二反馈环路中的因子。

9. 发明授权

US08373504B2 Class D power amplifier 有权
标题翻译： D类功率放大器
公开(公告)号：US08373504B2
公开(公告)日：2013-02-12
申请号：US13106611
申请日：2011-05-12
申请人： Baher Haroun , Joonhoi Hur , Lei Ding , Rahmi Hezar
发明人： Baher Haroun , Joonhoi Hur , Lei Ding , Rahmi Hezar
IPC分类号： H03F3/217
CPC分类号： H03F3/2173 , H03F1/26 , H03F2200/267 , H03F2200/297
摘要： A class D power amplifier (PA) is provided. The PA generally comprises a driver, output capacitor, a matching network, and a cancellation circuit. The driver has an input, an output, and a parasitic capacitance, and the input of the driver is configured to receive complementary first and second radio frequency (RF) signals, where there is a free-fly interval between consecutive pulses from the first and second RF signals. The output capacitor and cancellation circuit are each coupled to the output of the driver such that the cancellation circuit provides harmonic restoration at least during the free-fly interval, and the matching network is coupled to the output capacitor.
摘要翻译：提供D类功率放大器（PA）。 PA通常包括驱动器，输出电容器，匹配网络和消除电路。驱动器具有输入，输出和寄生电容，并且驱动器的输入被配置为接收互补的第一和第二射频（RF）信号，其中在来自第一和第二射频的连续脉冲之间存在自由间隔第二RF信号。输出电容器和消除电路各自耦合到驱动器的输出，使得消除电路至少在空闲间隔期间提供谐波恢复，并且匹配网络耦合到输出电容器。

10. 发明申请

US20050116850A1 CONTINUOUS TIME FOURTH ORDER DELTA SIGMA ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译：连续时间四分之三的SIGMA模拟数字转换器
公开(公告)号：US20050116850A1
公开(公告)日：2005-06-02
申请号：US10699585
申请日：2003-10-31
申请人： Rahmi Hezar , Baher Haroun
发明人： Rahmi Hezar , Baher Haroun
IPC分类号： H03M3/00 , H03M3/02
CPC分类号： H03M3/322 , H03M3/43 , H03M3/454
摘要： A fourth order delta sigma analog-to-digital converter is presented, comprising a passive delta sigma modulator including a passive filter, a quantizer, and a digital-to-analog converter in a first feedback loop, and an active filter having a large gain factor in a second feedback loop around the passive delta-sigma modulator.
摘要翻译：提出了一种第四级ΔΣ模数转换器，包括在第一反馈回路中包括无源滤波器，量化器和数模转换器的无源Δ-Σ调制器和具有大增益的有源滤波器在被动Δ-Σ调制器周围的第二反馈环路中的因子。

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