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1. 发明授权

US06950841B2 Logarithmic lookup tables 有权
标题翻译：对数查询表
公开(公告)号：US06950841B2
公开(公告)日：2005-09-27
申请号：US09954760
申请日：2001-09-14
申请人： Raghu Challa , Nagabhushana Sindhushayana , Arun Raghupathy
发明人： Raghu Challa , Nagabhushana Sindhushayana , Arun Raghupathy
IPC分类号： G06F1/02 , G06F1/03 , G06F7/00 , G06F7/523 , G06F7/556 , H04B1/16 , H04B1/707
CPC分类号： G06F7/5235 , G06F1/0356 , G06F2101/10
摘要： In one embodiment, the invention is directed toward techniques for generating results in a logarithmic domain. The techniques may exploit properties of a logarithmic function to reduce the memory requirements needed to implement lookup tables. For example, the techniques may utilize non-uniform sampling over a logarithmic or logarithmic-like function to reduce the number of entries needed for a given lookup table. In particular, the techniques may involve separating a number into an exponent component and a mantissa component. Each of these different components can then be converted from a first domain to a second domain using different lookup tables.
摘要翻译：在一个实施例中，本发明涉及用于在对数域中生成结果的技术。这些技术可以利用对数函数的属性来减少实现查找表所需的内存要求。例如，这些技术可以利用对数或类似对数的函数的非均匀采样来减少给定查找表所需的条目数。特别地，这些技术可以包括将数字分成指数分量和尾数分量。然后可以使用不同的查找表将这些不同组件中的每一个从第一域转换为第二域。

2. 发明授权

US06748201B2 Gain control for communications device 失效
标题翻译：增益控制通信设备
公开(公告)号：US06748201B2
公开(公告)日：2004-06-08
申请号：US10112642
申请日：2002-03-28
申请人： Peter J. Black , Nagabhushana Sindhushayana , Raghu Challa , Kevin Seltmann
发明人： Peter J. Black , Nagabhushana Sindhushayana , Raghu Challa , Kevin Seltmann
IPC分类号： H04B138
CPC分类号： H03G3/3036 , H03G3/3068
摘要： Systems and techniques for gain control include amplifying a signal with an amplifier having a gain represented by one of a plurality of gain curves depending on a value of a parameter, the signal being amplified at a first one of the parameter values, and controlling the gain of the amplified signal from a predetermined gain curve relating to the gain curve of the amplifier for a second one of the parameter values by adjusting a gain control signal corresponding to a point on the predetermined gain curve as a function of the first one of the parameter values, and applying the adjusted gain control signal to the amplifier. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译：用于增益控制的系统和技术包括用具有根据参数值的多个增益曲线之一表示的增益的放大器放大信号，该信号在第一个参数值处被放大，并且控制增益通过调整与预定增益曲线上的点相对应的增益控制信号作为参数中的第一个的函数，来从与放大器对于第二参数值的增益曲线相关的预定增益曲线的放大信号值，并将调整后的增益控制信号应用于放大器。要强调的是，该摘要被提供以符合要求摘要的规则，这将允许搜索者或其他读者快速确定技术公开的主题。

3. 发明授权

US06594501B2 Systems and techniques for channel gain computations 失效
标题翻译：通道增益计算的系统和技术
公开(公告)号：US06594501B2
公开(公告)日：2003-07-15
申请号：US10104208
申请日：2002-03-20
申请人： Peter J. Black , Nagabhushana Sindhushayana , Raghu Challa , Rashid Attar
发明人： Peter J. Black , Nagabhushana Sindhushayana , Raghu Challa , Rashid Attar
IPC分类号： H04B700
CPC分类号： H04W52/16 , H04W52/08 , H04W52/10 , H04W52/26 , H04W52/325 , H04W52/36
摘要： Systems and techniques for controlling transmission power involve receiving a first to second channel power ratio, receiving a first to second channel power ratio, adjusting the power ratio if a combined power of a plurality of channels exceeds a threshold, the channels including the first and second channels, and computing gain of the first channel as a function of the power ratio. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.
摘要翻译：用于控制传输功率的系统和技术涉及接收第一至第二信道功率比，接收第一至第二信道功率比，如果多个信道的组合功率超过阈值，则调整功率比，所述信道包括第一和第二信道功率比通道和第一通道的计算增益作为功率比的函数。要强调的是，该摘要被提供以符合要求摘要的规则，这将允许搜索者或其他读者快速确定技术公开的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

4. 发明授权

US08626099B2 Direct conversion receiver architecture 有权
标题翻译：直接转换接收机架构
公开(公告)号：US08626099B2
公开(公告)日：2014-01-07
申请号：US11376502
申请日：2006-03-14
申请人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
发明人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
IPC分类号： H04B1/06
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
摘要翻译：具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。可以如本文所述有利地设计和定位DVGA。可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。一些或全部RF /模拟电路的控制可以通过串行总线提供。

5. 发明授权

US08615212B2 Direct conversion receiver architecture 有权
公开(公告)号：US08615212B2
公开(公告)日：2013-12-24
申请号：US11862330
申请日：2007-09-27
申请人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
发明人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
IPC分类号： H04B7/00
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

6. 发明授权

US07076225B2 Variable gain selection in direct conversion receiver 失效
标题翻译：直接转换接收机中的可变增益选择
公开(公告)号：US07076225B2
公开(公告)日：2006-07-11
申请号：US10034734
申请日：2001-12-21
申请人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
发明人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
IPC分类号： H04B7/00
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
摘要翻译：具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。可以如本文所述有利地设计和定位DVGA。可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。一些或全部RF /模拟电路的控制可以通过串行总线提供。

7. 发明申请

US20080014895A1 DIRECT CONVERSION RECEIVER ARCHITECTURE 有权
标题翻译：直接转换接收机架构
公开(公告)号：US20080014895A1
公开(公告)日：2008-01-17
申请号：US11862330
申请日：2007-09-27
申请人： Tao Li , Christian Holenstein , Inyup Kang , Brett Walker , Paul Peterzell , Raghu Challa , Matthew Severson , Arun Raghupathy , Gilbert Sih
发明人： Tao Li , Christian Holenstein , Inyup Kang , Brett Walker , Paul Peterzell , Raghu Challa , Matthew Severson , Arun Raghupathy , Gilbert Sih
IPC分类号： H04B1/26
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
摘要翻译：具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。可以如本文所述有利地设计和定位DVGA。可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。一些或全部RF /模拟电路的控制可以通过串行总线提供。

8. 发明申请

US20110105070A1 Direct conversion receiver architecture 有权
标题翻译：直接转换接收机架构
公开(公告)号：US20110105070A1
公开(公告)日：2011-05-05
申请号：US11376502
申请日：2006-03-14
申请人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
发明人： Tao Li , Christian Holenstein , Inyup Kang , Brett C. Walker , Paul E. Peterzell , Raghu Challa , Matthew L. Severson , Arun Raghupathy , Gilbert Christopher Sih
IPC分类号： H03L5/00 , H04B1/16
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
摘要翻译：具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。可以如本文所述有利地设计和定位DVGA。可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。一些或全部RF /模拟电路的控制可以通过串行总线提供。

9. 发明授权

US08665996B2 Efficient parallel sub-packet decoding using multiple decoders 有权
标题翻译：使用多个解码器的高效并行子包解码
公开(公告)号：US08665996B2
公开(公告)日：2014-03-04
申请号：US12400124
申请日：2009-03-09
申请人： Joseph Zanotelli , Mrinal Mahesh Nath , Arunava Chaudhuri , Kaushik Ghosh , Raghu Challa , Weihong Jing
发明人： Joseph Zanotelli , Mrinal Mahesh Nath , Arunava Chaudhuri , Kaushik Ghosh , Raghu Challa , Weihong Jing
IPC分类号： H04L27/06
CPC分类号： H04L1/0045 , H03M13/2957 , H03M13/41 , H03M13/6508 , H03M13/6561 , H04L1/0052
摘要： A configurable decoder within a receiver (for example, within a wireless communication device) includes numerous decoders. In one mode, the multiple decoders are used to decode different sub-packets of a packet. When one decoder completes decoding the last sub-packet assigned to it of the packet, then that decoder generates a packet done indication. A control circuit receives the packet done indications, and when all the decoders have generated packet done indications then the control circuit initiates an action. In one example, the action is the interrupting of a processor. The processor responds by reading status information from the control circuit, thereby resetting the interrupt. End-of-packet markers are usable to generate packet done indications and to generate EOP interrupts. Similarly, end-of-group markers are usable to generate group done indications and to generate EOG interrupts. The decoder block is configurable to process sub-packets of a packet using either one or multiple decoders.
摘要翻译：接收机内的可配置解码器（例如，在无线通信设备内）包括许多解码器。在一种模式中，多个解码器用于解码分组的不同子分组。当一个解码器完成对分组给它的最后一个子分组的解码时，该解码器产生分组完成指示。控制电路接收分组完成指示，并且当所有解码器已经生成分组完成指示时，控制电路启动动作。在一个示例中，动作是处理器的中断。处理器通过从控制电路读取状态信息进行响应，从而复位中断。分组结束标记可用于生成分组完成指示并产生EOP中断。类似地，组尾标记可用于生成组完成指示并产生EOG中断。解码器块可配置为使用一个或多个解码器来处理分组的子分组。

10. 发明授权

US07436412B2 Graphics engine with efficient interpolation 有权
标题翻译：具有高效插值的图形引擎
公开(公告)号：US07436412B2
公开(公告)日：2008-10-14
申请号：US11211939
申请日：2005-08-24
申请人： Raghu Challa
发明人： Raghu Challa
IPC分类号： G09G5/00 , G09G5/02 , G06K9/32 , G06T11/40
CPC分类号： G06T11/40 , G06T9/00 , G06T15/005 , G06T15/80
摘要： A graphics engine includes a setup unit and a rendering unit. The setup unit computes coefficients A, B, and C used for interpolating an attribute v of a triangle to be rendered for a graphics image. The setup unit then derives compressed coefficients Ã, {tilde over (B)}, and {tilde over (C)} based on the coefficients A, B, and C. The compressed coefficients have a fixed-point format with R integer bits left of a binary point and T fractional bits right of the binary point, where R>1 and T≧0. R is selected based on the number of bits used for attribute v, T is selected based on the screen dimension, and R+T is much less than the number of bits used to represent the coefficients A, B, and C. The rendering unit performs interpolation for the attribute v using the compressed coefficients Ã, {tilde over (B)}, and {tilde over (C)}, and may be implemented with a simple (R+T)-bit non-saturating accumulator.
摘要翻译：图形引擎包括设置单元和渲染单元。设置单元计算用于内插用于图形图像呈现的三角形的属性v的系数A，B和C. 设置单元然后基于系数A，B和C导出压缩系数∈B和C。压缩系数具有固定点格式，其中R个整数位为二进制点，T分数位为二进制位点，其中R> 1和T> = 0。基于用于属性v的位数选择R，基于屏幕尺寸选择T，并且R + T远小于用于表示系数A，B和C的比特数。渲染单元使用压缩系数∈B和C对属性v执行内插，并且可以用简单（R + T）位非饱和累加器来实现。

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