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1. 发明申请

US20090294947A1 CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：芯片包装结构及其制造方法
公开(公告)号：US20090294947A1
公开(公告)日：2009-12-03
申请号：US12464873
申请日：2009-05-13
申请人： Ra-Min Tain , Yu-Lin Chao , Shu-Jung Yang , Rong-Chang Fang , Wei Li , Chih-Yuan Cheng , Ming-Che Hsieh
发明人： Ra-Min Tain , Yu-Lin Chao , Shu-Jung Yang , Rong-Chang Fang , Wei Li , Chih-Yuan Cheng , Ming-Che Hsieh
IPC分类号： H01L23/34 , H01L21/50 , H01L25/11
CPC分类号： H01L25/105 , H01L23/3128 , H01L25/0657 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2225/0652 , H01L2225/06541 , H01L2225/06589 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/10253 , H01L2924/15311 , H01L2924/00014 , H01L2924/00
摘要： A chip package structure includes a substrate, a chip, a thermal conductive layer, a plurality of signal contacts, and a molding compound. The substrate includes a plurality of first thermal conductive vias, a connecting circuit, and a plurality of signal vias electrically connected to the connecting circuit, and the substrate has a chip disposing region. The chip is disposed on the chip disposing region of the substrate and electrically connected to the signal vias through the connecting circuit. The thermal conductive layer is disposed over the substrate, connected to the first thermal conductive vias, and located above the chip disposing region. Besides, the thermal conductive layer has first openings exposing the signal vias. The signal contacts are respectively disposed in the first openings and connected to the signal vias. The molding compound encapsulates the chip.
摘要翻译：芯片封装结构包括衬底，芯片，导热层，多个信号触点和模塑料。衬底包括多个第一导热通孔，连接电路和电连接到连接电路的多个信号通孔，并且衬底具有芯片布置区域。芯片设置在基板的芯片布置区域上，并通过连接电路与信号通孔电连接。导热层设置在衬底上，连接到第一导热通孔，并且位于芯片布置区域的上方。此外，导热层具有暴露信号通孔的第一开口。信号触点分别设置在第一开口中并连接到信号通路。模塑料封装芯片。

2. 发明授权

US08004079B2 Chip package structure and manufacturing method thereof 有权
标题翻译：芯片封装结构及其制造方法
公开(公告)号：US08004079B2
公开(公告)日：2011-08-23
申请号：US12464873
申请日：2009-05-13
申请人： Ra-Min Tain , Yu-Lin Chao , Shu-Jung Yang , Rong-Chang Fang , Wei Li , Chih-Yuan Cheng , Ming-Che Hsieh
发明人： Ra-Min Tain , Yu-Lin Chao , Shu-Jung Yang , Rong-Chang Fang , Wei Li , Chih-Yuan Cheng , Ming-Che Hsieh
IPC分类号： H01L23/10 , H01L23/34
CPC分类号： H01L25/105 , H01L23/3128 , H01L25/0657 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2225/0652 , H01L2225/06541 , H01L2225/06589 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/10253 , H01L2924/15311 , H01L2924/00014 , H01L2924/00
摘要： A chip package structure includes a substrate, a chip, a thermal conductive layer, a plurality of signal contacts, and a molding compound. The substrate includes a plurality of first thermal conductive vias, a connecting circuit, and a plurality of signal vias electrically connected to the connecting circuit, and the substrate has a chip disposing region. The chip is disposed on the chip disposing region of the substrate and electrically connected to the signal vias through the connecting circuit. The thermal conductive layer is disposed over the substrate, connected to the first thermal conductive vias, and located above the chip disposing region. Besides, the thermal conductive layer has first openings exposing the signal vias. The signal contacts are respectively disposed in the first openings and connected to the signal vias. The molding compound encapsulates the chip.
摘要翻译：芯片封装结构包括衬底，芯片，导热层，多个信号触点和模塑料。衬底包括多个第一导热通孔，连接电路和电连接到连接电路的多个信号通孔，并且衬底具有芯片布置区域。芯片设置在基板的芯片布置区域上，并通过连接电路与信号通孔电连接。导热层设置在衬底上，连接到第一导热通孔，并且位于芯片布置区域的上方。此外，导热层具有暴露信号通孔的第一开口。信号触点分别设置在第一开口中并连接到信号通路。模塑料封装芯片。

3. 发明申请

US20110309357A1 MEASURING APPARATUS 有权
标题翻译：测量装置
公开(公告)号：US20110309357A1
公开(公告)日：2011-12-22
申请号：US12962658
申请日：2010-12-08
申请人： Ra-Min Tain , John H. Lau , Ming-Che Hsieh , Wei Li , Ming-Ji Dai
发明人： Ra-Min Tain , John H. Lau , Ming-Che Hsieh , Wei Li , Ming-Ji Dai
IPC分类号： H01L25/07
CPC分类号： G01B7/18 , G01L1/18 , G01L1/2206 , H01L2224/16145
摘要： A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface.
摘要翻译：提供了包括第一芯片，第一电路层，第一加热器，第一应力传感器和第二电路层的测量装置。第一芯片具有第一通孔硅通孔，第一表面和与第一表面相对的第二表面。第一电路层设置在第一表面上。第一加热器和第一应力传感器设置在第一表面上并连接到第一电路层。第二电路层设置在第二表面上。

4. 发明申请

US20110108973A1 CHIP PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：芯片包装结构及其制作方法
公开(公告)号：US20110108973A1
公开(公告)日：2011-05-12
申请号：US12748334
申请日：2010-03-26
申请人： Ming-Che Hsieh , Ra-Min Tain , Wei Li
发明人： Ming-Che Hsieh , Ra-Min Tain , Wei Li
IPC分类号： H01L23/522 , H01L21/768 , H01L23/48
CPC分类号： H01L25/50 , H01L21/7682 , H01L23/481 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L25/0657 , H01L2224/0401 , H01L2224/0557 , H01L2224/0603 , H01L2224/13025 , H01L2224/1403 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06572 , H01L2924/0002 , H01L2924/01019 , H01L2924/14 , H01L2224/05552
摘要： The disclosure provides a chip package structure and method for fabricating the same. The chip package structure includes at least one chip having at least one through via. At least one stress buffering structure is disposed in the through via. The stress buffering structure includes a first gasket and a second gasket. A supporting pillar has two terminals respectively connected to the first gasket and the second gasket. The cross-sectional area of the supporting pillar is smaller than areas of the first gasket and the second gasket. A buffering layer is sandwiched between the first gasket and the second gasket, surrounding a sidewall of the supporting pillar. An insulating layer is disposed on the through via, surrounding a sidewall of the stress buffering structure.
摘要翻译：本公开提供了一种芯片封装结构及其制造方法。芯片封装结构包括至少一个具有至少一个通孔的芯片。至少一个应力缓冲结构设置在通孔中。应力缓冲结构包括第一垫圈和第二垫圈。支撑柱具有分别连接到第一垫圈和第二垫圈的两个端子。支柱的横截面面积小于第一衬垫和第二衬垫的面积。缓冲层夹在第一衬垫和第二衬垫之间，围绕着支柱的侧壁。绝缘层设置在通孔上，围绕应力缓冲结构的侧壁。

5. 发明授权

US08502224B2 Measuring apparatus that includes a chip having a through silicon via, a heater, and a stress sensor 有权
标题翻译：包括具有硅通孔，加热器和应力传感器的芯片的测量装置
公开(公告)号：US08502224B2
公开(公告)日：2013-08-06
申请号：US12962658
申请日：2010-12-08
申请人： Ra-Min Tain , John H. Lau , Ming-Che Hsieh , Wei Li , Ming-Ji Dai
发明人： Ra-Min Tain , John H. Lau , Ming-Che Hsieh , Wei Li , Ming-Ji Dai
IPC分类号： H01L23/58
CPC分类号： G01B7/18 , G01L1/18 , G01L1/2206 , H01L2224/16145
摘要： A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface.
摘要翻译：提供了包括第一芯片，第一电路层，第一加热器，第一应力传感器和第二电路层的测量装置。第一芯片具有第一通孔硅通孔，第一表面和与第一表面相对的第二表面。第一电路层设置在第一表面上。第一加热器和第一应力传感器设置在第一表面上并连接到第一电路层。第二电路层设置在第二表面上。

6. 发明授权

US08102058B2 Chip package structure and method for fabricating the same 有权
标题翻译：芯片封装结构及其制造方法
公开(公告)号：US08102058B2
公开(公告)日：2012-01-24
申请号：US12748334
申请日：2010-03-26
申请人： Ming-Che Hsieh , Ra-Min Tain , Wei Li
发明人： Ming-Che Hsieh , Ra-Min Tain , Wei Li
IPC分类号： H01L23/52 , H01L23/48 , H01L23/40
CPC分类号： H01L25/50 , H01L21/7682 , H01L23/481 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L25/0657 , H01L2224/0401 , H01L2224/0557 , H01L2224/0603 , H01L2224/13025 , H01L2224/1403 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06572 , H01L2924/0002 , H01L2924/01019 , H01L2924/14 , H01L2224/05552
摘要： The disclosure provides a chip package structure and method for fabricating the same. The chip package structure includes at least one chip having at least one through via. At least one stress buffering structure is disposed in the through via. The stress buffering structure includes a first gasket and a second gasket. A supporting pillar has two terminals respectively connected to the first gasket and the second gasket. The cross-sectional area of the supporting pillar is smaller than areas of the first gasket and the second gasket. A buffering layer is sandwiched between the first gasket and the second gasket, surrounding a sidewall of the supporting pillar. An insulating layer is disposed on the through via, surrounding a sidewall of the stress buffering structure.
摘要翻译：本公开提供了一种芯片封装结构及其制造方法。芯片封装结构包括至少一个具有至少一个通孔的芯片。至少一个应力缓冲结构设置在通孔中。应力缓冲结构包括第一垫圈和第二垫圈。支撑柱具有分别连接到第一垫圈和第二垫圈的两个端子。支柱的横截面面积小于第一衬垫和第二衬垫的面积。缓冲层夹在第一衬垫和第二衬垫之间，围绕着支柱的侧壁。绝缘层设置在通孔上，围绕应力缓冲结构的侧壁。

7. 发明授权

US08397584B2 Fabricating method and testing method of semiconductor device and mechanical integrity testing apparatus 有权
标题翻译：半导体器件及机械完整性检测仪器的制作方法及测试方法
公开(公告)号：US08397584B2
公开(公告)日：2013-03-19
申请号：US13023545
申请日：2011-02-09
申请人： Ming-Che Hsieh , John H. Lau , Ra-Min Tain
发明人： Ming-Che Hsieh , John H. Lau , Ra-Min Tain
IPC分类号： G01N3/00 , G01N3/20
CPC分类号： H01L22/12 , G01N19/04 , H01L2224/16
摘要： A fabricating method and a testing method of a semiconductor device and a mechanical integrity testing apparatus are provided. An object includes a wafer, an insulating layer, and a plurality of conductive posts is provided. A surface of the wafer has a plurality of first blind holes outside chip regions and a plurality of second blind holes inside the chip regions. The insulating layer is between the conductive posts and the walls of the first blind holes and between the conductive posts and the walls of the second blind holes. A mechanical integrity test is performed to test a binding strength between the insulating layer, the conductive posts, and the walls of the first blind holes. The conductive posts in the chip regions are electrically connected to an element after the conductive posts in the first blind holes are qualified in the mechanical integrity test.
摘要翻译：提供了半导体器件和机械完整性测试装置的制造方法和测试方法。一种物体包括晶片，绝缘层和多个导电柱。晶片的表面在芯片区域外部具有多个第一盲孔和芯片区域内的多个第二盲孔。绝缘层位于导电柱和第一盲孔的壁之间以及导电柱和第二盲孔的壁之间。执行机械完整性测试以测试绝缘层，导电柱和第一盲孔的壁之间的结合强度。在机械完整性测试中，在第一盲孔中的导电柱被限定之后，芯片区域中的导电柱电连接到元件。

8. 发明授权

US08456017B2 Filled through-silicon via with conductive composite material 有权
标题翻译：用导电复合材料填充硅通孔
公开(公告)号：US08456017B2
公开(公告)日：2013-06-04
申请号：US13174794
申请日：2011-07-01
申请人： Ming-Ji Dai , Heng-Chieh Chien , Ming-Che Hsieh , Jui-Feng Hung , Ra-Min Tain , John H. Lau
发明人： Ming-Ji Dai , Heng-Chieh Chien , Ming-Che Hsieh , Jui-Feng Hung , Ra-Min Tain , John H. Lau
IPC分类号： H01L23/48
CPC分类号： H01L21/76898 , H01L21/486 , H01L23/147 , H01L23/481 , H01L23/49827 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/11009 , H01L2224/13082 , H01L2224/13147 , H01L2224/13155 , H01L2224/14181 , H01L2224/16225 , H01L2224/94 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06572 , H01L2924/00014 , H01L2924/10253 , H01L2924/10329 , H01L2924/12042 , H01L2924/1421 , H01L2924/1434 , H01L2924/3511 , H01L2924/01046 , H01L2924/01079 , H01L2224/03 , H01L2224/11 , H01L2224/05552 , H01L2924/00
摘要： By adding particles of high thermal conductivity and low thermal expansion coefficient into the copper as a composite material and filling with the composite material into the through-via hole, the mismatch of the coefficient of thermal expansion and the stress of the through-silicon via are lowered and the thermal conductivity of the through-silicon via is increased.
摘要翻译：通过将高导热性和低热膨胀系数的颗粒作为复合材料添加到铜中，并将复合材料填充到通孔中，热膨胀系数与贯穿硅通孔的应力的失配是降低了通硅通孔的导热性。

9. 发明申请

US20120273939A1 FILLED THROUGH-SILICON VIA AND THE FABRICATION METHOD THEREOF 有权
标题翻译：通过硅填充硅及其制造方法
公开(公告)号：US20120273939A1
公开(公告)日：2012-11-01
申请号：US13174794
申请日：2011-07-01
申请人： Ming-Ji Dai , Heng-Chieh Chien , Ming-Che Hsieh , Jui-Feng Hung , Ra-Min Tain , John H. Lau
发明人： Ming-Ji Dai , Heng-Chieh Chien , Ming-Che Hsieh , Jui-Feng Hung , Ra-Min Tain , John H. Lau
IPC分类号： H01L23/48
CPC分类号： H01L21/76898 , H01L21/486 , H01L23/147 , H01L23/481 , H01L23/49827 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/11009 , H01L2224/13082 , H01L2224/13147 , H01L2224/13155 , H01L2224/14181 , H01L2224/16225 , H01L2224/94 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06572 , H01L2924/00014 , H01L2924/10253 , H01L2924/10329 , H01L2924/12042 , H01L2924/1421 , H01L2924/1434 , H01L2924/3511 , H01L2924/01046 , H01L2924/01079 , H01L2224/03 , H01L2224/11 , H01L2224/05552 , H01L2924/00
摘要： By adding particles of high thermal conductivity and low thermal expansion coefficient into the copper as a composite material and filling with the composite material into the through-via hole, the mismatch of the coefficient of thermal expansion and the stress of the through-silicon via are lowered and the thermal conductivity of the through-silicon via is increased.
摘要翻译：通过将高导热性和低热膨胀系数的颗粒作为复合材料添加到铜中，并将复合材料填充到通孔中，热膨胀系数与贯穿硅通孔的应力的失配是降低了通硅通孔的导热性。

10. 发明申请

US20120135547A1 FABRICATING METHOD AND TESTING METHOD OF SEMICONDUCTOR DEVICE AND MECHANICAL INTEGRITY TESTING APPARATUS 有权
标题翻译：半导体器件的制造方法和测试方法和机械完整性测试装置
公开(公告)号：US20120135547A1
公开(公告)日：2012-05-31
申请号：US13023545
申请日：2011-02-09
申请人： Ming-Che Hsieh , John H. Lau , Ra-Min Tain
发明人： Ming-Che Hsieh , John H. Lau , Ra-Min Tain
IPC分类号： H01L21/66 , G01N3/00 , G01N3/20
CPC分类号： H01L22/12 , G01N19/04 , H01L2224/16
摘要： A fabricating method and a testing method of a semiconductor device and a mechanical integrity testing apparatus are provided. An object includes a wafer, an insulating layer, and a plurality of conductive posts is provided. A surface of the wafer has a plurality of first blind holes outside chip regions and a plurality of second blind holes inside the chip regions. The insulating layer is between the conductive posts and the walls of the first blind holes and between the conductive posts and the walls of the second blind holes. A mechanical integrity test is performed to test a binding strength between the insulating layer, the conductive posts, and the walls of the first blind holes. The conductive posts in the chip regions are electrically connected to an element after the conductive posts in the first blind holes are qualified in the mechanical integrity test.
摘要翻译：提供了半导体器件和机械完整性测试装置的制造方法和测试方法。一种物体包括晶片，绝缘层和多个导电柱。晶片的表面在芯片区域外部具有多个第一盲孔和芯片区域内的多个第二盲孔。绝缘层位于导电柱和第一盲孔的壁之间以及导电柱和第二盲孔的壁之间。执行机械完整性测试以测试绝缘层，导电柱和第一盲孔的壁之间的结合强度。在机械完整性测试中，在第一盲孔中的导电柱合格之后，芯片区域中的导电柱电连接到元件。

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