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1. 发明申请

WO2009111175A1 ERROR DETECTION AND OFFSET CANCELLATION DURING MULTI-WIRE COMMUNICATION 审中-公开
标题翻译：多线通信期间的错误检测和偏移消除
公开(公告)号：WO2009111175A1
公开(公告)日：2009-09-11
申请号：PCT/US2009/034494
申请日：2009-02-19
申请人： RAMBUS INC. , KIZER, Jade, M. , WILSON, John , LUO, Lei , WARE, Frederick , ZERBE, Jared, L.
发明人： KIZER, Jade, M. , WILSON, John , LUO, Lei , WARE, Frederick , ZERBE, Jared, L.
IPC分类号： H04L25/49
CPC分类号： H03M13/47 , H04L25/4919
摘要： Embodiments of a circuit are described. In this circuit, a receive circuit includes M input nodes that receive a set of M symbols on M links during a time interval, where the set of M symbols are associated with a codeword. Moreover, the receive circuit includes a decoder, coupled to the M input nodes, that determines the codeword in a code space based on the set of M symbols and that decodes the codeword to a corresponding set of N decoded symbols. Additionally, the receive circuit may include a detector that detects an imbalance in a number of instances of a first value in the set of M symbols and a number of instances of a second value in the set of M symbols, and, if an imbalance is detected, that asserts an error condition.
摘要翻译：描述电路的实施例。在该电路中，接收电路包括M个输入节点，该输入节点在时间间隔期间在M个链路上接收一组M个符号，其中该M个符号集合与码字相关联。此外，接收电路包括耦合到M个输入节点的解码器，其基于该M个符号集来确定码空间中的码字，并且将码字解码为相应的一组N个解码符号。另外，接收电路可以包括检测器，其检测M个符号集合中的第一值的多个实例中的不平衡，以及M个符号集合中的第二值的多个实例，并且如果不平衡是检测到，这会导致错误条件。

2. 发明申请

WO2009086078A1 RECEIVER FOR MULTI-WIRE COMMUNICATION WITH REDUCED INPUT CAPACITANCE 审中-公开
标题翻译：接收器用于具有降低输入电容的多线通信
公开(公告)号：WO2009086078A1
公开(公告)日：2009-07-09
申请号：PCT/US2008/087639
申请日：2008-12-19
申请人： RAMBUS INC. , WARE, Frederick , WILSON, John , OH, Kyung Suk , LEIBOWITZ, Brian S. , KIZER, Jade M. , LUO, Lei
发明人： WARE, Frederick , WILSON, John , OH, Kyung Suk , LEIBOWITZ, Brian S. , KIZER, Jade M. , LUO, Lei
IPC分类号： G06F13/42 , H04L25/49
CPC分类号： G06F13/4243 , H04L25/4906 , Y02D10/14 , Y02D10/151
摘要： Embodiments of a device that receives and decodes a series of parallel symbol sets over a series of time intervals is described. In this device, symbols in a respective parallel symbol set are received on nodes. Each node receives a respective symbol, which can have one of two possible logical values ( e.g ., a logic 0 or a logic 1). Differential amplifiers in the device provide primary comparison results, each of which compares symbols received on pairs of the links, and generation circuits in the device provide secondary comparison results from the primary comparison results. A decoder in the device decodes a respective parallel symbol set from the primary and secondary comparison results to recover encoded data.
摘要翻译：描述了在一系列时间间隔内接收并解码一系列并行符号集的设备的实施例。在这个装置中，各个并行符号集中的符号在节点上被接收。每个节点接收相应的符号，该符号可以具有两个可能的逻辑值之一（例如，逻辑0或逻辑1）。设备中的差分放大器提供主要比较结果，每个比较结果比较在链路对上接收的符号，并且设备中的发生电路提供来自主要比较结果的次级比较结果。设备中的解码器从主要和次要比较结果解码相应的并行符号集以恢复编码数据。

3. 发明申请

WO2009086142A1 ASYMMETRIC COMMUNICATION ON SHARED LINKS 审中-公开
标题翻译：共享链接上的不对称通信
公开(公告)号：WO2009086142A1
公开(公告)日：2009-07-09
申请号：PCT/US2008/087743
申请日：2008-12-19
申请人： RAMBUS INC. , OH, Kyung Suk , WILSON, John , WARE, Frederick , KIM, WooPoung , KIZER, Jade M. , LEIBOWITZ, Brian S. , LUO, Lei , EBLE, John Cronan
发明人： OH, Kyung Suk , WILSON, John , WARE, Frederick , KIM, WooPoung , KIZER, Jade M. , LEIBOWITZ, Brian S. , LUO, Lei , EBLE, John Cronan
IPC分类号： G06F13/42 , H04L25/49
CPC分类号： G06F13/4243 , H04L25/4906 , Y02D10/14 , Y02D10/151
摘要： Embodiments of a system that communicates bidirectional data between two devices via shared links is described. In this system, data is transmitted on the shared links by one of the devices using single-ended drivers, and corresponding symbols are received on the shared links by the other device using differential comparison circuits. The data may be encoded as a series of parallel codewords prior to transmission. Each shared link may communicate a respective symbol in each codeword, which can have one of two possible logical values (e.g., a logic 0 or a logic 1). The corresponding symbols received by the other device may comprise a parallel symbol set, and each of the differential comparison circuits may compare symbols received on pairs of the shared links. A decoder in the other device may decode a respective parallel symbol set from the outputs of the differential comparison circuits to recover the encoded data.
摘要翻译：描述了经由共享链路在两个设备之间传递双向数据的系统的实施例。在这个系统中，数据通过使用单端驱动器的设备之一在共享链路上传输，并且相应的符号由另一个设备使用差分比较电路在共享链路上接收。数据可以在传输之前被编码为一系列并行码字。每个共享链路可以传送每个码字中的相应符号，其可以具有两个可能的逻辑值中的一个（例如，逻辑0或逻辑1）。由另一个设备接收到的对应符号可以包括并行符号集合，并且每个差分比较电路可以比较在共享链路对上接收到的符号。另一个设备中的解码器可以从差分比较电路的输出中解码相应的并行符号集合以恢复编码的数据。

4. 发明申请

WO2009055103A3 LOW-POWER SOURCE-SYNCHRONOUS SIGNALING 审中-公开
公开(公告)号：WO2009055103A3
公开(公告)日：2009-04-30
申请号：PCT/US2008/069250
申请日：2008-07-03
申请人： RAMBUS, INC. , ZERBE, Jared, L. , WARE, Frederick
发明人： ZERBE, Jared, L. , WARE, Frederick
IPC分类号： G06F13/42
摘要： Within a system of integrated circuit devices, first and second signals are transmitted intermittently from a first integrated circuit device to a second integrated circuit device. The second integrated circuit device generates a timing signal based on transitions of the second signal and generates samples of the first signal in response to transitions of the timing signal. The second integrated circuit device further generates timing error information based on the samples of the first signal, the timing error information to enable adjustment of the relative phases of the timing signal and the first signal.

5. 发明申请

WO2009032928A3 METHOD AND APPARATUS TO REPAIR DEFECTS IN NONVOLATILE SEMICONDUCTOR MEMORY DEVICES 审中-公开
公开(公告)号：WO2009032928A3
公开(公告)日：2009-03-12
申请号：PCT/US2008/075261
申请日：2008-09-04
申请人： RAMBUS INC. , BRONNER, Gary, B. , LI, Ming , MULLEN, Donald, R. , WARE, Frederick , DONNELLY, Kevin, S.
发明人： BRONNER, Gary, B. , LI, Ming , MULLEN, Donald, R. , WARE, Frederick , DONNELLY, Kevin, S.
IPC分类号： G11C16/34
摘要： A method of repairing a nonvolatile semiconductor memory device to eliminate defects includes monitoring a memory endurance indicator for a nonvolatile semiconductor memory device contained in a semiconductor package. It is determined whether that the memory endurance indicator exceeds a predefined limit. Finally, in response to determining that the memory endurance indicator exceeds the predefined limit, the device is annealed.

6. 发明申请

WO2009099788A2 MULTI-DROP SIGNALING SYSTEM AND METHOD EMPLOYING SOURCE-TERMINATION 审中-公开
标题翻译：多信号信号系统和使用源终止的方法
公开(公告)号：WO2009099788A2
公开(公告)日：2009-08-13
申请号：PCT/US2009/031985
申请日：2009-01-26
申请人： RAMBUS INC. , WARE, Frederick , STOTT, Bret G.
发明人： WARE, Frederick , STOTT, Bret G.
IPC分类号： G06F13/42
CPC分类号： G06F13/4239 , G06F13/1689 , Y02D10/14 , Y02D10/151
摘要： A signaling system employs parallel termination for a timing reference signal and series termination for information signals that may be sampled using the timing reference signal. In this way, the system may provide desired levels of signal performance and power consumption. In addition, the system may be configured such that the initial wavefronts of these signals may travel in opposite directions along complementary signaling paths. For example, a timing reference signal that travels from a driving device (e.g., a memory controller) to several destination devices (e.g., memory devices) in a multi-drop/fly-by fashion may arrive at the destination devices in a given order. In contrast, associated information signals may travel from the driving device to the destination devices such that they arrive at the destination devices in the opposite order.
摘要翻译：信令系统对于可以使用定时参考信号进行采样的信息信号采用并行终止用于定时参考信号和串行终止。以这种方式，系统可以提供期望的信号性能和功耗水平。此外，该系统可以被配置为使得这些信号的初始波前沿互补的信令路径沿相反的方向行进。例如，以多分支/飞行方式从驱动装置（例如，存储器控制器）行进到若干目的地装置（例如，存储装置）的定时参考信号可以以给定的顺序到达目的地装置。相比之下，相关的信息信号可以从驱动设备行进到目标设备，使得它们以相反的顺序到达目的地设备。

7. 发明申请

WO2010039365A1 SIGNAL CALIBRATION METHODS AND APPARATUSES 审中-公开
标题翻译：信号校准方法和装置
公开(公告)号：WO2010039365A1
公开(公告)日：2010-04-08
申请号：PCT/US2009/055106
申请日：2009-08-27
申请人： RAMBUS INC. , WARE, Frederick , NAVID, Reza , POULTON, John, W.
发明人： WARE, Frederick , NAVID, Reza , POULTON, John, W.
IPC分类号： H03L7/00 , H04L7/00
CPC分类号： H03L7/00
摘要： In a signal calibration scheme, a desired phase relationship is maintained between a set of signals. For example, in some aspects the desired phase of a clock tree generated from a high speed reference clock signal may be maintained by detecting phase differences between a low speed reference clock signal and low speed clock signals associated with different phases of the clock tree. In some aspects, the desired phase of a clock tree may be maintained by detecting framing offsets that occur through the use of the clock tree.
摘要翻译：在信号校准方案中，在一组信号之间保持期望的相位关系。例如，在一些方面，可以通过检测低速参考时钟信号和与时钟树的不同相位相关联的低速时钟信号之间的相位差来维持从高速参考时钟信号产生的时钟树的期望相位。在某些方面，通过检测通过使用时钟树发生的成帧偏移，可以维持时钟树的所需相位。

8. 发明申请

WO2009042329A2 RECONFIGURABLE MEMORY SYSTEM DATA STROBES 审中-公开
标题翻译：可重构存储器系统数据条
公开(公告)号：WO2009042329A2
公开(公告)日：2009-04-02
申请号：PCT/US2008/074247
申请日：2008-08-25
申请人： RAMBUS INC. , SHAEFFER, Ian , WARE, Frederick , HAMPEL, Craig E.
发明人： SHAEFFER, Ian , WARE, Frederick , HAMPEL, Craig E.
IPC分类号： G06F13/16
CPC分类号： G06F3/0634 , G06F3/0665 , G06F3/0689 , G06F13/1694 , G06F2212/262 , G11C7/22

9. 发明申请

WO2004077524A2 METHOD AND APPARATUS FOR TEST AND CHARACTERIZATION OF SEMICONDUCTOR COMPONENTS 审中-公开
标题翻译：半导体元件测试和表征的方法和装置
公开(公告)号：WO2004077524A2
公开(公告)日：2004-09-10
申请号：PCT/US2004/005620
申请日：2004-02-25
申请人： RAMBUS INCORPORATED , WARE, Frederick , BEST, Scott , CHANG, Timothy , PEREGO, Richard , TSERN, Ely , MITCHELL, Jeff
发明人： WARE, Frederick , BEST, Scott , CHANG, Timothy , PEREGO, Richard , TSERN, Ely , MITCHELL, Jeff
IPC分类号： H01L
CPC分类号： G11C29/56004 , G01R31/31707 , G06F11/24 , G11C2029/5602
摘要： A method and apparatus for testing and characterizing circuits is provided. In one embodiment, a high-speed interface of a semiconductor component includes high-speed test circuitry. The high-speed test circuitry obviates the need for an external high-speed testing system for testing and characterization. In one embodiment, the high-speed test circuitry includes a test pattern generation circuit, and various differential comparators to compare low bandwidth reference signals with interface signals during testing and characterization. In one embodiment, an interface that includes the test circuitry can test itself or another interface. In one embodiment, a timing reference signal decouples the individual parameters of two interfaces testing each other to avoid any errors introduced by the combination of individual interface circuit parameters, such as receiver parameters and transmitter parameters. The testing can be performed at the wafer stage, at the component stage, and in a system.
摘要翻译：提供了用于测试和表征电路的方法和装置。在一个实施例中，半导体部件的高速接口包括高速测试电路。高速测试电路无需外部高速测试系统进行测试和表征。在一个实施例中，高速测试电路包括测试图形生成电路和各种差分比较器，用于在测试和表征期间将低带宽参考信号与接口信号进行比较。在一个实施例中，包括测试电路的接口可以测试自身或另一接口。在一个实施例中，定时参考信号使彼此测试的两个接口的各个参数解耦，以避免由诸如接收机参数和发射机参数的各个接口电路参数的组合引入的任何错误。测试可以在晶片级，元件级和系统中执行。

10. 发明申请

WO2020190841A1 SYSTEM APPLICATION OF DRAM COMPONENT WITH CACHE MODE 审中-公开
公开(公告)号：WO2020190841A1
公开(公告)日：2020-09-24
申请号：PCT/US2020/022907
申请日：2020-03-16
申请人： RAMBUS INC.
发明人： WARE, Frederick , VOGELSANG, Thomas , MILLER, Michael , WILLIAMS, Collins
IPC分类号： G06F12/08
摘要： Disclosed is a memory system that has a memory controller and may have a memory component. The memory component may be a dynamic random access memory (DRAM). The memory controller is connectable to the memory component. The memory component has at least one data row and at least one tag row different from and associated with the at least one data row. The memory system is to implement a cache having multiple ways to hold a data group. The memory controller is operable in each of a plurality of operating modes. The operating modes include a first operating mode and a second operating mode. The first operating mode and the second operating mode have differing addressing and timing for accessing the data group. The memory controller has cache read logic that sends a cache read command, cache results logic that receives a response from the memory component, and cache fetch logic.

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