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1. 发明申请

WO2009032928A3 METHOD AND APPARATUS TO REPAIR DEFECTS IN NONVOLATILE SEMICONDUCTOR MEMORY DEVICES 审中-公开
公开(公告)号：WO2009032928A3
公开(公告)日：2009-03-12
申请号：PCT/US2008/075261
申请日：2008-09-04
申请人： RAMBUS INC. , BRONNER, Gary, B. , LI, Ming , MULLEN, Donald, R. , WARE, Frederick , DONNELLY, Kevin, S.
发明人： BRONNER, Gary, B. , LI, Ming , MULLEN, Donald, R. , WARE, Frederick , DONNELLY, Kevin, S.
IPC分类号： G11C16/34
摘要： A method of repairing a nonvolatile semiconductor memory device to eliminate defects includes monitoring a memory endurance indicator for a nonvolatile semiconductor memory device contained in a semiconductor package. It is determined whether that the memory endurance indicator exceeds a predefined limit. Finally, in response to determining that the memory endurance indicator exceeds the predefined limit, the device is annealed.

2. 发明申请

WO2006088609A3 SEMICONDUCTOR PACKAGE WITH LOW AND HIGH-SPEED SIGNAL PATHS 审中-公开
公开(公告)号：WO2006088609A3
公开(公告)日：2006-08-24
申请号：PCT/US2006/002131
申请日：2006-01-19
申请人： RAMBUS INC. , LI, Ming , KHALILI, Sayeh , MULLEN, Donald, R.
发明人： LI, Ming , KHALILI, Sayeh , MULLEN, Donald, R.
IPC分类号： H01L23/498
摘要： The semiconductor package includes two electrical contacts and a semiconductor device coupled to opposing sides of a substrate. The substrate defines at least one via extending at least partially there through. The semiconductor device includes a semiconductor low-speed interface electrically coupled to one of the electrical contacts through the via, and a semiconductor high-speed interface electrically coupled to flexible tape. The flexible tape is also electrically coupled to the other one of the electrical contacts.

3. 发明申请

WO2011017202A2 PACKAGED SEMICONDUCTOR DEVICE FOR HIGH PERFORMANCE MEMORY AND LOGIC 审中-公开
标题翻译：用于高性能存储器和逻辑的封装半导体器件
公开(公告)号：WO2011017202A2
公开(公告)日：2011-02-10
申请号：PCT/US2010/043788
申请日：2010-07-29
申请人： RAMBUS INC. , LI, Ming
发明人： LI, Ming
IPC分类号： H01L23/48 , H01L23/12 , H01L23/52
CPC分类号： H01L23/49827 , H01L23/13 , H01L23/36 , H01L23/49822 , H01L24/48 , H01L24/73 , H01L25/18 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/06517 , H01L2225/06565 , H01L2225/06572 , H01L2225/06589 , H01L2924/00014 , H01L2924/14 , H01L2924/1433 , H01L2924/15153 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/181 , H01L2924/3011 , H01L2924/00012 , H01L2924/00 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A packaged semiconductor device is disclosed. The device comprises a substrate having multiple layers between first and second oppositely disposed faces, and a cavity with an opening at the first face to nest at least one integrated circuit memory device. Logic circuitry is disposed on the second face and includes contacts for electrically coupling to the stacked integrated circuit memory devices. The logic circuitry is coupled to electrical contacts formed on the first face through first electrical paths formed in the multiple layers of the substrate, the first electrical paths including conductive traces and vias.
摘要翻译：公开了一种封装半导体器件。该装置包括在第一和第二相对布置的面之间具有多个层的衬底以及在第一面处具有开口以嵌套至少一个集成电路存储器件的空腔。逻辑电路设置在第二面上，并且包括用于电耦合到堆叠集成电路存储器件的触点。逻辑电路通过形成在衬底的多层中的第一电路连接到形成在第一面上的电触头，第一电路包括导电迹线和通孔。

4. 发明申请

WO2006107365A3 HEAT SINK FOR MULTIPLE SEMICONDUCTOR MODULES 审中-公开
公开(公告)号：WO2006107365A3
公开(公告)日：2006-10-12
申请号：PCT/US2006/001591
申请日：2006-01-13
申请人： RAMBUS INC. , LI, Ming
发明人： LI, Ming
IPC分类号： G06F1/20 , H01L23/36 , H05K7/20
摘要： A system for dissipating heat away from multiple semiconductor modules includes a thermal conductor having a thermally conductive base and multiple thermally conductive semiconductor module connectors thermally coupled to the base. Each of the semiconductor module connectors is configured to connect to a different semiconductor module of multiple semiconductor modules.

5. 发明申请

WO2008103752A1 HIGH-SPEED MEMORY PACKAGE 审中-公开
标题翻译：高速存储器包
公开(公告)号：WO2008103752A1
公开(公告)日：2008-08-28
申请号：PCT/US2008/054455
申请日：2008-02-20
申请人： RAMBUS INC. , LI, Ming
发明人： LI, Ming
IPC分类号： H01L23/60
CPC分类号： H01L23/552 , H01L23/49838 , H01L2224/0554 , H01L2224/05567 , H01L2224/05573 , H01L2224/11015 , H01L2224/11334 , H01L2924/00014 , H01L2924/3011 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： The semiconductor package includes a dielectric layer, a trace layer, a conductive layer, a die and an underfill layer. The dielectric layer has first side and an opposing dielectric layer second side. Multiple vias extend through the dielectric layer from the dielectric layer first side to the dielectric layer second side. Multiple solder balls are disposed at the dielectric layer second side. Each of the solder balls is electrically coupled to a different one of the vias. The die is electrically coupled to the solder balls. The conductive layer is disposed between the dielectric layer second side and the die. The conductive layer defines a window there through for allowing the solder balls to electrically couple to the vias without contacting the conductive layer, i.e., no physical or electrical contact. The underfill layer is formed between the die and the conductive layer, while the trace layer is formed at the dielectric layer first side. Traces of the trace layer electrically couple the vias to other solder balls.
摘要翻译：半导体封装包括电介质层，迹线层，导电层，管芯和底部填充层。电介质层具有第一侧和相对的电介质层第二侧。多个通孔从电介质层第一侧延伸到电介质层第二侧。在电介质层第二侧设置多个焊球。每个焊球电耦合到不同的一个通孔。模具电耦合到焊球。导电层设置在电介质层第二侧和管芯之间。导电层在其上限定了一个窗口，以允许焊球电气耦合到通孔而不接触导电层，即没有物理或电接触。在芯片和导电层之间形成底部填充层，同时在电介质层第一侧形成迹线层。痕迹层的迹线将通孔电耦合到其他焊球。

6. 发明申请

WO2009029335A1 DETACHABLE INTERCONNECT FOR CONFIGURABLE WIDTH MEMORY SYSTEM 审中-公开
标题翻译：可配置的宽度存储器系统的可互连的互连
公开(公告)号：WO2009029335A1
公开(公告)日：2009-03-05
申请号：PCT/US2008/068822
申请日：2008-06-30
申请人： RAMBUS INC. , KOLLIPARA, Ravindranath , YUAN, Xingchao , LAMBRECHT, Frank , LI, Ming , PEREGO, Richard E. , LIN, Qi , NGUYEN, David , OH, Kyung Suk
发明人： KOLLIPARA, Ravindranath , YUAN, Xingchao , LAMBRECHT, Frank , LI, Ming , PEREGO, Richard E. , LIN, Qi , NGUYEN, David , OH, Kyung Suk
IPC分类号： G06F13/16 , H01L25/10 , H05K1/00
CPC分类号： G06F13/1668 , H01L2224/16225 , H01L2924/15174 , H01L2924/15311 , H05K1/0237 , H05K1/0295 , H05K1/14 , H05K1/141 , H05K1/147 , H05K3/222 , H05K2201/044 , H05K2201/09954 , H05K2201/10159 , H05K2201/10356
摘要： The disclosure relates to a detachable signalling interconnect apparatus that provides connectivity between two or more components of a memory system in conjunction with different modes of operation of the components. The memory system comprises: a first socket to receive a first memory module; a second socket to receive a second memory module; a detachable signal-interconnect; and a memory controller coupled to the detachable signal-interconnect and configured to define a first mode of operation and a second mode of operation, wherein in the first mode of operation the detachable signal-interconnect is to couple the memory- controller to the first memory module and in the second mode of operation the detachable signal-interconnect is to couple the memory controller to the first memory module and the second memory module.
摘要翻译：本公开涉及一种可拆卸信令互连装置，其提供存储器系统的两个或更多个组件与组件的不同操作模式之间的连接。存储器系统包括：第一插座，用于接收第一存储器模块; 用于接收第二存储器模块的第二插座; 可拆卸的信号互连; 以及存储器控制器，其耦合到所述可拆卸信号互连并且被配置为限定第一操作模式和第二操作模式，其中在所述第一操作模式中，所述可拆卸信号互连将所述存储器控制器耦合到所述第一存储器模块，并且在第二操作模式中，可拆卸信号互连将存储器控制器耦合到第一存储器模块和第二存储器模块。

7. 发明申请

WO2008076790A2 MULTI-DIE MEMORY DEVICE 审中-公开
标题翻译：多芯片存储器件
公开(公告)号：WO2008076790A2
公开(公告)日：2008-06-26
申请号：PCT/US2007/087359
申请日：2007-12-13
申请人： RAMBUS INC. , BEST, Scott , LI, Ming
发明人： BEST, Scott , LI, Ming
IPC分类号： G11C5/02
CPC分类号： G11C11/4093 , G11C5/02 , G11C5/025 , G11C5/04 , G11C11/4096 , H01L23/481 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/0401 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/0652 , H01L2225/06541 , H01L2225/06558 , H01L2225/06562 , H01L2225/1023 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/01055 , H01L2924/14 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/3011 , H01L2924/00012 , H01L2924/00
摘要： An integrated circuit (IC) package includes an interface die and a separate storage die. The interface die has a synchronous interface to receive memory access commands from an external memory controller, and has a plurality of clockless memory control interfaces to output row and column control signals that correspond to the memory access commands. The storage die has a plurality of independently accessible storage arrays and corresponding access-control interfaces to receive the row and column control signals from the clockless memory control interfaces, each of the access-control interfaces including data output circuitry to output read data corresponding to a given one of the memory access commands in a time-multiplexed transmission.
摘要翻译：集成电路（IC）封装包括接口管芯和单独的存储管芯。接口管芯具有用于从外部存储器控制器接收存储器访问命令的同步接口，并且具有多个无时钟存储器控制接口以输出对应于存储器访问命令的行和列控制信号。存储管芯具有多个可独立存取的存储阵列和相应的访问控制接口，用于接收来自无时钟存储器控制接口的行和列控制信号，每个访问控制接口包括数据输出电路，以输出对应于给定时间复用传输中的一个存储器访问命令。

8. 发明公开

EP0883837A1 AN OPTICAL ARRANGEMENT FOR PROCESSING AN OPTICAL WAVE 失效
标题翻译：光学装置用于处理光学波动
公开(公告)号：EP0883837A1
公开(公告)日：1998-12-16
申请号：EP97906404.0
申请日：1997-02-27
申请人： Hagberg, Mats , Li, Ming , Larsson, Anders
发明人： LI, Ming , LARSSON, Anders
IPC分类号： G02B6 , G02B5 , G03H1
CPC分类号： G02B6/4246 , G02B6/124 , G02B6/2848 , G03H1/0244 , G03H1/0841 , G03H1/26 , G03H2001/085 , G03H2001/2226 , G03H2223/16 , G03H2240/10 , G03H2240/13 , G03H2240/41 , G03H2240/43
摘要： The invention relates to an optical arrangement and a method for processing an optical wave, comprising a plurality of cells (20, 21) arranged on, into or partly into an optical medium, wherein the cells having a pattern structure formed therein. The pattern structure in each of the cells comprises a plurality of grooves (30). The grooves (30) in at least one of the cells (20, 21) are parallel to each other, and the grooves (30) form a grating (40).

9. 发明授权

EP0883837B1 AN OPTICAL ARRANGEMENT FOR PROCESSING AN OPTICAL WAVE 失效
标题翻译：光学装置用于处理光学波动
公开(公告)号：EP0883837B1
公开(公告)日：2006-07-12
申请号：EP97906404.5
申请日：1997-02-27
申请人： Hagberg, Mats , Li, Ming , Larsson, Anders
发明人： LI, Ming , LARSSON, Anders
IPC分类号： G03H1/08 , G02B5/32
CPC分类号： G02B6/4246 , G02B6/124 , G02B6/2848 , G03H1/0244 , G03H1/0841 , G03H1/26 , G03H2001/085 , G03H2001/2226 , G03H2223/16 , G03H2240/10 , G03H2240/13 , G03H2240/41 , G03H2240/43
摘要： The invention relates to an optical arrangement and a method for processing an optical wave, comprising a plurality of cells (20, 21) arranged on, into or partly into an optical medium, wherein the cells having a pattern structure formed therein. The pattern structure in each of the cells comprises a plurality of grooves (30). The grooves (30) in at least one of the cells (20, 21) are parallel to each other, and the grooves (30) form a grating (40).

10. 发明申请

WO2023028765A1 APPARATUS FOR PROVIDING THERMAL MANAGEMENT AND ELECTROMAGNETIC INTERFERENCE SHIELDING 审中-公开
公开(公告)号：WO2023028765A1
公开(公告)日：2023-03-09
申请号：PCT/CN2021/115390
申请日：2021-08-30
申请人： THOMSON LICENSING , ZHAO, Lizhi , LI, Ming
发明人： ZHAO, Lizhi , LI, Ming
IPC分类号： H05K7/20 , H05K9/00
摘要： An apparatus is described. The apparatus includes a shield enclosing a component attached to a circuit board and having an inner surface and outer surface, the component having an outer surface aligned in parallel with the shield inner surface of the shield, the shield including at least one opening extending through the shield from the outer surface to the inner surface and aligned with the component. The apparatus includes a heatsink positioned adjacent to the outer surface of the shield and aligned with the component, the heatsink thermally coupled to the outer surface of the component using flowable thermally conductive material that extends through the opening (s) and occupies a space between the outer surface of the component and the shield inner surface and a space between the shield outer surface and a surface of the heatsink. The apparatus may be assembled and used as part of an electronic device.

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