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1. 发明申请

WO2006078845A3 HIGH-SPEED SIGNALING SYSTEMS WITH ADAPTABLE PRE-EMPHASIS AND EQUALIZATION 审中-公开
标题翻译：具有适应性前瞻性和均衡性的高速信号系统
公开(公告)号：WO2006078845A3
公开(公告)日：2007-02-15
申请号：PCT/US2006001944
申请日：2006-01-20
申请人： RAMBUS INC , ZERBE JARED L , CHEN FRED F , HO ANDREW , FARJAD-RAD RAMIN , POULTON JOHN W , DONNELLY KEVIN S , LEBOWITZ BRIAN
发明人： ZERBE JARED L , CHEN FRED F , HO ANDREW , FARJAD-RAD RAMIN , POULTON JOHN W , DONNELLY KEVIN S , LEBOWITZ BRIAN
IPC分类号： H04L25/03
CPC分类号： H04L27/01 , H04L1/0026 , H04L7/0025 , H04L7/0087 , H04L7/0337 , H04L25/0272 , H04L25/028 , H04L25/03057 , H04L25/03343 , H04L25/03885 , H04L25/497 , H04L2025/03503 , H04W52/20 , H04W52/225 , Y02B60/50
摘要： A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.
摘要翻译：一个信令系统包括一个预先强调的发射机和一个通过高速信号路径相互耦合的均衡接收机。接收机测量从发射机传送的数据的质量。控制器使用该信息和其他信息来自适应地建立适当的发送预加重和接收均衡设置，例如，选择信令系统提供一些最小通信带宽而不超过所需误码率的最低功率设置。

2. 发明申请

WO2007016274A2 RAM-DAC FOR TRANSMIT PREEMPHASIS 审中-公开
标题翻译：用于传输预留的RAM-DAC
公开(公告)号：WO2007016274A2
公开(公告)日：2007-02-08
申请号：PCT/US2006029241
申请日：2006-07-25
申请人： RAMBUS INC , HO ANDREW , CHEN FRED F , ZERBE JARED L
发明人： HO ANDREW , CHEN FRED F , ZERBE JARED L
IPC分类号： H04L25/03
CPC分类号： H04L25/03834 , H03H17/0294
摘要： Described are transmitters with RAM-DAC based pre-emphasis filters that can be updated adaptively without interfering with data transmission. The memory within the RAM- DAC is divided into active and inactive memory locations, in which active memory locations are those to be accessed in the near future, and consequently cannot be updated (written to) at a given time due without inducing a read/write conflict. One embodiment monitors incoming memory addresses to find an adequate time window for a write to take place without a read interference. Another embodiment includes two memory blocks with similar address space, one of which may be updated as the other is used to for data transmission. Some embodiments employ a RAM-DAC with reduced memory size and complexity.
摘要翻译：描述的是具有基于RAM-DAC的预加重滤波器的发射器，其可以自适应地更新而不干扰数据传输。 RAM-DAC内的存储器被分为有源和非活动存储器位置，其中有效存储器位置是在不久的将来被访问的存储器位置，因此不能在给定时间更新（写入），而不引起读/ 写冲突。一个实施例监视进入的存储器地址以找到足够的时间窗口，以便在没有读取干扰的情况下进行写入。另一个实施例包括具有相似地址空间的两个存储器块，其中之一可以被更新，而另一个用于数据传输。一些实施例采用具有减小的存储器大小和复杂度的RAM-DAC。

3. 发明申请

WO2005046156A2 TRANSPARENT MULTI-MODE PAM INTERFACE 审中-公开
标题翻译：透明多模式接口
公开(公告)号：WO2005046156A2
公开(公告)日：2005-05-19
申请号：PCT/US2004035990
申请日：2004-10-26
申请人： RAMBUS INC , ZERBE JARED L , WERNER CARL W , STONECYPHER WILLIAM F , CHEN FRED F
发明人： ZERBE JARED L , WERNER CARL W , STONECYPHER WILLIAM F , CHEN FRED F
IPC分类号： H04L1/00 , H04L5/14 , H04L25/02 , H04L25/03 , H04L25/49 , H04L27/08 , H04L27/32
CPC分类号： H04L27/08 , H04L1/0003 , H04L5/1438 , H04L25/028 , H04L25/0292 , H04L25/4917 , H04L2025/03585
摘要： Provided are a method and apparatus for high-speed, multi-mode PAM symbol transmission. A multi-mode PAM output driver drives one or more symbols, the number of levels used in the PAM modulation of the one or more symbols depending on the state of a PAM mode signal. Additionally, the one or more symbols are driven at a symbol rate, the symbol rate selected in accordance with the PAM mode signal so that a data rate of the driven symbols in constant with respect to changes in the state of the PAM mode signal. Further provided are methods for determining the optimal number of PAM levels for symbol transmission and reception in a given physical environment.
摘要翻译：提供了一种用于高速，多模式PAM符号传输的方法和装置。多模式PAM输出驱动器根据PAM模式信号的状态驱动一个或多个符号，用于一个或多个符号的PAM调制中使用的级别数。另外，一个或多个符号以符号率被驱动，符号速率是根据PAM模式信号选择的符号速率，使得驱动符号的数据速率相对于PAM模式信号的状态的变化是恒定的。还提供了用于在给定物理环境中确定用于符号传输和接收的PAM最优数量的方法。

4. 发明申请

WO2004093144A3 PARTIAL RESPONSE RECEIVER 审中-公开
标题翻译：部分响应接收者
公开(公告)号：WO2004093144A3
公开(公告)日：2006-10-12
申请号：PCT/US2004010980
申请日：2004-04-09
申请人： RAMBUS INC , STOJANOVIC VLADIMIR M , HOROWITZ MARK A , ZERBE JARED L , BESSIOS ANTHONY , HO ANDREW C C , WEI JASON C , TSANG GRACE , GARLEPP BRUNO W
发明人： STOJANOVIC VLADIMIR M , HOROWITZ MARK A , ZERBE JARED L , BESSIOS ANTHONY , HO ANDREW C C , WEI JASON C , TSANG GRACE , GARLEPP BRUNO W
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159 , H04L25/06 , H04L25/497
CPC分类号： H04L25/03057 , H04L7/0276 , H04L25/063 , H04L25/497 , H04L2025/03369 , H04L2025/03503
摘要： A receive circuit for receiving a signal transmitted via an electrical signal conductor. A first sampling circuit generates a first sample value that indicates whether the signal exceeds a first threshold level, and a second sampling circuit generates a second sample value that indicates whether the signal exceeds a second threshold level. A first select circuit receives the first and second sample values from the first and second sampling circuits and selects, according to a previously generated sample value, either the first sample value or the second sample value to be output as a selected sample value.
摘要翻译：用于接收通过电信号导体发送的信号的接收电路。第一采样电路产生指示信号是否超过第一阈值电平的第一采样值，并且第二采样电路产生指示信号是否超过第二阈值电平的第二采样值。第一选择电路从第一和第二采样电路接收第一和第二采样值，并根据先前产生的采样值选择作为选择的采样值输出的第一采样值或第二采样值。

5. 发明申请

WO2012064537A3 USING A STUTTERED CLOCK SIGNAL TO REDUCE SELF-INDUCED VOLTAGE NOISE 审中-公开
标题翻译：使用时钟信号来减少自感电压噪声
公开(公告)号：WO2012064537A3
公开(公告)日：2012-07-12
申请号：PCT/US2011058525
申请日：2011-10-31
申请人： RAMBUS INC , LEIBOWITZ BRIAN S , ZERBE JARED L
发明人： LEIBOWITZ BRIAN S , ZERBE JARED L
IPC分类号： G06F1/04 , G06F1/32 , H03K19/0175
CPC分类号： G06F1/12 , G06F1/08 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： The disclosed embodiments relate to a technique that uses a modified timing signal to reduce self-induced voltage noise in a synchronous system. During a transient period associated with a deterministic event in the synchronous system, the technique uses a modified timing signal generated based on a normal timing signal as a timing signal for the synchronous system. Outside of the transient period, the technique uses the normal timing as the timing signal for the synchronous system. In some embodiments, the modified timing signal is generated by skipping a pattern of clock transitions in the normal timing signal.
摘要翻译：所公开的实施例涉及使用修改的时序信号来减少同步系统中的自感应电压噪声的技术。在与同步系统中的确定性事件相关联的过渡时段期间，该技术使用基于正常定时信号生成的修改定时信号作为同步系统的定时信号。在瞬态时段之外，该技术使用正常时序作为同步系统的时序信号。在一些实施例中，通过跳过正常定时信号中的时钟转变的模式来生成修改的定时信号。

6. 发明申请

WO2010078384A3 METHOD AND APPARATUS FOR CORRECTING PHASE ERRORS DURING TRANSIENT EVENTS IN HIGH-SPEED SIGNALING SYSTEMS 审中-公开
标题翻译：用于在高速信号系统中的瞬态事件中校正相位误差的方法和装置
公开(公告)号：WO2010078384A3
公开(公告)日：2010-09-16
申请号：PCT/US2009069760
申请日：2009-12-29
申请人： RAMBUS INC , ZERBE JARED L
发明人： ZERBE JARED L
IPC分类号： H04L7/033 , H04L27/18
CPC分类号： H04L7/0083 , H03L7/07 , H03L7/0807 , H03L7/0814 , H04L7/0008
摘要： A system for dynamically correcting phase errors between data and a timing reference signal caused by a transient event during data communication between a transmitter and a receiver is described. During operation, the system stores one or more phase-offset values for the event in an offset table, wherein the constituent phase-offset values are associated with phase error caused by the event. Upon detecting a subsequent occurrence of the event, the system adjusts a phase relationship between the data and the timing reference signal based on the one or more phase-offset values.
摘要翻译：描述了用于在发射机和接收机之间的数据通信期间动态地校正由数据通信期间的瞬态事件引起的数据与定时参考信号之间的相位误差的系统。在操作期间，系统将一个或多个相位偏移值存储在偏移表中，其中组成相位偏移值与由事件引起的相位误差相关联。在检测到事件的后续发生时，系统基于一个或多个相位偏移值来调整数据和定时参考信号之间的相位关系。

7. 发明申请

WO2007024446A3 LINEAR TRANSFORMATION CIRCUITS 审中-公开
标题翻译：线性变换电路
公开(公告)号：WO2007024446A3
公开(公告)日：2008-09-18
申请号：PCT/US2006030411
申请日：2006-08-02
申请人： RAMBUS INC , AMIRKHANY AMIR , STOJANOVIC VLADIMIR M , ALON ELAD , ZERBE JARED L , HOROWITZ MARK A
发明人： AMIRKHANY AMIR , STOJANOVIC VLADIMIR M , ALON ELAD , ZERBE JARED L , HOROWITZ MARK A
IPC分类号： G06J1/00 , G06F17/14
CPC分类号： G06F17/141 , G06J1/005
摘要： A transform circuit includes a first circuit and a second circuit. The first circuit and the second circuit implement first and second mappings that together generate a pre-defined transform of N digital data symbols. The first circuit maps a set of N digital data symbols from N parallel data streams to N analog data symbols by generating N sets of first weighted sums of the N digital data symbols. Each respective first weighted sum is defined by a respective set of pre-determined first weighting values in a first matrix. The second circuit maps the N analog data symbols to a sequence of N output signals over N time intervals. Each of the N output signals corresponds to a respective second weighted sum of the N analog data symbols. Each respective second weighted sum is defined by a respective set of pre-determined second weighting values in a second matrix.
摘要翻译：变换电路包括第一电路和第二电路。第一电路和第二电路实现一起产生N个数字数据符号的预定义变换的第一和第二映射。第一电路通过产生N个数字数据符号的第一加权和的N组，将来自N个并行数据流的一组N个数字数据符号映射到N个模拟数据符号。每个相应的第一加权和由第一矩阵中的预定的第一加权值的相应集合来定义。第二电路在N个时间间隔内将N个模拟数据符号映射到N个输出信号的序列。 N个输出信号中的每一个对应于N个模拟数据符号的相应的第二加权和。每个相应的第二加权和由第二矩阵中的预定的第二加权值的相应集合来定义。

8. 发明申请

WO2008070138A9 METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN TRANSCEIVER DEVICES 审中-公开
标题翻译：收发器设备之间信道均衡不对称分布的方法和电路
公开(公告)号：WO2008070138A9
公开(公告)日：2009-03-05
申请号：PCT/US2007024948
申请日：2007-12-05
申请人： RAMBUS INC , ZERBE JARED L , ASSADERAGHI FARIBORZ , LEIBOWITZ BRIAN S , LEE HAE-CHANG , REN JIHONG , LIN QI
发明人： ZERBE JARED L , ASSADERAGHI FARIBORZ , LEIBOWITZ BRIAN S , LEE HAE-CHANG , REN JIHONG , LIN QI
IPC分类号： H04L25/03
CPC分类号： H04L25/03343 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03433 , H04L2025/03617
摘要： A transceiver architecture supports high-speed communication over a signal lane (120-125) that extends between a high-performance integrated circuit (IC) (105) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers (110). The. architecture compensates for performance asymmetry between ICs communicating over a bidirectional lan by instantiating relatively complex transmit (Tx1) and receive (Rx1) equalization cir.cuitry on the higher-performance, side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated (162) based upon the signal response at the receiver of the higher-performance IC (Rx1N).
摘要翻译：收发机体系结构支持在高性能集成电路（IC）（105）和采用较不复杂的发射机和接收机（110）的一个或多个相对低性能的IC之间延伸的信号通道（120-125）上的高速通信。。的。通过在更高性能的通道侧实例化相对复杂的发送（Tx1）和接收（Rx1）均衡电路，体系结构补偿了通过双向lan进行通信的IC之间的性能不对称。基于在更高性能IC（Rx1N）的接收机处的信号响应，高性能IC中的发射和接收均衡滤波器系数都可以自适应地更新（162）。

9. 发明申请

WO2008070138A3 METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN TRANSCEIVER DEVICES 审中-公开
标题翻译：收发器之间通道均衡化的不对称分配方法与电路
公开(公告)号：WO2008070138A3
公开(公告)日：2009-01-15
申请号：PCT/US2007024948
申请日：2007-12-05
申请人： RAMBUS INC , ZERBE JARED L , ASSADERAGHI FARIBORZ , LEIBOWITZ BRIAN S , LEE HAE-CHANG , REN JIHONG , LIN QI
发明人： ZERBE JARED L , ASSADERAGHI FARIBORZ , LEIBOWITZ BRIAN S , LEE HAE-CHANG , REN JIHONG , LIN QI
IPC分类号： H04L25/03
CPC分类号： H04L25/03343 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03433 , H04L2025/03617
摘要： A transceiver architecture supports high-speed communication over a signal lane (120-125) that extends between a high-performance integrated circuit (IC) (105) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers (110). The. architecture compensates for performance asymmetry between ICs communicating over a bidirectional lan by instantiating relatively complex transmit (Tx1) and receive (Rx1) equalization cir.cuitry on the higher-performance, side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated (162) based upon the signal response at the receiver of the higher-performance IC (Rx1N).
摘要翻译：收发器架构支持在高性能集成电路（IC）（105）和使用较不复杂的发送器和接收器（110）的一个或多个相对低性能的IC之间延伸的信号通道（120-125）上的高速通信，。的。架构通过在车道的较高性能侧实例化相对复杂的发送（Tx1）和接收（Rx1）均衡电路来补偿通过双向LAN通信的IC之间的性能不对称性。基于在高性能IC（Rx1N）的接收机处的信号响应，可以自适应地更新（162）高性能IC中的发射和接收均衡滤波器系数。

10. 发明申请

WO2013006231A3 LOW-LATENCY, FREQUENCY-AGILE CLOCK MULTIPLIER 审中-公开
标题翻译：低延迟，频率敏捷的时钟倍频器
公开(公告)号：WO2013006231A3
公开(公告)日：2013-04-04
申请号：PCT/US2012039268
申请日：2012-05-24
申请人： RAMBUS INC , ZERBE JARED L , LEIBOWITZ BRIAN S , HOSSAIN MASUM
发明人： ZERBE JARED L , LEIBOWITZ BRIAN S , HOSSAIN MASUM
IPC分类号： H03K5/00 , H03B19/00
CPC分类号： H03L7/16 , H03J2200/10 , H03K3/0315 , H03K5/00006 , H03K5/13 , H03K5/14 , H03L7/06 , H03L7/0995 , H03L7/24
摘要： In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally- staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
摘要翻译：在第一时钟倍频器中，并行操作具有光谱交错锁定范围的多个注入锁定振荡器（ILO），以实现比单独ILO的集中输入频率范围宽得多的集中输入频率范围。在每个输入频率改变之后，可以根据一个或多个合格标准评估ILO输出时钟，以选择ILO中的一个作为最终时钟源。在第二个时钟倍频器中，柔性注入速率注入锁定振荡器锁定超级谐波，次谐波或频率注入脉冲，在不同的注入脉冲速率之间无缝切换，以实现宽泛的输入频率范围。由第一和/或第二时钟倍频器响应于输入时钟而实现的倍频因子被实时确定，然后与编程的（期望的）倍增因子进行比较以在倍频的不同分频实例之间进行选择时钟。

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