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1. 发明专利

JP2006060842A Delay-locked loop 有权
标题翻译：延迟锁定
公开(公告)号：JP2006060842A
公开(公告)日：2006-03-02
申请号：JP2005253696
申请日：2005-09-01
申请人： Rambus Inc , ラムバス・インコーポレーテッド
发明人： LEE THOMAS H , DONNELLY KEVIN S , HO TSYR-CHYANG , JOHNSON MARK G
IPC分类号： G01R31/28 , H03L7/081 , H03L7/00 , H03L7/08 , H03L7/093 , H04L7/033
CPC分类号： H03L7/0812
摘要： PROBLEM TO BE SOLVED: To provide a delay locked loop in which a voltage controlled oscillator (VCO) is obviated, power supply induction jitter is speedily obtained and suppressed to a minimum and a phase shift range is not limited. SOLUTION: The output of a phase comparator drives a differential charge pump which functions to integrate a phase comparator output signal over time. The charge pump output controls a phase shifter with unlimited range that adjusts the phase of the DLL output so that the output of the phase comparator is high 50% of the time on average. Because the DLL adjusts the phase shifter until the output of the phase detector is high 50% of the time, on average, the relationship of the DLL output clock to the input reference clock depends only on the type of phase detector used. Furthermore, the DLL is controlled to minimize dither jitter while minimizing acquisition time. In addition, duty cycle correcting amplifiers are employed to produce a DLL output clock that has a desired duty cycle, for example 50%. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供消除压控振荡器（VCO）的延迟锁定环路，快速获得电源感应抖动并将其抑制到最小，相移范围不受限制。
解决方案：相位比较器的输出驱动差分电荷泵，其功能是使相位比较器输出信号随时间积分。电荷泵输出控制无限幅度的移相器，可调节DLL输出的相位，使相位比较器的输出平均高达50％的时间。因为DLL调整移相器直到相位检测器的输出高达50％的时间，平均而言，DLL输出时钟与输入参考时钟的关系仅取决于所使用的相位检测器的类型。此外，DLL被控制以最小化抖动抖动，同时最小化采集时间。此外，采用占空比校正放大器来产生具有期望占空比的DLL输出时钟，例如50％。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

DE69840350D1 未知
公开(公告)号：DE69840350D1
公开(公告)日：2009-01-22
申请号：DE69840350
申请日：1998-02-04
申请人： RAMBUS INC
发明人： DONNELLY KEVIN S , CHAU PAK SHING , HOROWITZ MARK A , LEE THOMAS H , JOHNSON MARK G , LAU BENEDICT C , YU LEUNG , GARLEPP BRUNO W , CHAN YIU-FAI , KIM JUN , TRAN CHANH VI , STARK DONALD C
IPC分类号： H04L7/00 , G06F1/10 , G11C7/22 , H03K5/00 , H03K5/13 , H03K5/24 , H03L7/07 , H03L7/081
摘要： Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the delayed output clock or the output clock.

3. 发明专利

DE69840242D1 未知
公开(公告)号：DE69840242D1
公开(公告)日：2009-01-02
申请号：DE69840242
申请日：1998-02-04
申请人： RAMBUS INC
发明人： DONNELLY KEVIN S , CHAU PAK SHING , HOROWITZ MARK A , LEE THOMAS H , JOHNSON MARK G , LAU BENEDICT C , YU LEUNG , GARLEPP BRUNO W , CHAN YIU-FAI , KIM JUN , TRAN CHANH VI , STARK DONALD C
IPC分类号： H03L7/081 , G06F1/10 , G11C7/22 , H03K5/00 , H03K5/13 , H03K5/24 , H03L7/07 , H04L7/00
摘要： Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the delayed output clock or the output clock.

4. 发明专利

AU3721895A Cmos dynamic latching input buffer circuit 未知
公开(公告)号：AU3721895A
公开(公告)日：1996-04-26
申请号：AU3721895
申请日：1995-09-18
申请人： RAMBUS INC
发明人： JOHNSON MARK G
IPC分类号： H03K3/356

5. 发明申请

WO9837656A3 DELAY LOCKED LOOP CIRCUITRY FOR CLOCK DELAY ADJUSTMENT 审中-公开
标题翻译：延迟锁定环路电路用于时钟延迟调整
公开(公告)号：WO9837656A3
公开(公告)日：1998-11-19
申请号：PCT/US9802053
申请日：1998-02-04
申请人： RAMBUS INC
发明人： DONNELLY KEVIN S , CHAU PAK SHING , HOROWITZ MARK A , LEE THOMAS H , JOHNSON MARK G , LAU BENEDICT C , YU LEUNG , GARLEPP BRUNO W , CHAN YIU-FAI , KIM JUN , TRAN CHANH VI , STARK DONALD C
IPC分类号： G06F1/10 , G11C7/22 , H03K5/00 , H03K5/13 , H03K5/24 , H03L7/07 , H03L7/081 , H04L7/00 , H04L
CPC分类号： H03K5/133 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/2481 , H03K2005/00026 , H03K2005/00032 , H03K2005/00052 , H03K2005/00208 , H03L7/07 , H03L7/0805 , H03L7/0812 , H03L7/0814 , H04L7/0008 , H04L7/0025 , H04L7/0037
摘要： Delay locked loops (320, 350) for generating a predetermined phase relationship between a pair of clocks (300, 310). A first delay-locked loop (320) includes delay elements arranged in a chain, the chain receiving an input clock (300) and generating, from each delay element, a set of phase vectors (330), each shifted a unit delay from the adjacent vector. The first delay-locked loop (320) adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors (330) span a predetermined phase shift of the input clock (300). A second delay-locked loop (350) selects, from the first delay-locked loop (320), a pair of phase vectors which brackets the phase of an input clock (300). A phase interpolator (560) receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector (590) compares the delayed output clock with the input clock and adjusts the phase interpolator (560), based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock (410). As a result, there is a predetermined phase relationship being the amount of delay between the output clock (640) and the delayed output clock (360).

6. 发明公开

EP1031203A4 DELAY LOCKED LOOP CIRCUITRY FOR CLOCK DELAY ADJUSTMENT 失效
标题翻译：时延控制回路调整时钟延迟电路
公开(公告)号：EP1031203A4
公开(公告)日：2003-04-16
申请号：EP98906112
申请日：1998-02-04
申请人： RAMBUS INC
发明人： DONNELLY KEVIN S , CHAU PAK SHING , HOROWITZ MARK A , LEE THOMAS H , JOHNSON MARK G , LAU BENEDICT C , YU LEUNG , GARLEPP BRUNO W , CHAN YIU-FAI , KIM JUN , TRAN CHANH VI , STARK DONALD C
IPC分类号： G06F1/10 , G11C7/22 , H03K5/00 , H03K5/13 , H03K5/24 , H03L7/07 , H03L7/081 , H04L7/00
CPC分类号： H03K5/133 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/2481 , H03K2005/00026 , H03K2005/00032 , H03K2005/00052 , H03K2005/00208 , H03L7/07 , H03L7/0805 , H03L7/0812 , H03L7/0814 , H04L7/0008 , H04L7/0025 , H04L7/0037
摘要： Delay locked loops (320, 350) for generating a predetermined phase relationship between a pair of clocks (300, 310). A first delay-locked loop (320) includes delay elements arranged in a chain, the chain receiving an input clock (300) and generating, from each delay element, a set of phase vectors (330), each shifted a unit delay from the adjacent vector. The first delay-locked loop (320) adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors (330) span a predetermined phase shift of the input clock (300). A second delay-locked loop (350) selects, from the first delay-locked loop (320), a pair of phase vectors which brackets the phase of an input clock (300). A phase interpolator (560) receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector (590) compares the delayed output clock with the input clock and adjusts the phase interpolator (560), based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock (410). As a result, there is a predetermined phase relationship being the amount of delay between the output clock (640) and the delayed output clock (360).

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