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1. 发明专利

AU2002334980A1 Method and apparatus for evaluating and optimizing a signaling system 未知
公开(公告)号：AU2002334980A1
公开(公告)日：2003-04-22
申请号：AU2002334980
申请日：2002-10-11
申请人： RAMBUS INC
发明人： ZERBE JARED , STONECYPHER WILLIAM FRANKLIN , CHAU PAK SHING
IPC分类号： G01R31/28 , G01R31/317 , H04B3/32
摘要： A method and apparatus for evaluating and optimizing a signaling system is described. Evaluation is accomplished using the same circuits actually involved in normal operation of the signaling system. Capability for in-situ testing of a signaling system is provided, and information may be obtained from the actual perspective of a receive circuit in the system. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. Preferably, the patterns are repeating patterns that allow many iterations of testing to be performed. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. Information obtained from testing may be used to assess the effects of various system parameters, including but not limited to output current, crosstalk cancellation coefficients, and self-equalization coefficients, and system parameters may be adjusted to optimize system performance. An embodiment of the invention may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the invention may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

2. 发明专利

DE60238646D1 VERFAHREN UND VORRICHTUNG ZUR BEWERTUNG UND OPTIMIERUNG EINES ZEICHENGABESYSTEMS 未知
公开(公告)号：DE60238646D1
公开(公告)日：2011-01-27
申请号：DE60238646
申请日：2002-10-11
申请人： RAMBUS INC
发明人： ZERBE JARED , CHAU PAK SHING , STONECYPHER WILLIAM FRANKLIN
IPC分类号： H04Q1/00 , G01R31/28 , G01R31/317 , H04B3/32

3. 发明专利

DE69636797D1 未知
公开(公告)号：DE69636797D1
公开(公告)日：2007-02-08
申请号：DE69636797
申请日：1996-05-21
申请人： RAMBUS INC
发明人： DONNELLY KEVIN S , CHAU PAK SHING
IPC分类号： H03K5/135 , H03K5/15 , H03H11/18 , H03K5/00 , H03K5/13 , H03K5/151 , H03L7/081
摘要： A phase shifting circuit that may be used as part of a quadrature clock generator. The phase shifting circuit comprises a triangle wave generator coupled to receive an input reference signal. The triangle wave generator outputs a pair of complementary triangle wave signals in response to the input reference signal. A comparator having a pair of inputs is coupled to receive the pair of complementary triangle wave signals. The comparator outputs and output signal having a predetermined phase relationship with the input reference signal in response to a comparison between the pair of complementary triangle wave signals.

4. 发明专利

AU2002334980A8 Method and apparatus for evaluating and optimizing a signaling system 未知
公开(公告)号：AU2002334980A8
公开(公告)日：2006-11-09
申请号：AU2002334980
申请日：2002-10-11
申请人： RAMBUS INC
发明人： ZERBE JARED , STONECYPHER WILLIAM FRANKLIN , CHAU PAK SHING
IPC分类号： G01R31/28 , G01R31/317 , H04B3/32
摘要： A method and apparatus for evaluating and optimizing a signaling system is described. Evaluation is accomplished using the same circuits actually involved in normal operation of the signaling system. Capability for in-situ testing of a signaling system is provided, and information may be obtained from the actual perspective of a receive circuit in the system. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. Preferably, the patterns are repeating patterns that allow many iterations of testing to be performed. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. Information obtained from testing may be used to assess the effects of various system parameters, including but not limited to output current, crosstalk cancellation coefficients, and self-equalization coefficients, and system parameters may be adjusted to optimize system performance. An embodiment of the invention may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the invention may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

5. 发明专利

DE69840350D1 未知
公开(公告)号：DE69840350D1
公开(公告)日：2009-01-22
申请号：DE69840350
申请日：1998-02-04
申请人： RAMBUS INC
发明人： DONNELLY KEVIN S , CHAU PAK SHING , HOROWITZ MARK A , LEE THOMAS H , JOHNSON MARK G , LAU BENEDICT C , YU LEUNG , GARLEPP BRUNO W , CHAN YIU-FAI , KIM JUN , TRAN CHANH VI , STARK DONALD C
IPC分类号： H04L7/00 , G06F1/10 , G11C7/22 , H03K5/00 , H03K5/13 , H03K5/24 , H03L7/07 , H03L7/081
摘要： Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the delayed output clock or the output clock.

6. 发明专利

DE69635626T2 未知
公开(公告)号：DE69635626T2
公开(公告)日：2006-10-26
申请号：DE69635626
申请日：1996-05-21
申请人： RAMBUS INC
发明人： DONNELLY KEVIN S , CHAU PAK SHING
IPC分类号： H03H11/18 , H03K5/15 , H03K5/00 , H03K5/13 , H03K5/151 , H03L7/081
摘要： A phase shifting circuit that may be used as part of a quadrature clock generator. The phase shifting circuit comprises a triangle wave generator coupled to receive an input reference signal. The triangle wave generator outputs a pair of complementary triangle wave signals in response to the input reference signal. A comparator having a pair of inputs is coupled to receive the pair of complementary triangle wave signals. The comparator outputs and output signal having a predetermined phase relationship with the input reference signal in response to a comparison between the pair of complementary triangle wave signals.

7. 发明专利

DE69635626D1 未知
公开(公告)号：DE69635626D1
公开(公告)日：2006-01-26
申请号：DE69635626
申请日：1996-05-21
申请人： RAMBUS INC
发明人： DONNELLY KEVIN S , CHAU PAK SHING
IPC分类号： H03K5/15 , H03H11/18 , H03K5/00 , H03K5/13 , H03K5/151 , H03L7/081
摘要： A phase shifting circuit that may be used as part of a quadrature clock generator. The phase shifting circuit comprises a triangle wave generator coupled to receive an input reference signal. The triangle wave generator outputs a pair of complementary triangle wave signals in response to the input reference signal. A comparator having a pair of inputs is coupled to receive the pair of complementary triangle wave signals. The comparator outputs and output signal having a predetermined phase relationship with the input reference signal in response to a comparison between the pair of complementary triangle wave signals.

8. 发明专利

DE69840242D1 未知
公开(公告)号：DE69840242D1
公开(公告)日：2009-01-02
申请号：DE69840242
申请日：1998-02-04
申请人： RAMBUS INC
发明人： DONNELLY KEVIN S , CHAU PAK SHING , HOROWITZ MARK A , LEE THOMAS H , JOHNSON MARK G , LAU BENEDICT C , YU LEUNG , GARLEPP BRUNO W , CHAN YIU-FAI , KIM JUN , TRAN CHANH VI , STARK DONALD C
IPC分类号： H03L7/081 , G06F1/10 , G11C7/22 , H03K5/00 , H03K5/13 , H03K5/24 , H03L7/07 , H04L7/00
摘要： Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the delayed output clock or the output clock.

9. 发明专利

AU5866396A Phase shifter for use in a quadrature clock generator 未知
公开(公告)号：AU5866396A
公开(公告)日：1996-12-11
申请号：AU5866396
申请日：1996-05-21
申请人： RAMBUS INC
发明人： DONNELLY KEVIN S , CHAU PAK SHING
IPC分类号： H03K5/15 , H03H11/18 , H03K5/00 , H03K5/13 , H03K5/151 , H03L7/081
摘要： A phase shifting circuit that may be used as part of a quadrature clock generator. The phase shifting circuit comprises a triangle wave generator coupled to receive an input reference signal. The triangle wave generator outputs a pair of complementary triangle wave signals in response to the input reference signal. A comparator having a pair of inputs is coupled to receive the pair of complementary triangle wave signals. The comparator outputs and output signal having a predetermined phase relationship with the input reference signal in response to a comparison between the pair of complementary triangle wave signals.

10. 发明申请

WO9837656A3 DELAY LOCKED LOOP CIRCUITRY FOR CLOCK DELAY ADJUSTMENT 审中-公开
标题翻译：延迟锁定环路电路用于时钟延迟调整
公开(公告)号：WO9837656A3
公开(公告)日：1998-11-19
申请号：PCT/US9802053
申请日：1998-02-04
申请人： RAMBUS INC
发明人： DONNELLY KEVIN S , CHAU PAK SHING , HOROWITZ MARK A , LEE THOMAS H , JOHNSON MARK G , LAU BENEDICT C , YU LEUNG , GARLEPP BRUNO W , CHAN YIU-FAI , KIM JUN , TRAN CHANH VI , STARK DONALD C
IPC分类号： G06F1/10 , G11C7/22 , H03K5/00 , H03K5/13 , H03K5/24 , H03L7/07 , H03L7/081 , H04L7/00 , H04L
CPC分类号： H03K5/133 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/2481 , H03K2005/00026 , H03K2005/00032 , H03K2005/00052 , H03K2005/00208 , H03L7/07 , H03L7/0805 , H03L7/0812 , H03L7/0814 , H04L7/0008 , H04L7/0025 , H04L7/0037
摘要： Delay locked loops (320, 350) for generating a predetermined phase relationship between a pair of clocks (300, 310). A first delay-locked loop (320) includes delay elements arranged in a chain, the chain receiving an input clock (300) and generating, from each delay element, a set of phase vectors (330), each shifted a unit delay from the adjacent vector. The first delay-locked loop (320) adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors (330) span a predetermined phase shift of the input clock (300). A second delay-locked loop (350) selects, from the first delay-locked loop (320), a pair of phase vectors which brackets the phase of an input clock (300). A phase interpolator (560) receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector (590) compares the delayed output clock with the input clock and adjusts the phase interpolator (560), based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock (410). As a result, there is a predetermined phase relationship being the amount of delay between the output clock (640) and the delayed output clock (360).

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