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1. 发明授权

US5912881A Method and apparatus for fast checking the frame check sequence of a segmented message 失效
标题翻译：用于快速检查分段消息的帧校验序列的方法和装置
公开(公告)号：US5912881A
公开(公告)日：1999-06-15
申请号：US754562
申请日：1996-11-21
申请人： R Glaise , Eric Lallemand , Gilles Toubol , Fabrice Verplanken
发明人： R Glaise , Eric Lallemand , Gilles Toubol , Fabrice Verplanken
IPC分类号： G06F13/00 , G06F11/10 , H03M13/00 , H03M13/09 , H04L1/00 , H04L12/56 , H04J3/24
CPC分类号： H03M13/091 , H04L1/0083 , H04L2012/5652
摘要： A process and an apparatus to calculate the FCS (Frame Check Sequence) error checking code of a message sent over a connection and segmented into a finite number of packets in a fixed size packets network. The process is implemented in the adapter cards of the ATM network access nodes (2, 4) located at the boundary of the ATM network. These nodes, when supporting AAL5 type ATM connections, reassemble messages which have been segmented at the entry of the network and to calculate the FCS of the message cell payloads for data integrity checking. The process of the invention starts at each reception of a cell with the calculation of a partial FCS (10) performed in parallel to the connection control block fetching phase (40); these 2 parallel operations allow FCS checking during the cell processing time of connections established over medium and high speed lines.
摘要翻译：计算通过连接发送并在固定大小的分组网络中分段成有限数量的分组的消息的FCS（帧校验序列）错误校验码的过程和装置。该过程在位于ATM网络边界处的ATM网络接入节点（2,4）的适配卡中实现。当支持AAL5型ATM连接时，这些节点重新组合已经在网络入口处被分段的消息，并且计算用于数据完整性检查的消息小区有效载荷的FCS。本发明的过程开始于每个小区的接收，计算与连接控制块提取阶段（40）并行执行的部分FCS（10）。这两个并行操作允许在通过中速和高速线路建立的连接的单元处理时间期间进行FCS检查。

2. 发明授权

US5557266A System for cascading data switches in a communication node 失效
标题翻译：用于在通信节点中级联数据交换机的系统
公开(公告)号：US5557266A
公开(公告)日：1996-09-17
申请号：US206363
申请日：1994-03-07
申请人： Jean Calvignac , Pierre Huon , Daniel Orsatti , Gilles Toubol , Fabrice Verplanken
发明人： Jean Calvignac , Pierre Huon , Daniel Orsatti , Gilles Toubol , Fabrice Verplanken
IPC分类号： H04L12/933 , H04L12/935 , H04L12/937 , H04L29/00 , H03K17/00
CPC分类号： H04L49/15 , H04L29/00 , H04L49/103 , H04L49/254 , H04L49/3027
摘要： A system for cascading data switches in a communication node allows for transfer of data among a plurality of adapters (30-i), expanding a moderate low cost switch 31-1 with additional hardware (31-2, 31-3, 31-4) to interconnect more adapters. The data transfers are performed by a plurality of Burst Relaying Cascaders (32-i) which connect the plurality of switches (31-i). A similar interface connect each adapter to the switch. A set of address information is used by the system to route the data from the source adapter to the target adapter, allowing navigation among the intermediate switches. Each interface contains a table where the address of every adapter of the whole system could be constructed dynamically at each communication node configuration.
摘要翻译：用于在通信节点中级联数据交换的系统允许在多个适配器（30-i）之间传输数据，用附加硬件（31-2,31-3-3,34-4）扩展适度的低成本开关31-1 ）来互连更多适配器。数据传送由连接多个开关（31-i）的多个突发中继级联（32-i）执行。类似的接口将每个适配器连接到交换机。系统使用一组地址信息将数据从源适配器路由到目标适配器，允许在中间交换机之间导航。每个接口包含一个表，其中可以在每个通信节点配置下动态构建整个系统的每个适配器的地址。

3. 发明授权

US06370148B1 Data communications 失效
标题翻译：数据通信
公开(公告)号：US06370148B1
公开(公告)日：2002-04-09
申请号：US09110920
申请日：1998-07-06
申请人： Jean Calvignac , Daniel Orsatti , Fabrice Verplanken , Gilles Toubol
发明人： Jean Calvignac , Daniel Orsatti , Fabrice Verplanken , Gilles Toubol
IPC分类号： H04J314
CPC分类号： H04L49/106 , H04L49/20 , H04L49/254 , H04L49/3018 , H04L49/508
摘要： An improved arbiter is described for arbitrating requests by a plurality of first data processing units for access to a plurality of second data processing units interconnected by a switching system of a type in which at any time each first unit can only access one second unit and each second unit can only be accessed by one first unit. The arbiter comprises a scheduler mechanism for repeatedly selecting access requests with a defined minimum probability of selecting a request for each first unit-second unit combination. Rearrangement storage means records requests selected by the scheduler mechanism. A rearranger is provided for repeatedly selecting a set of requests recorded in the rearrangement storage means, so that only one request per first unit and per second unit is selected, using a priority mechanism which increases the probability of selection with the length of time a request is stored in the rearrangement storage means. Finally, means are provided for communicating the grant of the selected set of requests to the switching system and for deleting the selected set of requests from the rearrangement storage means. In one embodiment, the arbiter is used for controlling switching paths in a packet data switch.
摘要翻译：描述了一种改进的仲裁器，用于对多个第一数据处理单元的请求进行仲裁，以访问多个第二数据处理单元，该多个第二数据处理单元通过一种类型的交换系统互连，其中每个第一单元在任何时候只能访问一个第二单元，并且每个第二单元只能由一个第一单元访问。仲裁器包括一个调度机制，用于以对每个第一单位 - 第二单位组合选择一个请求的限定的最小概率重复地选择访问请求。重排存储装置记录由调度机制选择的请求。提供了一种重排器，用于重复选择记录在重排存储装置中的一组请求，使得仅使用优先级机制选择每第一单元和每秒单元的一个请求，该优先级机制随着请求的长度增加选择的概率存储在重排存储装置中。最后，提供了用于将所选择的一组请求的许可传送给交换系统并且用于从重排存储装置中删除所选择的一组请求的装置。在一个实施例中，仲裁器用于控制分组数据交换机中的交换路径。

4. 发明授权

US5668798A Multiplexed TC sublayer for ATM switch 失效
标题翻译：用于ATM交换机的多路TC子层
公开(公告)号：US5668798A
公开(公告)日：1997-09-16
申请号：US547827
申请日：1995-10-25
申请人： Gilles Toubol , Jean Calvignac , Jean-Luc Frenoy , Daniel Orsatti , Luc Torres , Fabrice Verplanken
发明人： Gilles Toubol , Jean Calvignac , Jean-Luc Frenoy , Daniel Orsatti , Luc Torres , Fabrice Verplanken
IPC分类号： H04L12/70 , H04Q11/04 , H04L12/56
CPC分类号： H04Q11/0478 , H04L2012/5615 , H04L2012/5616
摘要： A data switching device, such as an ATM or Asynchronous Transfer Mode switch, includes a switching fabric with multiple input and output leads. The device also includes at least one input adapter for receiving data cells on each of a number of input ports and at least one output adapter for delivering data cells switched through the switching fabric to a target port in a set of output ports. Error and format checks are performed on incoming cells and counts are kept of the number of good cells and invalid cells received on a particular input port. To reduce hardware costs, the counts are kept in a random access memory which is shared among the input ports. Several storage locations are allocated to each input port to maintain the necessary counts.
摘要翻译：诸如ATM或异步传输模式开关的数据交换设备包括具有多个输入和输出引线的交换结构。该设备还包括至少一个用于在多个输入端口中的每一个上接收数据单元的输入适配器和至少一个输出适配器，用于将通过交换结构交换的数据单元传送到一组输出端口中的目标端口。在进入的单元格上执行错误和格式检查，并且保留在特定输入端口上接收到的良好单元和无效单元的数量的计数。为了降低硬件成本，将计数保存在随机存取存储器中，该存储器在输入端口之间共享。将几个存储位置分配给每个输入端口以维持必要的计数。

5. 发明授权

US06195335B1 Data switch 失效
标题翻译：数据开关
公开(公告)号：US06195335B1
公开(公告)日：2001-02-27
申请号：US09110917
申请日：1998-07-06
申请人： Jean Calvignac , Daniel Orsatti , Gilles Toubol , Fabrice Verplanken , Claude Basso
发明人： Jean Calvignac , Daniel Orsatti , Gilles Toubol , Fabrice Verplanken , Claude Basso
IPC分类号： H04L1256
CPC分类号： H04L12/5601 , H04L49/1576 , H04L2012/5679 , H04L2012/5681
摘要： A packet data switch is described comprising a crossbar switch fabric including a set of crosspoint buffers for storing at least one data packet, one for each input/output pair. An input queue is provided for each input-output pair and means are provided for storing incoming data packets in one of the queues corresponding to an input-output routing for the data packet. An input scheduler repeatedly selects one queue from the plurality of queues at each input and a data packet is transferred from the queue selected by the input scheduler from the input queue means to the crosspoint buffer corresponding to the input-output routing for the data packet. A back pressure mechanism is arranged to inhibit selection by the first selector of queues corresponding to input/output pairs for which the respective crosspoint buffer is full. Finally, an output scheduler repeatedly selects for each output one of the crosspoint buffers corresponding to the output and the switch is responsive to the output scheduler to complete the transmission through the switch fabric of the data packet stored in the crosspoint buffer selected by the output scheduler.
摘要翻译：描述包数据交换机，其包括交叉开关结构，其包括用于存储至少一个数据分组的一组交叉点缓冲器，每个数据分组一个用于每个输入/输出对。为每个输入 - 输出对提供输入队列，并且提供装置用于在对应于数据分组的输入 - 输出路由的一个队列中存储输入数据分组。输入调度器在每个输入处重复从多个队列中选择一个队列，并且将数据分组从输入调度器选择的队列从输入队列装置传送到对应于数据分组的输入 - 输出路由的交叉点缓冲区。背压机构被布置为禁止第一选择器对应于相应交叉点缓冲器已满的输入/输出对的队列的选择。最后，输出调度器针对每个输出重复选择对应于输出的交叉点缓冲器之一，并且交换机响应于输出调度器来完成通过存储在由输出调度器选择的交叉点缓冲器中的数据分组的交换结构的传输。

6. 发明授权

US5251206A Hybrid switching system for a communication node 失效
标题翻译：用于通信节点的混合交换系统
公开(公告)号：US5251206A
公开(公告)日：1993-10-05
申请号：US684111
申请日：1991-04-12
申请人： Jean Calvignac , Eric Saint Georges , Daniel Orsatti , Gilles Toubol , Fabrice Verplanken , Francois Nicolas
发明人： Jean Calvignac , Eric Saint Georges , Daniel Orsatti , Gilles Toubol , Fabrice Verplanken , Francois Nicolas
IPC分类号： H04Q3/52 , H04L12/64 , H04L12/56 , H04L12/50
CPC分类号： H04L12/64
摘要： The hybrid packet and circuit switching system allows merging of packet and circuit traffic from user interface modules on a TDM bus and transfer of packet information from one module to another module or the exchange circuit information between modules. Circuit exchanges or packet transfers are performed synchronously on the TDM busses in bursts of period T, with each burst comprising a fixed number of bytes. The bursts are switched by switch 1. A routing indication common to the packet and circuit bursts is used for controlling the switching of the bursts by the switch 1. The indication is performed by piggy backing the target module address for the circuit bursts, as well as for the packet burst, with the data bursts. Marking tables needed for the circuit burst allocation are located in the user interface modules.

7. 发明授权

US06993035B2 System for routing data packets through a crossbar switch in expansion mode 有权
公开(公告)号：US06993035B2
公开(公告)日：2006-01-31
申请号：US09683231
申请日：2001-12-04
申请人： Alain Benayoun , Patrick Michel , Gilles Toubol
发明人： Alain Benayoun , Patrick Michel , Gilles Toubol
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L12/5601 , H04L12/46 , H04L49/1576 , H04L49/255 , H04L49/455 , H04L2012/5674
摘要： The present invention describes a switching module for use either in port or speed expansion mode. The switching module is preferably used in a data transmission system consisting of a number of Local Area Networks LANs interconnected by a hub which includes a number of LAN adapters respectively connected to said LANs. A crossbar switch interconnects all LAN adapters and consists of switching modules having first receiving means for storing a first number of data packets; second receiving means for storing a second number of data packets; first outputting means for outputting a first subset of the first number of data packets and the second number of data packets; second outputting means for outputting a second subset of the first number of data packets; and switching means, coupled to the first and second receiving means and coupled to the first and second outputting means for routing the first and the second subsets of the first number of data packets and the second number of data packets to the respective first or second output means. The routing of the incoming data packets to their final destination is done without modifying the data packet header as a data packet sent by a source of adapter contains in its header the physical address of the destination adapter.

8. 发明授权

US06426953B1 Method of operating an internal high speed ATM bus inside a switching core 失效
标题翻译：在切换核心内部操作内部高速ATM总线的方法
公开(公告)号：US06426953B1
公开(公告)日：2002-07-30
申请号：US09189871
申请日：1998-11-10
申请人： Alain Benayoun , Patrick Michel , Claude Pin , Gilles Toubol
发明人： Alain Benayoun , Patrick Michel , Claude Pin , Gilles Toubol
IPC分类号： H04L1256
CPC分类号： H04L12/5601 , H04L49/107 , H04L49/255 , H04L2012/5674
摘要： The ATM bus (100) is composed of a clock signal, CLK, a synchronization signal, -SYNC, a data bus, S(0-31), and an adapter identification bus, SID(0-3). It is a synchronous bus running at any clock rates. The clock signal is generated by the backplane (20) and transmitted to each adapter (10-1, . . . 10-N). During each clock cycle, the data bus has three serialized operation modes (or cycles) defined in this order: a bus_req cycle of 1 clock period, a bus_ack cycle of 1 clock period and an ATM cell_xfr cycle of 14 clock periods. The free-running synchronization signal is generated on the backplane (20) and transmitted to each adapter (10-1, . . . , 10-N). The activation of the synchronization signal of one bit of the data bus, S(0-31), starts the bus_req cycle. In each case, the remaining data bus signals are left in high impedance state. To increase the bus performance, the synchronization signal is held active until an adapter activates its bus_request signal. For the bus_ack cycle, an arbiter located in a control logic (102) determines which adapter has the bus granted for its data transfer by generating an acknowledge signal to the corresponding requester during one clock period following the deactivation of the synchronization signal. The next fourteen clock periods starts the xfer_cycle for transferring one ATM cell from a requester adapter to a destination adapter. At the end of this transmission, another req_cycle starts by the activation of the synchronization signal.
摘要翻译： ATM总线（100）由时钟信号CLK，同步信号-SYNC，数据总线S（0-31）和适配器识别总线SID（0-3）组成。它是以任何时钟速率运行的同步总线。时钟信号由背板（20）产生并发送到每个适配器（10-1，...，10-N）。在每个时钟周期期间，数据总线具有以下顺序定义的三个串行化操作模式（或周期）：1个时钟周期的bus_req周期，1个时钟周期的bus_ack周期和14个时钟周期的ATM cell_xfr周期。自由运行的同步信号在背板（20）上产生并被发送到每个适配器（10-1，...，10-N）。数据总线S（0-31）的一位的同步信号的激活开始bus_req循环。在每种情况下，剩余的数据总线信号保持在高阻抗状态。为了增加总线性能，同步信号保持有效，直到适配器激活其总线请求信号。对于bus_ack周期，位于控制逻辑（102）中的仲裁器通过在停止同步信号之后的一个时钟周期期间通过向对应的请求者生成确认信号来确定哪个适配器具有用于其数据传输的总线。接下来的十四个时钟周期启动xfer_cycle，用于将一个ATM信元从请求者适配器传输到目标适配器。在该传输结束时，通过同步信号的激活开始另一个req_cycle。

9. 发明授权

US07751312B2 System and method for packet switch cards re-synchronization 有权
标题翻译：分组交换卡重新同步的系统和方法
公开(公告)号：US07751312B2
公开(公告)日：2010-07-06
申请号：US10860293
申请日：2004-06-03
申请人： Alain Benayoun , Patrick Michel , Gilles Toubol
发明人： Alain Benayoun , Patrick Michel , Gilles Toubol
IPC分类号： G01R31/08
CPC分类号： H04L49/552 , H04L49/1523
摘要： The disclosed invention relates to a re-synchronization system that operates in a switching arrangement receiving a plurality of incoming data packets. The switching arrangement is made of an active switch card that transmits the incoming data packets and a backup switch card that may be re-activated by an operator after replacement. The re-synchronization system is implemented in each switch card. When the backup switch card is re-activated, both switch cards receive the incoming data packets and the system of the invention allows to re-synchronized both switch cards by controlling the transmission of the incoming data packets out of each switch card until the same data packets are transmitted. The re-synchronization system further comprise storage for storing the incoming data packets and detector for detecting a re-synchronization information among the incoming data packets.
摘要翻译：所公开的本发明涉及一种在接收多个输入数据分组的交换机构中操作的再同步系统。切换装置由传送数据包的主动交换卡和备用交换机卡组成，备用交换机卡可以由操作员在更换后重新激活。在每个交换机卡中实现重新同步系统。当备用交换卡被重新启动时，两个交换卡都接收输入的数据包，并且本发明的系统允许通过控制每个交换机卡中的输入数据分组的传输来重新同步两个交换机卡，直到相同的数据数据包被传输。重新同步系统还包括用于存储输入数据分组的存储器和用于检测输入数据分组之间的重新同步信息的检测器。

10. 发明授权

US07085802B1 Device for connecting two workstations with several links 失效
标题翻译：用于连接两个工作站与多个链接的设备
公开(公告)号：US07085802B1
公开(公告)日：2006-08-01
申请号：US09680798
申请日：2000-10-06
申请人： Alain Benayoun , Patrick Michel , Jean-Francois Le Pennec , Gilles Toubol
发明人： Alain Benayoun , Patrick Michel , Jean-Francois Le Pennec , Gilles Toubol
IPC分类号： G06F13/00
CPC分类号： G06F13/4059
摘要： According to the invention, a device for transferring data between two workstations connected to a network is provided. This device comprises means for distributing data among a plurality of links of the network. Preferentially, the device comprises a dual-port memory for storing the data. In a preferred embodiment, the device further comprises a high speed interface for transmitting data from a workstation to the memory, associated with each link, a low speed interface for transmitting a part of the data from the memory to this link, and a controller for monitoring the data flow between the workstation and the plurality of links, by controlling the memory and the interfaces.
摘要翻译：根据本发明，提供了一种用于在连接到网络的两个工作站之间传送数据的设备。该设备包括用于在网络的多个链路之间分发数据的装置。优选地，该设备包括用于存储数据的双端口存储器。在优选实施例中，该设备还包括用于将数据从工作站发送到与每个链路相关联的存储器的高速接口，用于将数据的一部分从存储器传输到该链路的低速接口，以及用于通过控制存储器和接口来监视工作站和多个链路之间的数据流。

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