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1. 发明申请

WO2018057148A1 CONFIGURABLE MIXER 审中-公开
标题翻译：可配置的混合器
公开(公告)号：WO2018057148A1
公开(公告)日：2018-03-29
申请号：PCT/US2017/046801
申请日：2017-08-14
申请人： QUALCOMM INCORPORATED
发明人： CHOI, Kiyong , ZENG, Yi , KIM, Hong Sun , VUJCIC, Sasha , PATEL, Chirag Dipak , TASIC, Aleksandar Miodrag , GATHMAN, Timothy Donald , CHEN, Wu-Hsin , VAN ZALINGE, Klaas
IPC分类号： H04B1/10 , H03D7/14
摘要： A method and apparatus are disclosed for a configurable mixer capable of operating in a linear, a legacy, and a low-power mode. In the linear mode, the configurable mixer is configured to operate as a double-balanced mixer to multiply a first differential signal by a second differential signal. In the legacy mode, the configurable mixer is configured to as a double-balanced mixer to multiply a differential signal by a single-ended signal. In the low-power mode, the configurable mixer is configured to operate as a single-balanced mixer to multiply a differential signal by a single-ended signal. The operating mode of the configurable mixer may be based, at least in part, on a mode control signal. In some embodiments, the configurable mixer may be included in an analog front end of a wireless communication device.
摘要翻译：公开了一种用于能够以线性，传统和低功率模式操作的可配置混频器的方法和设备。在线性模式中，可配置混频器被配置为作为双平衡混频器操作以将第一差分信号乘以第二差分信号。在传统模式中，可配置混频器被配置为双平衡混频器，以将差分信号乘以单端信号。在低功耗模式下，可配置混频器配置为作为单平衡混频器工作，以将差分信号与单端信号相乘。可配置混频器的操作模式可以至少部分地基于模式控制信号。在一些实施例中，可配置混频器可以被包括在无线通信设备的模拟前端中。

2. 发明申请

WO2010151890A1 FM TRANSMITTER WITH A DELTA-SIGMA MODULATOR AND A PHASE-LOCKED LOOP 审中-公开
标题翻译：具有三角形调制器和相位锁定环的FM发射器
公开(公告)号：WO2010151890A1
公开(公告)日：2010-12-29
申请号：PCT/US2010/040247
申请日：2010-06-28
申请人： QUALCOMM Incorporated , TRIKHA, Pushp K. , PAN, Tzu-wang , YANG, Eugene , ZENG, Yi , LIN, I-Hsiang , VISHWANATH, Tg
发明人： TRIKHA, Pushp K. , PAN, Tzu-wang , YANG, Eugene , ZENG, Yi , LIN, I-Hsiang , VISHWANATH, Tg
IPC分类号： H04H20/57 , H04B1/40 , H04H40/45
CPC分类号： H04H20/57 , H04H40/45
摘要： A frequency modulation (FM) transmitter implemented with a delta-sigma modulator and a phase-locked loop (PLL) is described. The delta-sigma modulator receives a modulating signal (e.g., an FM stereo multiplex (MPX) signal) and provides a modulator output signal. The PLL performs frequency modulation based on the modulator output signal and provides an FM signal. The FM transmitter may further include a gain/phase compensation unit and a scaling unit. The compensation unit may compensate the modulating signal for the closed-loop response of the PLL. The scaling unit may scale the amplitude of the modulating signal based on a gain to obtain a target frequency deviation for the FM signal. The PLL may operate in a transmit mode or a receive mode, may perform frequency modulation in the transmit mode, and may provide a local oscillator (LO) signal at a fixed frequency in the receive mode.
摘要翻译：描述了用Δ-Σ调制器和锁相环（PLL）实现的频率调制（FM）发射机。 Δ-Σ调制器接收调制信号（例如，FM立体声多路复用（MPX）信号），并提供调制器输出信号。 PLL根据调制器输出信号进行调频，并提供FM信号。 FM发射机还可以包括增益/相位补偿单元和缩放单元。补偿单元可以补偿PLL的闭环响应的调制信号。缩放单元可以基于增益来调整调制信号的幅度，以获得FM信号的目标频率偏差。 PLL可以以发送模式或接收模式工作，可以在发送模式下执行频率调制，并且可以在接收模式下以固定频率提供本地振荡器（LO）信号。

3. 发明申请

WO2019212856A1 CONCURRENT SUPPORT FOR MULTIPLE FREQUENCY BANDS FOR SATELLITE NAVIGATION SIGNALS 审中-公开
公开(公告)号：WO2019212856A1
公开(公告)日：2019-11-07
申请号：PCT/US2019/029140
申请日：2019-04-25
申请人： QUALCOMM INCORPORATED
发明人： ZENG, Yi , KIM, Hong Sun , WANG, Cheng-Han
IPC分类号： G01S19/32 , G01S19/21 , H03D7/16 , H04B1/00 , H04B1/30 , H04K3/00
摘要： A radio frequency (RF) receiver, for example a satellite positioning system receiver, can be configured to use a single phase locked loop for generating an oscillator signal to perform downconversion of signals in two different frequency bands using two or more local oscillators. A first RF signal portion includes a first signal band and undergoes double downconversion using a first mixer and a second mixer, while a second RF signal portion includes a second signal band and undergoes single downconversion using a single mixer. A controller is configured to determine a first oscillator divider value and a second oscillator divider value to avoid a jammer frequency and frequency dividers are used to generate the two or more local oscillators.

4. 发明申请

WO2011100539A1 WIDE BAND LNA WITH NOISE CANCELING 审中-公开
标题翻译：宽带上弦与噪音消除
公开(公告)号：WO2011100539A1
公开(公告)日：2011-08-18
申请号：PCT/US2011/024516
申请日：2011-02-11
申请人： QUALCOMM INCORPORATED , ZENG, Yi , LI, Xiaoyong , APTE, Rahul A.
发明人： ZENG, Yi , LI, Xiaoyong , APTE, Rahul A.
IPC分类号： H03F1/26 , H03F3/195 , H03F1/42 , H03F3/347 , H03F3/21 , H03F3/02
CPC分类号： H03F1/0205 , H01B3/004 , H03F1/26 , H03F1/42 , H03F3/195 , H03F3/211 , H03F3/347 , H03F2200/294 , H03F2200/36 , H03F2200/372 , H03F2200/451
摘要： Techniques to improve low noise amplifiers (LNAs) with noise canceling are described. LNA includes a first (24) and a second (26) amplifier which work together to noise cancel the noise generated at an input stage circuit (22). The input stage circuit (22) receives an RF signal and is characterized by a first node and a second node. The first amplifier (24) converts a noise voltage at the first node into a first noise current at an output (220) of the first amplifier (24). The second amplifier (26) is directly coupled to the output of the first amplifier and provides noise canceling by summing the first noise current with a second noise current generated by the second amplifier as a function of the noise voltage at the second node. The proposed techniques eliminate the need for large ac coupling capacitors and reduce the die size occupied by the LNA. The elimination of ac coupling capacitors between amplification stages of the LNA allows current reuse resulting in reduced current consumption.
摘要翻译：描述了改进具有噪声消除的低噪声放大器（LNA）的技术。 LNA包括第一（24）和第二（26）放大器，其一起工作以抵消在输入级电路（22）处产生的噪声的噪声。输入级电路（22）接收RF信号，其特征在于第一节点和第二节点。第一放大器（24）将第一节点处的噪声电压转换为第一放大器（24）的输出端（220）处的第一噪声电流。第二放大器（26）直接耦合到第一放大器的输出，并且通过将第一噪声电流与由第二放大器产生的第二噪声电流相加作为第二节点处的噪声电压的函数来提供噪声消除。所提出的技术消除了对大型交流耦合电容器的需要，并且减小了LNA占用的管芯尺寸。在LNA的放大级之间消除交流耦合电容器允许电流重用，从而减少电流消耗。

5. 发明申请

WO2010129925A3 OVERLAPPING, TWO-SEGMENT CAPACITOR BANK FOR VCO FREQUENCY TUNING 审中-公开
标题翻译：用于VCO频率调谐的重叠，双段电容器库
公开(公告)号：WO2010129925A3
公开(公告)日：2010-11-11
申请号：PCT/US2010/034129
申请日：2010-05-07
申请人： QUALCOMM Incorporated , ZENG, Yi , PAN, Tzu-Wang , LIN, I-Hsiang
发明人： ZENG, Yi , PAN, Tzu-Wang , LIN, I-Hsiang
IPC分类号： H03B5/12
摘要： A VCO (for example, in an FM receiver) includes an LC resonant tank. The LC resonant tank includes a coarse tuning capacitor bank and a fine tuning capacitor bank. The coarse tuning capacitor bank contains a plurality of digitally controlled coarse tuning capacitor elements, each providing a first capacitance value when active. The fine tuning capacitor bank contains a plurality of digitally controlled fine tuning capacitor elements, each providing a second capacitance value when active. To address the practical problem of capacitor mismatch, capacitance overlap throughout the VCO tuning range is created by selecting the first and second capacitance values such that the capacitance value of the fine capacitor bank is greater than the first capacitance value when all of the digitally controlled fine tuning capacitor elements of the fine capacitor bank are active.
摘要翻译： VCO（例如，在FM接收器中）包括LC谐振回路。 LC谐振回路包括一个粗调电容器组和一个精调电容器组。粗调电容器组包含多个数字控制的粗调电容器元件，每个电容器元件在激活时提供第一电容值。微调电容器组包含多个数字控制微调电容器元件，每个电容器元件在激活时提供第二电容值。为了解决电容器失配的实际问题，通过选择第一和第二电容值产生整个VCO调谐范围内的电容重叠，使得精细电容器组的电容值大于第一电容值，当所有的数字控制精细微调电容器组的电容元件是有效的。

6. 发明申请

WO2010126844A1 JAMMER DETECTION BASED ADAPTIVE PLL BANDWIDTH ADJUSTMENT IN FM RECEIVER 审中-公开
标题翻译：基于JAMMER检测的FM接收器中的自适应PLL带宽调整
公开(公告)号：WO2010126844A1
公开(公告)日：2010-11-04
申请号：PCT/US2010/032455
申请日：2010-04-26
申请人： QUALCOMM Incorporated , ZENG, Yi , PAN, Tzu-wang , LIN, I-Hsiang , DUNWORTH, Jeremy , TRIKHA, Pushp , APTE, Rahul
发明人： ZENG, Yi , PAN, Tzu-wang , LIN, I-Hsiang , DUNWORTH, Jeremy , TRIKHA, Pushp , APTE, Rahul
IPC分类号： H04B1/10 , H03L7/107
CPC分类号： H04B1/1027
摘要： A frequency synthesizer within an FM receiver employs a Phase-Locked Loop (PLL) to generate a Local Oscillator (LO) signal. The LO signal is supplied to a mixer. The FM receiver also includes jammer detection functionality. If no jammer is detected, then the loop bandwidth of the PLL is set to have a relatively high value, thereby favoring suppression of in-band residual FM. If a jammer is detected, then the loop bandwidth of the PLL is set to have a relatively low value, thereby favoring suppression of out-of-band SSB phase noise. By adaptively changing loop bandwidth depending on whether a jammer is detected, performance requirements on sub-circuits within the PLL can be relaxed while still satisfying in-band residual FM and out-of-band SSB phase noise requirements. By allowing the VCO of the PLL to generate more phase noise due to the adaptive changing of loop bandwidth, VCO power consumption can be reduced.
摘要翻译： FM接收机内的频率合成器采用锁相环（PLL）来产生本地振荡器（LO）信号。 LO信号提供给混频器。 FM接收机还包括干扰检测功能。如果没有检测到干扰，则PLL的环路带宽被设置为具有相对较高的值，从而有利于抑制带内剩余FM。如果检测到干扰，则将PLL的环路带宽设置为具有相对较低的值，从而有利于抑制带外SSB相位噪声。通过根据是否检测到干扰信号来自适应地改变环路带宽，可以放宽PLL内的子电路的性能要求，同时仍然满足带内剩余FM和带外SSB相位噪声要求。通过允许PLL的VCO由于环路带宽的自适应变化而产生更多的相位噪声，可以降低VCO的功耗。

7. 发明申请

WO2010059872A3 FM TRANSMITTER AND NON-FM RECEIVER INTEGRATED ON SINGLE CHIP 审中-公开
公开(公告)号：WO2010059872A3
公开(公告)日：2010-05-27
申请号：PCT/US2009/065213
申请日：2009-11-19
申请人： QUALCOMM INCORPORATED , LIN, I-Hsiang , PAN, Tzu-Wang , ZENG, Yi
发明人： LIN, I-Hsiang , PAN, Tzu-Wang , ZENG, Yi
IPC分类号： H04B1/52
摘要： Exemplary embodiments include a frequency modulation (FM) transmitter and a non-FM receiver, which may be implemented on the same IC chip. The FM transmitter may include a digital FM modulator, a lowpass filter, an amplifier, and an LC tank circuit. The digital FM modulator may receive a digital input signal, perform FM modulation with the digital input signal, and provide a digital FM signal. The lowpass filter may filter the digital FM signal and provide a filtered FM signal. The amplifier may amplify the filtered FM signal and provide an output FM signal. The LC tank circuit may filter the output FM signal. The digital FM modulator may perform FM modulation by changing a variable divider ratio of a multi-modulus divider within a PLL. A delta-sigma modulator may receive the digital input signal and generate a modulator output signal used to obtain the variable divider ratio.

8. 发明公开

EP3788407A1 CONCURRENT SUPPORT FOR MULTIPLE FREQUENCY BANDS FOR SATELLITE NAVIGATION SIGNALS 审中-公开
公开(公告)号：EP3788407A1
公开(公告)日：2021-03-10
申请号：EP19729930.8
申请日：2019-04-25
申请人： QUALCOMM INCORPORATED
发明人： ZENG, Yi , KIM, Hong Sun , WANG, Cheng-Han
IPC分类号： G01S19/32 , G01S19/21 , H03D7/16 , H04B1/00 , H04B1/30 , H04K3/00

9. 发明公开

EP3516778A1 CONFIGURABLE MIXER 有权
公开(公告)号：EP3516778A1
公开(公告)日：2019-07-31
申请号：EP17758337.4
申请日：2017-08-14
申请人： Qualcomm Incorporated
发明人： CHOI, Kiyong , ZENG, Yi , KIM, Hong Sun , VUJCIC, Sasha , PATEL, Chirag Dipak , TASIC, Aleksandar Miodrag , GATHMAN, Timothy Donald , CHEN, Wu-Hsin , VAN ZALINGE, Klaas
IPC分类号： H04B1/10 , H03D7/14
摘要： A method and apparatus are disclosed for a configurable mixer capable of operating in a linear, a legacy, and a low-power mode. In the linear mode, the configurable mixer is configured to operate as a double-balanced mixer to multiply a first differential signal by a second differential signal. In the legacy mode, the configurable mixer is configured to as a double-balanced mixer to multiply a differential signal by a single-ended signal. In the low-power mode, the configurable mixer is configured to operate as a single-balanced mixer to multiply a differential signal by a single-ended signal. The operating mode of the configurable mixer may be based, at least in part, on a mode control signal. In some embodiments, the configurable mixer may be included in an analog front end of a wireless communication device.

10. 发明申请

WO2016028993A1 MULTI IQ-PATH SYNCHRONIZATION 审中-公开
标题翻译：多智能路径同步
公开(公告)号：WO2016028993A1
公开(公告)日：2016-02-25
申请号：PCT/US2015/046073
申请日：2015-08-20
申请人： QUALCOMM INCORPORATED
发明人： CHOI, Kiyong , YANG, Jeongsik , KO, Jin-Su , ZENG, Yi
IPC分类号： H04W56/00
CPC分类号： H04L27/2662 , H04L27/2627 , H04L27/2649 , H04W56/0035
摘要： Aspects of a wireless apparatus and a method for handling a modulated signal include a frequency generator that produces a clock signal, a first synchronization circuit that generates a first sync enable signal based on an even edge of the clock signal, a second synchronization circuit that generates a second sync enable signal based on an even edge of the clock signal, a first divider having a first initial operating condition that generates a first IQ path based on the first sync enable signal, and a second divider having a second initial operating condition that generates a second IQ path based on the second sync enable signal, wherein the first and second operating conditions are not equal when initially powered.
摘要翻译：无线装置和处理调制信号的方法的方面包括产生时钟信号的频率发生器，基于时钟信号的偶边产生第一同步使能信号的第一同步电路，产生基于所述时钟信号的偶边的第二同步使能信号，具有基于所述第一同步使能信号产生第一IQ路径的第一初始操作条件的第一分频器，以及产生第二初始操作条件的第二分频器，基于第二同步使能信号的第二IQ路径，其中当初始供电时，第一和第二操作条件不相等。

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