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1. 发明申请

WO2018031194A1 SYSTEMS AND METHODS PROVIDING AN INTERMODULATION DISTORTION SINK 审中-公开
标题翻译：提供交调失真水槽的系统和方法
公开(公告)号：WO2018031194A1
公开(公告)日：2018-02-15
申请号：PCT/US2017/042395
申请日：2017-07-17
申请人： QUALCOMM INCORPORATED
发明人： GATHMAN, Timothy Donald , PATEL, Chirag Dipak , VUJCIC, Sasha , TASIC, Aleksandar Miodrag , CHEN, Wu-Hsin , VAN ZALINGE, Klaas
IPC分类号： H03F1/32 , H03F1/08 , H03F3/193 , H03F3/30 , H03F3/45 , H03H11/32
CPC分类号： H03H11/32 , H03F1/086 , H03F1/3205 , H03F1/3217 , H03F1/3223 , H03F3/19 , H03F3/193 , H03F3/21 , H03F3/3022 , H03F3/45183 , H03F3/45237 , H03F3/45475 , H03F2200/06 , H03F2200/09 , H03F2200/129 , H03F2200/144 , H03F2200/18 , H03F2200/21 , H03F2200/24 , H03F2200/294 , H03F2200/321 , H03F2200/33 , H03F2200/42 , H03F2200/451 , H03F2200/453 , H03F2200/555 , H03F2203/30069 , H03F2203/45091 , H03F2203/45101 , H03F2203/45116 , H03F2203/45136 , H03F2203/45208 , H03F2203/45288 , H03F2203/45374 , H03F2203/45458 , H03F2203/45526 , H03F2203/45528 , H03F2203/45544 , H03F2203/45596 , H03F2203/45712 , H04L7/0337
摘要： A circuit includes an active balun having an RF signal input and having differential signal outputs, the active balun including a first pair of transistors coupled to the RF signal input, the first pair of transistors including a first transistor of a first type and a second transistor of a second type, wherein the first type and second type are complementary; and an intermodulation distortion (IMD) sink circuit having an operational amplifier (op amp) coupled between a first node and a second node, wherein the first transistor and second transistor are coupled in series between the first node and the second node.
摘要翻译：一种电路包括具有RF信号输入并且具有差分信号输出的有源平衡 - 不平衡变换器，所述有源平衡 - 不平衡变换器包括耦合到所述RF信号输入的第一对晶体管，所述第一对晶体管包括第一晶体管第一类型和第二类型的第二晶体管，其中第一类型和第二类型是互补的; 以及具有耦合在第一节点和第二节点之间的运算放大器（运算放大器）的互调失真（IMD）宿电路，其中第一晶体管和第二晶体管串联耦合在第一节点和第二节点之间。 >

2. 发明申请

WO2014209716A1 PSEUDO-CML LATCH AND DIVIDER HAVING REDUCED CHARGE SHARING BETWEEN OUTPUT NODES 审中-公开
标题翻译： PSEUDO-CML LATCH和DIVIDER在输出节点之间具有减少的充电共享
公开(公告)号：WO2014209716A1
公开(公告)日：2014-12-31
申请号：PCT/US2014/042935
申请日：2014-06-18
申请人： QUALCOMM INCORPORATED
发明人： CHEN, Wu-Hsin , LIU, Li , HU, Jianyun
IPC分类号： H03K3/356
CPC分类号： H03K3/017 , H01L21/823871 , H03K3/356121 , H03K3/356139
摘要： In one example, a high-speed divider (38) includes two identical pseudo-CML latches (L1, L2) and four output inverters (70-73). Each latch includes a pair of cross-coupled signal holding transistors (MN1, MN2, MN7, MN8). A first P-channel pull-up circuit (MP1, MP3) pulls up on a second output node QB of the latch. A second P-channel pull-up circuit (MP2, MP4) pulls up on a first output node Q of the latch. A pull-down circuit (MN3-5, MN9-11) involves four N-channel transistors. This pull-down circuit: 1) couples the QB node to ground when a clock signal CK is high and a data signal D is high, 2) couples the Q node to ground when CK is high and D is low, 3) prevents a transfer of charge between the QB and Q nodes through the pull-down circuit when D transitions during a time period when CK is low, and 4) decouples the QB and Q nodes from the pull-down circuit when CK is low.
摘要翻译：在一个示例中，高速分配器（38）包括两个相同的伪CML锁存器（L1，L2）和四个输出反相器（70-73）。每个锁存器包括一对交叉耦合的信号保持晶体管（MN1，MN2，MN7，MN8）。第一个P通道上拉电路（MP1，MP3）在锁存器的第二个输出节点QB上拉起。第二个P沟道上拉电路（MP2，MP4）在锁存器的第一个输出节点Q上拉起。下拉电路（MN3-5，MN9-11）涉及四个N沟道晶体管。该下拉电路：1）当时钟信号CK为高电平且数据信号D为高电平时，将QB节点耦合到地，2）当CK为高电平且D为低电平时将Q节点接地，3）防止当CK为低电平时，D转换时，通过下拉电路在QB和Q节点之间传输电荷;以及4）当CK为低电平时，将QB和Q节点与下拉电路解耦。

3. 发明授权

EP3497798B1 RECONFIGURABLE RADIO FREQUENCY (RF) BANDSTOP / INTERMEDIATE FREQUENCY (IF) BANDPASS FILTER 有权
公开(公告)号：EP3497798B1
公开(公告)日：2020-01-22
申请号：EP17745924.5
申请日：2017-07-17
申请人： Qualcomm Incorporated
发明人： GATHMAN, Timothy Donald , CHOKSI, Ojas , TASIC, Aleksandar Miodrag , VUJCIC, Sasha , PATEL, Chirag Dipak , CHEN, Wu-Hsin , VAN ZALINGE, Klaas
IPC分类号： H04B1/00 , H03H17/02 , H04B1/10

4. 发明公开

EP3014769A1 FREQUENCY DIVIDER WITH DUTY CYCLE ADJUSTMENT WITHIN FEEDBACK LOOP 审中-公开
标题翻译：且占空比设置分频器在反馈回路
公开(公告)号：EP3014769A1
公开(公告)日：2016-05-04
申请号：EP14736260.2
申请日：2014-06-18
申请人： Qualcomm Incorporated
发明人： CHEN, Wu-Hsin , SRIDHARA, Sriramgopal , LIU, Li
IPC分类号： H03K3/017 , H03K5/156 , H03K21/08
CPC分类号： H03L7/18 , H03K3/017 , H03K5/1565 , H03K21/08
摘要： A frequency divider (300) with duty cycle adjustment within a feedback loop is disclosed. In an exemplary design, an apparatus includes at least one divider circuit (310a, 310b) and at least one duty cycle adjustment circuit (320a, 320b) coupled in a feedback loop. The divider circuit(s) receive a clock signal (input Clock) at a first frequency and provide at least one divided signal (Idivp, Idivn) at a second frequency, which is a fraction of the first frequency. The duty cycle adjustment circuit(s) adjust the duty cycle of the at least one divided signal and provide at least one duty cycle adjusted signal (ladjp, ladjn) to the divider circuit(s). The divider circuit(s) may include first and second latches (310a, 310b), and the duty cycle adjustment circuit(s) may include first and second duty cycle adjustment circuits (320a, 320b). The first and second latches and the first and second duty cycle adjustment circuits may be coupled in a feedback loop and may perform divide-by-2.

5. 发明公开

EP3949114A1 SWING TRACKING AND CONTROL 审中-公开
公开(公告)号：EP3949114A1
公开(公告)日：2022-02-09
申请号：EP20722015.3
申请日：2020-03-31
申请人： QUALCOMM INCORPORATED
发明人： CHEN, Wu-Hsin , XU, Rui , VIGILANTE, Marco , LIU, Li , WU, Xiaotie
IPC分类号： H03B5/12 , H03F1/34

6. 发明申请

WO2018031195A1 RECONFIGURABLE RADIO FREQUENCY (RF) BANDSTOP / INTERMEDIATE FREQUENCY (IF) BANDPASS FILTER 审中-公开
标题翻译：可重构射频（RF）带阻滤波器/中频（IF）带通滤波器
公开(公告)号：WO2018031195A1
公开(公告)日：2018-02-15
申请号：PCT/US2017/042431
申请日：2017-07-17
申请人： QUALCOMM INCORPORATED
发明人： GATHMAN, Timothy Donald , CHOKSI, Ojas , TASIC, Aleksandar Miodrag , VUJCIC, Sasha , PATEL, Chirag Dipak , CHEN, Wu-Hsin , VAN ZALINGE, Klaas
IPC分类号： H04B1/00 , H03H17/02 , H04B1/10
CPC分类号： H03H11/0427 , H03F3/19 , H03F2200/294 , H03F2200/451 , H03H11/126 , H03H17/0294 , H03H2011/0483 , H03H2011/0488 , H04B1/0053 , H04B1/1036 , H04L5/0041 , H04W88/08
摘要： A reconfigurable filter circuit has a first path including a transimpedance amplifier (TIA). The transimpedance amplifier has an input that receives an input current and an output that outputs a voltage. The reconfigurable filter circuit also includes a switchable feedback path. The switchable feedback path includes a first low-pass filter coupled to an output of the TIA. The switchable feedback path also includes a first switch to couple the feedback path to provide a feedback current to the first path resulting in a bandpass response in the output voltage when the switch is closed and a low-pass response in the output voltage when the switch is open.
摘要翻译：可重构滤波器电路具有包括跨阻放大器（TIA）的第一路径。跨阻放大器具有接收输入电流的输入和输出电压的输出。可重构滤波器电路还包括可切换反馈路径。可切换的反馈路径包括耦合到TIA的输出的第一低通滤波器。可切换反馈路径还包括第一开关，用于耦合反馈路径以向第一路径提供反馈电流，从而导致当开关闭合时输出电压中的带通响应以及当开关闭合时输出电压中的低通响应已打开。

7. 发明申请

WO2014209715A1 FREQUENCY DIVIDER WITH DUTY CYCLE ADJUSTMENT WITHIN FEEDBACK LOOP 审中-公开
标题翻译：频率分频器在反馈环路中进行占空比调整
公开(公告)号：WO2014209715A1
公开(公告)日：2014-12-31
申请号：PCT/US2014/042920
申请日：2014-06-18
申请人： QUALCOMM INCORPORATED
发明人： CHEN, Wu-Hsin , SRIDHARA, Sriramgopal , LIU, Li
IPC分类号： H03K3/017 , H03K5/156 , H03K21/08
CPC分类号： H03L7/18 , H03K3/017 , H03K5/1565 , H03K21/08
摘要： A frequency divider (300) with duty cycle adjustment within a feedback loop is disclosed. In an exemplary design, an apparatus includes at least one divider circuit (310a, 310b) and at least one duty cycle adjustment circuit (320a, 320b) coupled in a feedback loop. The divider circuit(s) receive a clock signal (input Clock) at a first frequency and provide at least one divided signal (Idivp, Idivn) at a second frequency, which is a fraction of the first frequency. The duty cycle adjustment circuit(s) adjust the duty cycle of the at least one divided signal and provide at least one duty cycle adjusted signal (ladjp, ladjn) to the divider circuit(s). The divider circuit(s) may include first and second latches (310a, 310b), and the duty cycle adjustment circuit(s) may include first and second duty cycle adjustment circuits (320a, 320b). The first and second latches and the first and second duty cycle adjustment circuits may be coupled in a feedback loop and may perform divide-by-2.
摘要翻译：公开了一种在反馈环路内进行占空比调整的分频器（300）。在示例性设计中，装置包括耦合在反馈回路中的至少一个除法器电路（310a，310b）和至少一个占空比调整电路（320a，320b）。分频器电路以第一频率接收时钟信号（输入时钟），并以第二频率提供至少一个分频信号（Idivp，Idivn），其为第一频率的一部分。占空比调整电路调整至少一个分频信号的占空比，并向分频器电路提供至少一个占空比调整信号（ladjp，ladjn）。分频器电路可以包括第一和第二锁存器（310a，310b），并且占空比调整电路可以包括第一和第二占空比调整电路（320a，320b）。第一和第二锁存器以及第一和第二占空比调节电路可以耦合在反馈回路中并且可以执行除以2。

8. 发明申请

WO2018057148A1 CONFIGURABLE MIXER 审中-公开
标题翻译：可配置的混合器
公开(公告)号：WO2018057148A1
公开(公告)日：2018-03-29
申请号：PCT/US2017/046801
申请日：2017-08-14
申请人： QUALCOMM INCORPORATED
发明人： CHOI, Kiyong , ZENG, Yi , KIM, Hong Sun , VUJCIC, Sasha , PATEL, Chirag Dipak , TASIC, Aleksandar Miodrag , GATHMAN, Timothy Donald , CHEN, Wu-Hsin , VAN ZALINGE, Klaas
IPC分类号： H04B1/10 , H03D7/14
摘要： A method and apparatus are disclosed for a configurable mixer capable of operating in a linear, a legacy, and a low-power mode. In the linear mode, the configurable mixer is configured to operate as a double-balanced mixer to multiply a first differential signal by a second differential signal. In the legacy mode, the configurable mixer is configured to as a double-balanced mixer to multiply a differential signal by a single-ended signal. In the low-power mode, the configurable mixer is configured to operate as a single-balanced mixer to multiply a differential signal by a single-ended signal. The operating mode of the configurable mixer may be based, at least in part, on a mode control signal. In some embodiments, the configurable mixer may be included in an analog front end of a wireless communication device.
摘要翻译：公开了一种用于能够以线性，传统和低功率模式操作的可配置混频器的方法和设备。在线性模式中，可配置混频器被配置为作为双平衡混频器操作以将第一差分信号乘以第二差分信号。在传统模式中，可配置混频器被配置为双平衡混频器，以将差分信号乘以单端信号。在低功耗模式下，可配置混频器配置为作为单平衡混频器工作，以将差分信号与单端信号相乘。可配置混频器的操作模式可以至少部分地基于模式控制信号。在一些实施例中，可配置混频器可以被包括在无线通信设备的模拟前端中。

9. 发明申请

WO2015200135A1 FILTER WITH AN AUXILIARY MIXING PATH 审中-公开
标题翻译：过滤器与辅助混合路径
公开(公告)号：WO2015200135A1
公开(公告)日：2015-12-30
申请号：PCT/US2015/036738
申请日：2015-06-19
申请人： QUALCOMM INCORPORATED
发明人： WANG, Chuan , CHEN, Wu-Hsin , TASIC, Aleksandar Miodrag , KIM, Jusung
IPC分类号： H04B1/10
CPC分类号： H03D7/1466 , H03H7/38 , H03H2007/0192 , H04B1/1036 , H04B1/109 , H04B1/40 , H04B2001/1063
摘要： An apparatus includes an auxiliary mixing path configured to receive a differential signal. The apparatus also includes a filter having an input coupled to the auxiliary mixing path to filter jammer components of the received differential signal.
摘要翻译：一种装置包括配置成接收差分信号的辅助混合路径。该装置还包括滤波器，其具有耦合到辅助混合路径的输入端，以过滤接收的差分信号的干扰分量。

10. 发明公开

EP3516778A1 CONFIGURABLE MIXER 有权
公开(公告)号：EP3516778A1
公开(公告)日：2019-07-31
申请号：EP17758337.4
申请日：2017-08-14
申请人： Qualcomm Incorporated
发明人： CHOI, Kiyong , ZENG, Yi , KIM, Hong Sun , VUJCIC, Sasha , PATEL, Chirag Dipak , TASIC, Aleksandar Miodrag , GATHMAN, Timothy Donald , CHEN, Wu-Hsin , VAN ZALINGE, Klaas
IPC分类号： H04B1/10 , H03D7/14
摘要： A method and apparatus are disclosed for a configurable mixer capable of operating in a linear, a legacy, and a low-power mode. In the linear mode, the configurable mixer is configured to operate as a double-balanced mixer to multiply a first differential signal by a second differential signal. In the legacy mode, the configurable mixer is configured to as a double-balanced mixer to multiply a differential signal by a single-ended signal. In the low-power mode, the configurable mixer is configured to operate as a single-balanced mixer to multiply a differential signal by a single-ended signal. The operating mode of the configurable mixer may be based, at least in part, on a mode control signal. In some embodiments, the configurable mixer may be included in an analog front end of a wireless communication device.

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