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1. 发明申请

WO2011106349A1 SEMICONDUCTOR DEVICE WITH VIAS HAVING MORE THAN ONE MATERIAL 审中-公开
标题翻译：具有超过一种材料的VIAS的半导体器件
公开(公告)号：WO2011106349A1
公开(公告)日：2011-09-01
申请号：PCT/US2011/025813
申请日：2011-02-23
申请人： QUALCOMM Incorporated , GU, Shiqun , LI, Yiming , BEZUK, Steve, J.
发明人： GU, Shiqun , LI, Yiming , BEZUK, Steve, J.
IPC分类号： H01L23/48 , H01L23/532
CPC分类号： H01L23/481 , H01L23/53238 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A semiconductor die includes a via within a substrate material of the semiconductor die. The via includes a first conductive material having a first Coefficient of Thermal Expansion (CTE) and a second conductive material between the first conductive material and the substrate material of the semiconductor die. The second conductive material has a second CTE between the first CTE and a CTE of the substrate material of the semiconductor die. The first conductive material can be copper. The second conductive material can be tungsten and/or nickel. The substrate material can be silicon.
摘要翻译：半导体管芯包括在半导体管芯的衬底材料内的通孔。通孔包括具有第一热膨胀系数（CTE）的第一导电材料和位于第一导电材料和半导体管芯的衬底材料之间的第二导电材料。第二导电材料在第一CTE和半导体管芯的衬底材料的CTE之间具有第二CTE。第一导电材料可以是铜。第二导电材料可以是钨和/或镍。衬底材料可以是硅。

2. 发明申请

WO2012135832A3 VOLTAGE SWITCHABLE DIELECTRIC FOR DIE-LEVEL ELECTROSTATIC DISCHARGE (ESD) PROTECTION 审中-公开
公开(公告)号：WO2012135832A3
公开(公告)日：2012-10-04
申请号：PCT/US2012/031861
申请日：2012-04-02
申请人： QUALCOMM INCORPORATED , GU, Shiqun , RADOJCIC, Ratibor , LI, Yiming
发明人： GU, Shiqun , RADOJCIC, Ratibor , LI, Yiming
IPC分类号： H01L23/60 , H01L23/29 , H01L23/62 , H01L23/525
摘要： A voltage-switchable dielectric layer may be employed on a die for electrostatic discharge (ESD) protection. The voltage-switchable dielectric layer functions as a dielectric layer between terminals of the die during normal operation of the die. When ESD events occur at the terminals of the die, a high voltage between the terminals switches the voltage-switchable dielectric layer into a conducting layer to allow current to discharge to a ground terminal of the die without the current passing through circuitry of the die. Thus, damage to the circuitry of the die is reduced or prevented during ESD events on dies with the voltage-switchable dielectric layer. The voltage-switchable dielectric layer may be deposited on the back side of a die for protection during stacking with a second die to form a stacked IC.

3. 发明申请

WO2011127041A1 SELECTIVE PATTERNING FOR LOW COST THROUGH VIAS 审中-公开
标题翻译：通过VIAS低成本的选择性图案
公开(公告)号：WO2011127041A1
公开(公告)日：2011-10-13
申请号：PCT/US2011/031230
申请日：2011-04-05
申请人： QUALCOMM Incorporated , LI, Yiming , VELEZ, Mario Francisco , GU, Shiqun
发明人： LI, Yiming , VELEZ, Mario Francisco , GU, Shiqun
IPC分类号： H05K3/00 , H01L21/768 , H01L21/48
CPC分类号： H05K3/002 , H01L21/486 , H01L21/76898 , H01L23/15 , H01L23/49827 , H01L2924/0002 , H05K1/0306 , H05K3/386 , H05K2201/0394 , H01L2924/00
摘要： A block layer (304) deposited on a substrate (302) before deposition of metal lines (308) and etching of a through via (306) enables low cost fabrication of through vias in a substrate using isotropic etching processes. For example, wet etching of a glass substrate (302) may be used to fabricate through glass vias (306) without undercut from the wet etching shorting metal lines (308) on the glass substrate (302). The block layer (304) prevents contact between a conductive layer (310) lining the through via (306) with more than one metal line (308) on the substrate (302). The manufacturing process allows stacking of devices on substrates such as glass substrates and connecting the devices with through vias.
摘要翻译：在沉积金属线（308）和蚀刻通孔（306）之前沉积在基板（302）上的阻挡层（304）能够使用各向同性蚀刻工艺在基板中实现通孔的低成本制造。例如，玻璃基板（302）的湿蚀刻可以用于通过玻璃导孔（306）制造，而不会从玻璃基板（302）上的湿蚀刻短路金属线（308）的底切。阻挡层（304）防止在通孔（306）衬里的导电层（310）与衬底（302）上的多于一个金属线（308）之间的接触。制造过程允许在诸如玻璃基板的基板上堆叠设备并且将设备与通孔连接。

4. 发明申请

WO2011116326A1 THROUGH-SILICON VIA FABRICATION WITH ETCH STOP FILM 审中-公开
标题翻译：通过硅胶制成的薄膜
公开(公告)号：WO2011116326A1
公开(公告)日：2011-09-22
申请号：PCT/US2011/029058
申请日：2011-03-18
申请人： QUALCOMM Incorporated , GU, Shiqun , LI, Yiming , RAY, Urmi
发明人： GU, Shiqun , LI, Yiming , RAY, Urmi
IPC分类号： H01L21/768
CPC分类号： H01L21/76898
摘要： For a semiconductor wafer substrate (102) having an inter layer dielectric (110), a through - silicon via may be formed in the substrate by first depositing an etch stop film (202) on top of the inter layer dielectric, followed by etching an opening (204) through the etch stop film, the interlayer dielectric, and into the substrate. A dielectric liner (206) is then deposited over the etch stop film and into the opening. For some embodiments, the dielectric liner may be etched away except for those portions adhering to the sidewall of the opening. Then a conductive material (208) may be deposited into the opening and on the etch stop film. The excess conductive material may then be removed, and for some embodiments the etch stop film may also be removed.
摘要翻译：对于具有层间电介质（110）的半导体晶片基板（102），可以通过首先在层间电介质的顶部上沉积蚀刻停止膜（202），然后蚀刻通过蚀刻停止膜，层间电介质，并进入衬底的开口（204）。然后将电介质衬垫（206）沉积在蚀刻停止膜上并进入开口中。对于一些实施例，除了粘附到开口的侧壁上的那些部分之外，电介质衬垫可被蚀刻掉。然后可以将导电材料（208）沉积到开口中和蚀刻停止膜上。然后可以除去过量的导电材料，并且对于一些实施例，也可以去除蚀刻停止膜。

5. 发明申请

WO2010144848A3 STRESS BALANCE LAYER ON SEMICONDUCTOR WAFER BACKSIDE 审中-公开
公开(公告)号：WO2010144848A3
公开(公告)日：2010-12-16
申请号：PCT/US2010/038383
申请日：2010-06-11
申请人： QUALCOMM Incorporated , GU, Shiqun , CHANDRASEKARAN, Arvind , RAY, Urmi , LI, Yiming
发明人： GU, Shiqun , CHANDRASEKARAN, Arvind , RAY, Urmi , LI, Yiming
IPC分类号： H01L23/00
摘要： A semiconductor component (such as a semiconductor wafer or semiconductor die) includes a substrate having a front side and a back side. The semiconductor die/wafer also includes a stress balance layer on the back side of the substrate. An active layer deposited on the front side of the substrate creates an unbalanced stress in the semiconductor wafer/die. The stress balance layer balances stress in the semiconductor wafer/die. The stress in the stress balance layer approximately equals the stress in the active layer. Balancing stress in the semiconductor component prevents warpage of the semiconductor wafer/die.

6. 发明申请

WO2011116325A1 THROUGH GLASS VIA MANUFACTURING PROCESS 审中-公开
标题翻译：通过制造过程的玻璃
公开(公告)号：WO2011116325A1
公开(公告)日：2011-09-22
申请号：PCT/US2011/029057
申请日：2011-03-18
申请人： QUALCOMM Incorporated , GU, Shiqun , LI, Xia , LI, Yiming
发明人： GU, Shiqun , LI, Xia , LI, Yiming
IPC分类号： H01L21/48 , H01L23/15 , H01L23/498
CPC分类号： H01L23/15 , H01L21/486 , H01L23/49827 , H01L2924/0002 , H05K3/0041 , Y10T428/24273 , H01L2924/00
摘要： Fabrication of a through glass via in a relatively thick glass substrate includes patterning a through glass via hard mask on a surface of the glass substrate. The fabrication also includes wet etching a portion of the glass substrate, through the hard mask, to create a partial through glass via. The wet etching may involve applying a vapor of an oxide etch chemical, such as HF and XeF6, or applying a wet oxide etch chemical, such as HF and XeF6. The fabrication further includes passivating the etched partial through glass via, removing bottom passivation from the partial through glass via, and repeating the etching, passivating and removing to create the through glass via. The resulting through glass via has a scalloped side wall, a vertical profile and a high aspect ratio.
摘要翻译：在相对厚的玻璃基板中制造直通玻璃通孔包括在玻璃基板的表面上通过硬掩模图案化通孔玻璃。该制造还包括通过硬掩模湿法蚀刻玻璃基底的一部分，以产生部分透过玻璃通孔。湿蚀刻可以包括施加氧化物蚀刻化学品的蒸气，例如HF和XeF 6，或者施加湿氧化物蚀刻化学品，例如HF和XeF 6。该制造还包括钝化蚀刻的部分通过玻璃通孔，从部分通过玻璃通孔去除底部钝化，并重复蚀刻，钝化和去除以产生通孔玻璃通孔。所产生的通过玻璃通孔具有扇形侧壁，垂直轮廓和高纵横比。

7. 发明申请

WO2011009063A1 BARRIER LAYER ON POLYMER PASSIVATION FOR INTEGRATED CIRCUIT PACKAGING 审中-公开
标题翻译：用于集成电路封装的聚合物钝化器的阻挡层
公开(公告)号：WO2011009063A1
公开(公告)日：2011-01-20
申请号：PCT/US2010/042310
申请日：2010-07-16
申请人： QUALCOMM Incorporated , GU, Shiqun , RAY, Urmi , LI, Yiming , CHANDREASKARAN, Arvind
发明人： GU, Shiqun , RAY, Urmi , LI, Yiming , CHANDREASKARAN, Arvind
IPC分类号： H01L23/31 , H01L21/68
CPC分类号： H01L23/3192 , H01L21/6836 , H01L23/3142 , H01L24/11 , H01L24/13 , H01L24/94 , H01L2221/6834 , H01L2224/10126 , H01L2224/1147 , H01L2224/1191 , H01L2224/13022 , H01L2224/13099 , H01L2224/16225 , H01L2224/94 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01033 , H01L2924/14 , H01L2924/1433 , H01L2224/11 , H01L2224/03
摘要： A barrier layer deposited on the passivation layer of a semiconductor die decreases adhesion of glue used during stacking of semiconductor dies by altering chemical or structural properties of the passivation layer. During detachment of a carrier wafer from a wafer, the barrier layer reduces glue residue on the wafer by modifying the surface of the passivation layer. The barrier layer may be insulating films such as silicon dioxide, silicon nitride, silicon carbide, polytetrafluoroethylene, organic layers, or epoxy and may be less than two micrometers in thickness. Additionally, the barrier layer may be used to reduce topography of the semiconductor die to decrease adhesion of glues.
摘要翻译：沉积在半导体管芯的钝化层上的阻挡层通过改变钝化层的化学或结构特性来降低在半导体管芯堆叠期间使用的胶粘附力。在从晶片分离载体晶片时，阻挡层通过改变钝化层的表面来减少晶片上的胶残余物。阻挡层可以是诸如二氧化硅，氮化硅，碳化硅，聚四氟乙烯，有机层或环氧树脂之类的绝缘膜，并且其厚度可以小于2微米。此外，阻挡层可以用于减少半导体管芯的形貌以降低胶粘剂的粘附。

8. 发明申请

WO2015027442A1 CONTENT SELECTION WITH PRECISION CONTROLS 审中-公开
标题翻译：内容选择与精密控制
公开(公告)号：WO2015027442A1
公开(公告)日：2015-03-05
申请号：PCT/CN2013/082620
申请日：2013-08-30
申请人： GOOGLE INC. , GE, Rong , SHENG, Yong , ASUNCION, Arthur , KRAFCIK, Jonathan, Michael , LI, Yiming
发明人： GE, Rong , SHENG, Yong , ASUNCION, Arthur , KRAFCIK, Jonathan, Michael , LI, Yiming
IPC分类号： G06F13/10
CPC分类号： G06Q30/0244 , G06Q30/0255
摘要： Systems and methods for content selection with precision controls include receiving a content selection parameter value and a degree of precision specified by a content provider. A content selection parameter value for a device identifier may be predicted using a predictive model. A precision factor may be associated with the predicted content selection parameter value. Content from the provider may be selected based on a comparison between the predicted selection parameter value and precision factor for the device identifier and the selection parameter value and degree of precision specified by the content provider.
摘要翻译：具有精确控制的内容选择的系统和方法包括接收内容选择参数值和由内容提供者指定的精度度。可以使用预测模型来预测用于设备标识符的内容选择参数值。精度因子可以与预测内容选择参数值相关联。可以基于预测的选择参数值和设备标识符的精度因数与内容提供者指定的选择参数值和精度之间的比较来选择来自提供者的内容。

9. 发明公开

EP2695190A2 VOLTAGE SWITCHABLE DIELECTRIC FOR DIE-LEVEL ELECTROSTATIC DISCHARGE (ESD) PROTECTION 审中-公开
标题翻译：电压开关介电保护静电对芯片级
公开(公告)号：EP2695190A2
公开(公告)日：2014-02-12
申请号：EP12720020.2
申请日：2012-04-02
申请人： Qualcomm Incorporated
发明人： GU, Shiqun , RADOJCIC, Ratibor , LI, Yiming
IPC分类号： H01L23/60
CPC分类号： H01L23/62 , H01L23/29 , H01L23/60 , H01L24/05 , H01L24/06 , H01L24/16 , H01L25/0657 , H01L2224/0401 , H01L2224/05567 , H01L2224/0557 , H01L2224/06181 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/12042 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： A voltage-switchable dielectric layer may be employed on a die for electrostatic discharge (ESD) protection. The voltage-switchable dielectric layer functions as a dielectric layer between terminals of the die during normal operation of the die. When ESD events occur at the terminals of the die, a high voltage between the terminals switches the voltage-switchable dielectric layer into a conducting layer to allow current to discharge to a ground terminal of the die without the current passing through circuitry of the die. Thus, damage to the circuitry of the die is reduced or prevented during ESD events on dies with the voltage-switchable dielectric layer. The voltage-switchable dielectric layer may be deposited on the back side of a die for protection during stacking with a second die to form a stacked IC.

10. 发明公开

EP2556730A1 SELECTIVE PATTERNING FOR LOW COST THROUGH VIAS 审中-公开
标题翻译：选择结构为成本经文
公开(公告)号：EP2556730A1
公开(公告)日：2013-02-13
申请号：EP11713973.3
申请日：2011-04-05
申请人： Qualcomm Incorporated
发明人： LI, Yiming , VELEZ, Mario Francisco , GU, Shiqun
IPC分类号： H05K3/00 , H01L21/768 , H01L21/48
CPC分类号： H05K3/002 , H01L21/486 , H01L21/76898 , H01L23/15 , H01L23/49827 , H01L2924/0002 , H05K1/0306 , H05K3/386 , H05K2201/0394 , H01L2924/00
摘要： A block layer (304) deposited on a substrate (302) before deposition of metal lines (308) and etching of a through via (306) enables low cost fabrication of through vias in a substrate using isotropic etching processes. For example, wet etching of a glass substrate (302) may be used to fabricate through glass vias (306) without undercut from the wet etching shorting metal lines (308) on the glass substrate (302). The block layer (304) prevents contact between a conductive layer (310) lining the through via (306) with more than one metal line (308) on the substrate (302). The manufacturing process allows stacking of devices on substrates such as glass substrates and connecting the devices with through vias.

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