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1. 发明申请

WO2017139410A1 INTEGRATED DEVICE COMPRISING A CAPACITOR THAT INCLUDES MULTIPLE PINS AND AT LEAST ONE PIN THAT TRAVERSES A PLATE OF THE CAPACITOR 审中-公开
标题翻译：包含电容器的集成器件，该电容器包括多个引脚并且至少一个引脚穿过电容器板
公开(公告)号：WO2017139410A1
公开(公告)日：2017-08-17
申请号：PCT/US2017/017059
申请日：2017-02-08
申请人： QUALCOMM INCORPORATED
发明人： GU, Shiqun , PANDEY, Shree Krishna , RADOJCIC, Ratibor
IPC分类号： H01L23/64 , H01L23/498 , H01L23/538 , H01L21/60 , H01L49/02
CPC分类号： H01L23/49838 , H01L21/4846 , H01L21/568 , H01L23/3128 , H01L23/49822 , H01L23/5389 , H01L23/642 , H01L24/17 , H01L24/19 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/16238 , H01L2224/16268 , H01L2224/18 , H01L2924/05042 , H01L2924/15311 , H01L2924/19011 , H01L2924/19041 , H01L2924/19102
摘要： Some features pertain to an integrated device that includes a die and a first redistribution portion coupled to the die. The first redistribution portion includes at least one dielectric layer and a capacitor. The capacitor includes a first plate, a second plate, and an insulation layer located between the first plate and the second plate. The first redistribution portion further includes several first pins coupled to the first plate of the capacitor. The first redistribution portion further includes several second pins coupled to the second plate of the capacitor. In some implementations, the capacitor includes the first pins and/or the second pins. In some implementations, at least one pin from the several first pins traverses through the second plate to couple to the first plate of the capacitor. In some implementations, the second plate comprises a fin design.
摘要翻译：一些特征涉及包括管芯和耦合到管芯的第一重新分配部分的集成器件。第一重新分配部分包括至少一个介电层和电容器。电容器包括第一板，第二板以及位于第一板和第二板之间的绝缘层。第一重新分配部分还包括耦合到电容器的第一板的多个第一引脚。第一重新分配部分还包括耦合到电容器的第二板的若干第二引脚。在一些实现中，电容器包括第一引脚和/或第二引脚。在一些实施方式中，来自多个第一引脚的至少一个引脚横穿第二板以耦合到电容器的第一板。在一些实现中，第二板包括翅片设计。

2. 发明公开

EP3341966A1 INTEGRATED CIRCUIT (IC) PACKAGE COMPRISING ELECTROSTATIC DISCHARGE (ESD) PROTECTION 审中-公开
公开(公告)号：EP3341966A1
公开(公告)日：2018-07-04
申请号：EP16760343.0
申请日：2016-08-26
申请人： Qualcomm Incorporated
发明人： GU, Shiqun , WORLEY, Eugene Robert , RADOJCIC, Ratibor , RAY, Urmi
IPC分类号： H01L23/60 , H01L23/62 , H01L23/48 , H01L27/02
CPC分类号： H02H9/046 , H01L23/48 , H01L23/60 , H01L23/62 , H01L27/0255 , H01L27/0292 , H01L27/0296 , H01L2224/16225 , H01L2924/15311 , H01L2924/181 , H02H9/044 , H01L2924/00012
摘要： An integrated circuit (IC) package includes a die, a package substrate coupled to the die, and a first electrostatic discharge (ESD) protection component coupled to the package substrate, where the first electrostatic discharge (ESD) protection component is configured to provide package level electrostatic discharge (ESD) protection. In some implementations, the first electrostatic discharge (ESD) protection component is embedded in the package substrate. In some implementations, the die includes an internal electrostatic discharge (ESD) protection component configured to provide die level electrostatic discharge (ESD) protection. In some implementations, the internal electrostatic discharge (ESD) protection component and the first electrostatic discharge (ESD) protection component are configured to provide cumulative electrostatic discharge (ESD) protection for the die.

3. 发明申请

WO2014126818A1 DUAL SUBSTRATE, POWER DISTRIBUTION AND THERMAL SOLUTION FOR DIRECT STACKED INTEGRATED DEVICES 审中-公开
标题翻译：直接堆叠集成设备的双基板，功率分配和热解决方案
公开(公告)号：WO2014126818A1
公开(公告)日：2014-08-21
申请号：PCT/US2014/015422
申请日：2014-02-07
申请人： QUALCOMM INCORPORATED
发明人： HENDERSON, Brian Matthew , LISK, Durodami Joscelyn , GU, Shiqun , RADOJCIC, Ratibor , NOWAK, Matthew Michael
IPC分类号： H01L25/065 , H01L23/31 , H01L23/36 , H01L23/538 , H01L23/528 , H01L23/48
CPC分类号： H01L23/5384 , H01L21/50 , H01L23/3128 , H01L23/34 , H01L23/36 , H01L23/481 , H01L23/49811 , H01L23/5286 , H01L23/5383 , H01L23/5389 , H01L24/19 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/73259 , H01L2224/92224 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06544 , H01L2225/06548 , H01L2225/06586 , H01L2225/06589 , H01L2924/15184 , H01L2924/15311
摘要： Some implementations provide an integrated device (400) that includes a first substrate (402), a first die (404) coupled to the first substrate, a second die (406) coupled to the first die, and a second substrate (409) coupled to the second die. The second substrate is configured to provide an electrical path for a signal to the second die. The integrated device further includes a molding (408) surrounding the first die and the second die, and several through mold vias (TMVs) coupled to the second substrate. The TMVs (414, 416) are configured to provide an electrical path for the signal to the second die through the second substrate. In some implementations, the second substrate includes a signal distribution structure (411, 412) configured to provide the electrical path for the signal to the second die. In some implementations, the first substrate and the second substrate are part of a signal distribution network that provides signal to the second die.
摘要翻译：一些实施方案提供了集成器件（400），其包括第一衬底（402），耦合到第一衬底的第一裸片（404），耦合到第一裸片的第二裸片（406）和耦合到第一裸片到第二个死亡第二基板被配置为提供用于到第二管芯的信号的电路径。集成装置还包括围绕第一管芯和第二管芯的模制件（408）以及耦合到第二基板的多个通孔（TMV）。 TMV（414,416）被配置为提供通过第二基板的信号到第二管芯的电路径。在一些实施方式中，第二衬底包括被配置为向第二管芯提供信号的电路的信号分配结构（411,412）。在一些实施方案中，第一衬底和第二衬底是向第二裸片提供信号的信号分配网络的一部分。

4. 发明申请

WO2013163177A1 THERMAL MANAGEMENT FLOORPLAN FOR A MULTI-TIER STACKED IC PACKAGE 审中-公开
标题翻译：用于多层堆叠IC封装的热管理FLOORPLAN
公开(公告)号：WO2013163177A1
公开(公告)日：2013-10-31
申请号：PCT/US2013/037790
申请日：2013-04-23
申请人： QUALCOMM INCORPORATED
发明人： LISK, Durodami, J. , CHIRIAC, Victor, A. , RADOJCIC, Ratibor
IPC分类号： H01L25/065 , H01L23/36
CPC分类号： H05K13/00 , H01L23/36 , H01L23/433 , H01L25/0657 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2225/06562 , H01L2225/06589 , H01L2924/00014 , H05K7/2039 , Y10T29/49124 , H01L2224/0401
摘要： A first tier die (402A) is provided having a thermal management floorplan with a heat region (402A_HT) having an area for thermal coupling to a heat sink (430), a second tier die (404A) is provided, shaped and dimensioned to be stackable into a multi-tier stack with the first tier die and, when stacked in the multi-tier stack, to not substantially overlap the heat region. A heat sink is provided, and a thermal coupling element (420), the heat sink, a stack having the first tier die and the second tier die are arranged to form the multi-tier stacked integrated circuit. In the arrangement, the thermal coupling element is located to form a thermal path from the heat region of the first tier die to the heat sink.
摘要翻译：提供具有热管理平面图的第一层模具（402A），其具有热区域（402A_HT），所述热区域具有用于热耦合到散热器（430）的区域，第二层模具（404A）被设计成形状和尺寸为可堆叠成具有第一层裸片的多层堆叠，并且当堆叠在多层堆叠中时，不能基本上重叠热区域。提供散热器，并且布置热耦合元件（420），散热器，具有第一层管芯和第二层管芯的堆叠以形成多层堆叠集成电路。在该布置中，热耦合元件被定位成形成从第一层模具的热区域到散热器的热路径。

5. 发明申请

WO2011020038A3 INTERCONNECT STRUCTURE WITH ELEMENTS OF VARYING HEIGHT OR DIFFERENT MATERIALS THAT ALLOWS A BALANCED STRESS TO PREVENT THIN DIE WARPAGE 审中-公开
公开(公告)号：WO2011020038A3
公开(公告)日：2011-02-17
申请号：PCT/US2010/045499
申请日：2010-08-13
申请人： QUALCOMM INCORPORATED , CHANDRASEKARAN, Arvind , RADOJCIC, Ratibor
发明人： CHANDRASEKARAN, Arvind , RADOJCIC, Ratibor
IPC分类号： H01L23/485 , H01L21/60
摘要： A packaged semiconductor product (600,800,900,1000 ) includes a packaging substrate (510,710,910,1010 ) coupled to a semiconductor die (540,740,940,1040) through an interconnect structure. Interconnect structure elements (530,730,930,1030) may be pillars of similar heights prior to reflow and manufactured from different materials or bumps of different heights before reflow. The interconnect structure elements induce a reverse bend on the semiconductor die that mitigates warpage of the semiconductor die during semiconductor assembly by balancing bending of the packaging substrate during reflow.

6. 发明公开

EP3140861A1 SUBSTRATE BLOCK FOR PoP PACKAGE 审中-公开
标题翻译： SUBSTRATBLOCKFÜRPOP-VERPACKUNG
公开(公告)号：EP3140861A1
公开(公告)日：2017-03-15
申请号：EP15723397.4
申请日：2015-05-05
申请人： Qualcomm Incorporated
发明人： WE, Hong Bok , KIM, Dong Wook , LEE, Jae Sik , GU, Shiqun , RADOJCIC, Ratibor
IPC分类号： H01L23/498 , H01L23/538 , H01L25/10 , H01L23/00 , H01L21/56 , H01L25/00
CPC分类号： H01L23/49827 , H01L21/31127 , H01L21/561 , H01L21/565 , H01L21/78 , H01L23/3107 , H01L23/3128 , H01L23/498 , H01L23/49866 , H01L23/5226 , H01L23/528 , H01L23/5385 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/97 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13118 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/16235 , H01L2224/81411 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81466 , H01L2224/81484 , H01L2224/81801 , H01L2224/81815 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06548 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2225/107 , H01L2924/01014 , H01L2924/01029 , H01L2924/141 , H01L2924/143 , H01L2924/1433 , H01L2924/15311 , H01L2924/15331 , H01L2924/157 , H01L2924/15788 , H01L2924/1579 , H01L2924/20648 , H01L2924/3511 , H05K1/09 , H05K1/115 , H05K2201/09563 , H01L2924/014 , H01L2224/81
摘要： A substrate block is provided that has an increased width. The substrate block comprises two substrate bars, and the substrate bars each comprise a substrate and a plurality of filled vias through the substrate. The substrate block may be used to manufacture package substrates, and these package substrate may be incorporated into a PoP structure. The package substrate includes a carrier having a plurality of vertical interconnections and a bar coupled to the vertical interconnections.
摘要翻译：提供了具有增加的宽度的衬底块。衬底块包括两个衬底条，并且衬底条各自包括衬底和穿过衬底的多个填充的通孔。衬底块可用于制造封装衬底，并且这些封装衬底可以并入PoP结构中。封装衬底包括具有多个垂直互连的载体和耦合到垂直互连的条。

7. 发明公开

EP3140860A1 INTEGRATED DEVICE COMPRISING HIGH DENSITY INTERCONNECTS IN INORGANIC LAYERS AND REDISTRIBUTION LAYERS IN ORGANIC LAYERS 审中-公开
标题翻译：在层中的高密度无机化合物和重分布层中的有机层的集成器件
公开(公告)号：EP3140860A1
公开(公告)日：2017-03-15
申请号：EP15719392.1
申请日：2015-04-17
申请人： Qualcomm Incorporated
发明人： GU, Shiqun , RADOJCIC, Ratibor , KIM, Dong Wook , LEE, Jae Sik
IPC分类号： H01L23/498 , H01L21/48 , H05K3/46 , H01L21/56 , H01L23/14 , H01L25/065 , H01L25/10 , H01L21/60
CPC分类号： H01L21/568 , H01L21/4857 , H01L21/486 , H01L21/56 , H01L21/76802 , H01L21/76877 , H01L23/145 , H01L23/15 , H01L23/3107 , H01L23/481 , H01L23/49811 , H01L23/49838 , H01L23/5384 , H01L23/5385 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/0655 , H01L25/105 , H01L25/50 , H01L2224/023 , H01L2224/131 , H01L2224/13147 , H01L2224/16055 , H01L2224/16057 , H01L2224/16227 , H01L2224/16238 , H01L2224/171 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2224/81895 , H01L2224/81896 , H01L2224/83005 , H01L2224/92125 , H01L2225/1023 , H01L2225/1058 , H01L2924/01029 , H01L2924/1434 , H01L2924/1517 , H01L2924/15192 , H01L2924/15311 , H01L2924/1533 , H01L2924/18161 , H05K3/4688 , H01L2924/014
摘要： An integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die (206) (e.g., first wafer level die), and a second die (208) (e.g., second wafer level die). The base portion includes a first inorganic dielectric layer (203), a first set of interconnects (280) located in the first inorganic dielectric layer, a second dielectric layer (202) different from the first inorganic dielectric layer, and a set of redistribution metal layers (230,240,250,260) in the second dielectric layer. The first die is coupled to a first surface of the base portion. The second die is coupled to the first surface of the base portion, the second die is electrically coupled to the first die through the first set of interconnects (280).
摘要翻译：一些新颖的特征涉及在集成的装置（例如，集成的封装）那样包括用于集成装置，第一对（例如，第一晶片级模）的基部，和一个第二即（E. G.，第二晶片级模）。基座部分包括第一无机介电层，第一组位于所述第一无机介电层中的互连，第二介电层从所述第一无机介电层不同，并且所述第二介电层中的一组再分布金属层。第一个是连接到所述底座部分的第一表面上。第二，其耦合到所述底座部分的第一表面，第二个是电通过所述第一组互连耦合到所述第一。

8. 发明申请

WO2017035510A1 INTEGRATED CIRCUIT (IC) PACKAGE COMPRISING ELECTROSTATIC DISCHARGE (ESD) PROTECTION 审中-公开
标题翻译：包含静电放电（ESD）保护的集成电路（IC）封装
公开(公告)号：WO2017035510A1
公开(公告)日：2017-03-02
申请号：PCT/US2016/049123
申请日：2016-08-26
申请人： QUALCOMM INCORPORATED
发明人： GU, Shiqun , WORLEY, Eugene Robert , RADOJCIC, Ratibor , RAY, Urmi
IPC分类号： H01L23/60 , H01L23/62 , H01L23/48 , H01L27/02
CPC分类号： H02H9/046 , H01L23/48 , H01L23/60 , H01L23/62 , H01L27/0255 , H01L27/0292 , H01L27/0296 , H01L2224/16225 , H01L2924/15311 , H01L2924/181 , H02H9/044 , H01L2924/00012
摘要： An integrated circuit (IC) package includes a die, a package substrate coupled to the die, and a first electrostatic discharge (ESD) protection component coupled to the package substrate, where the first electrostatic discharge (ESD) protection component is configured to provide package level electrostatic discharge (ESD) protection. In some implementations, the first electrostatic discharge (ESD) protection component is embedded in the package substrate. In some implementations, the die includes an internal electrostatic discharge (ESD) protection component configured to provide die level electrostatic discharge (ESD) protection. In some implementations, the internal electrostatic discharge (ESD) protection component and the first electrostatic discharge (ESD) protection component are configured to provide cumulative electrostatic discharge (ESD) protection for the die.
摘要翻译：集成电路（IC）封装包括管芯，耦合到管芯的封装衬底和耦合到封装衬底的第一静电放电（ESD）保护部件，其中第一静电放电（ESD）保护部件被配置为提供封装级静电放电（ESD）保护。在一些实施方案中，第一静电放电（ESD）保护组件嵌入在封装衬底中。在一些实施方案中，管芯包括配置成提供管芯级静电放电（ESD）保护的内部静电放电（ESD）保护部件。在一些实施方案中，内部静电放电（ESD）保护部件和第一静电放电（ESD）保护部件被配置为为管芯提供累积静电放电（ESD）保护。

9. 发明申请

WO2014168946A1 LOW COST INTERPOSER COMPRISING AN OXIDATION LAYER 审中-公开
标题翻译：包含氧化层的低成本间隙器
公开(公告)号：WO2014168946A1
公开(公告)日：2014-10-16
申请号：PCT/US2014/033329
申请日：2014-04-08
申请人： QUALCOMM INCORPORATED
发明人： GU, Shiqun , RAY, Urmi , CHEN, Roawen , HENDERSON, Brian Matthew , RADOJCIC, Ratibor , NOWAK, Matthew , YU, Nicholas
IPC分类号： H01L23/498 , H01L21/48
CPC分类号： H01L23/49811 , H01L21/486 , H01L23/147 , H01L23/49827 , H01L2224/16225 , H01L2924/15311
摘要： Some implementations provide an interposer that includes a substrate, a via in the substrate, and an oxidation layer. The via includes a metal material. The oxidation layer is between the via and the substrate. In some implementations, the substrate is a silicon substrate. In some implementations, the oxidation layer is a thermal oxide formed by exposing the substrate to heat. In some implementations, the oxidation layer is configured to provide electrical insulation between the via and the substrate. In some implementations, the interposer also includes an insulation layer. In some implementations, the insulation layer is a polymer layer. In some implementations, the interposer also includes at least one interconnect on the surface of the interposer. The at least one interconnect is positioned on the surface of the interposer such that the oxidation layer is between the interconnect and the substrate.
摘要翻译：一些实施方案提供了一种插入器，其包括衬底，衬底中的通孔和氧化层。通孔包括金属材料。氧化层位于通孔和衬底之间。在一些实施方式中，衬底是硅衬底。在一些实施方案中，氧化层是通过将基底暴露于热而形成的热氧化物。在一些实施方案中，氧化层被配置为在通孔和基底之间提供电绝缘。在一些实施方案中，插入件还包括绝缘层。在一些实施方案中，绝缘层是聚合物层。在一些实现中，插入器还包括在插入器的表面上的至少一个互连。所述至少一个互连件位于所述插入件的表面上，使得所述氧化层位于所述互连件和所述基板之间。

10. 发明申请

WO2012135832A3 VOLTAGE SWITCHABLE DIELECTRIC FOR DIE-LEVEL ELECTROSTATIC DISCHARGE (ESD) PROTECTION 审中-公开
公开(公告)号：WO2012135832A3
公开(公告)日：2012-10-04
申请号：PCT/US2012/031861
申请日：2012-04-02
申请人： QUALCOMM INCORPORATED , GU, Shiqun , RADOJCIC, Ratibor , LI, Yiming
发明人： GU, Shiqun , RADOJCIC, Ratibor , LI, Yiming
IPC分类号： H01L23/60 , H01L23/29 , H01L23/62 , H01L23/525
摘要： A voltage-switchable dielectric layer may be employed on a die for electrostatic discharge (ESD) protection. The voltage-switchable dielectric layer functions as a dielectric layer between terminals of the die during normal operation of the die. When ESD events occur at the terminals of the die, a high voltage between the terminals switches the voltage-switchable dielectric layer into a conducting layer to allow current to discharge to a ground terminal of the die without the current passing through circuitry of the die. Thus, damage to the circuitry of the die is reduced or prevented during ESD events on dies with the voltage-switchable dielectric layer. The voltage-switchable dielectric layer may be deposited on the back side of a die for protection during stacking with a second die to form a stacked IC.

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