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1. 发明授权

US09678758B2 Coprocessor for out-of-order loads 有权
公开(公告)号：US09678758B2
公开(公告)日：2017-06-13
申请号：US14499044
申请日：2014-09-26
申请人： QUALCOMM Incorporated
发明人： Lucian Codrescu , Christopher Edward Koob , Eric Wayne Mahurin , Suresh Kumar Venkumahanti
IPC分类号： G06F9/312 , G06F15/76 , G06F15/80 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3877 , G06F9/30036 , G06F9/30043 , G06F9/3814 , G06F9/3824 , G06F9/3836 , G06F9/3887 , G06F15/8053
摘要： Systems and methods for implementing certain load instructions, such as vector load instructions by cooperation of a main processor and a coprocessor. The load instructions which are identified by the main processor for offloading to the coprocessor are committed in the main processor without receiving corresponding load data. Post-commit, the load instructions are processed in the coprocessor, such that latencies incurred in fetching the load data are hidden from the main processor. By implementing an out-of-order load data buffer associated with an in-order instruction buffer, the coprocessor is also configured to avoid stalls due to long latencies which may be involved in fetching the load data from levels of memory hierarchy, such as L2, L3, L4 caches, main memory, etc.

2. 发明申请

US20150324239A1 DYNAMIC LOAD BALANCING OF HARDWARE THREADS IN CLUSTERED PROCESSOR CORES USING SHARED HARDWARE RESOURCES, AND RELATED CIRCUITS, METHODS, AND COMPUTER-READABLE MEDIA 审中-公开
标题翻译：使用共享硬件资源的集群处理器芯片中的硬件线路的动态负载平衡以及相关电路，方法和计算机可读介质
公开(公告)号：US20150324239A1
公开(公告)日：2015-11-12
申请号：US14271812
申请日：2014-05-07
申请人： QUALCOMM Incorporated
发明人： Suresh Kumar Venkumahanti , Stephen Robert Shannon , Lin Wang
IPC分类号： G06F9/50 , G06F9/30
CPC分类号： G06F9/30098 , G06F9/3851 , G06F9/3891 , G06F9/5088
摘要： Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer readable media are disclosed. In one aspect, a dynamic load balancing circuit comprising a control unit is provided. The control unit is configured to determine whether a suboptimal load condition exists between a first cluster and a second cluster of a clustered processor core. If a suboptimal load condition exists, the control unit is further configured to transfer a content of private register(s) of a first hardware thread of the first cluster to private register(s) of a second hardware thread of the second cluster via shared hardware resources of the first hardware thread and the second hardware thread. The control unit is also configured to exchange a first identifier associated with the first hardware thread with a second identifier associated with the second hardware thread via the shared hardware resources.
摘要翻译：公开了使用共享硬件资源的集群处理器核心中的硬件线程的动态负载平衡以及相关电路，方法和计算机可读介质。一方面，提供了包括控制单元的动态负载平衡电路。控制单元被配置为确定集群处理器核心的第一集群和第二集群之间是否存在次优负载条件。如果存在次优负载条件，则控制单元还被配置为经由共享硬件将第一集群的第一硬件线程的私有寄存器的内容传送到第二集群的第二硬件线程的私有寄存器第一个硬件线程和第二个硬件线程的资源。控制单元还被配置为经由共享硬件资源与第一硬件线程相关联的第一标识符与与第二硬件线程相关联的第二标识符进行交换。

3. 发明申请

US20190196867A1 SYSTEM AND METHOD OF PRIORITY-BASED INTERRUPT STEERING 审中-公开
公开(公告)号：US20190196867A1
公开(公告)日：2019-06-27
申请号：US15983992
申请日：2018-05-18
申请人： QUALCOMM Incorporated
发明人： Erich Plondke , Suresh Kumar Venkumahanti , Lin Wang , Lucian Codrescu
IPC分类号： G06F9/48
CPC分类号： G06F9/4818 , G06F9/4812 , G06F9/4881
摘要： A processor includes priority adjustment circuitry configured to adjust a priority of a thread of multiple threads configured to execute tasks to have a software-defined priority value or a designated high priority value. The processor also includes circuitry configured to identify a lowest priority thread of the multiple threads and a control unit configured to cause the lowest priority thread to take a pending interrupt.

4. 发明授权

US10068645B2 Multiple cycle search content addressable memory 有权
公开(公告)号：US10068645B2
公开(公告)日：2018-09-04
申请号：US15369823
申请日：2016-12-05
申请人： QUALCOMM Incorporated
发明人： Kim Yaw Tong , Suresh Kumar Venkumahanti , Fadi Hamdan , Kun Ma
IPC分类号： G11C15/04
摘要： In an aspect of the disclosure, a method and an apparatus are provided. The apparatus may be a content addressable memory. The content addressable memory includes a plurality of memory sections each configured to store data. Additionally, the content addressable memory includes a comparator configured to compare the stored data in each of the plurality of memory sections with search input data. The comparison may be in a time division multiplexed fashion. The comparator may be configured to compare the stored data in each of the plurality of memory sections with search input data in a corresponding one of a plurality of memory access cycles. The content addressable memory may include a state machine configured to control when the comparator compares the stored data in each of the plurality of memory sections with search input data based on a state of the state machine.

5. 发明申请

US20150347308A1 RECONFIGURABLE FETCH PIPELINE 有权
标题翻译：可重构FETCH管道
公开(公告)号：US20150347308A1
公开(公告)日：2015-12-03
申请号：US14287331
申请日：2014-05-27
申请人： QUALCOMM Incorporated
发明人： Suresh Kumar Venkumahanti , Stephen Robert Shannon
IPC分类号： G06F12/08
CPC分类号： G06F12/0884 , G06F9/30189 , G06F9/3802 , G06F9/3824 , G06F9/3851 , G06F12/0811 , G06F12/0846 , G06F12/0855 , G06F12/0857 , G06F12/0864 , G06F12/0877 , G06F2212/1028 , G06F2212/283 , G06F2212/6012 , G06F2212/603 , Y02D10/13
摘要： A particular method includes selecting between a first cache access mode and a second cache access mode based on a number of instructions stored at an issue queue, a number of active threads of an execution unit, or both. The method further includes performing a first cache access. When the first cache access mode is selected, performing the first cache access includes performing a tag access and performing a data array access after performing the tag access. When the second cache access mode is selected, performing the first cache access includes performing the tag access in parallel with the data array access.
摘要翻译：一种特定的方法包括基于存储在发布队列中的指令数量，执行单元的活动线程数量，或两者来选择第一高速缓存访问模式和第二高速缓存访问模式。该方法还包括执行第一高速缓存访问。当选择第一高速缓存访问模式时，执行第一高速缓存访问包括在执行标签访问之后执行标签访问并执行数据阵列访问。当选择第二高速缓存访问模式时，执行第一高速缓存访问包括与数据阵列访问并行地执行标签访问。

6. 发明申请

US20150301573A1 LATENCY-BASED POWER MODE UNITS FOR CONTROLLING POWER MODES OF PROCESSOR CORES, AND RELATED METHODS AND SYSTEMS 有权
标题翻译：用于控制处理器电源模式的基于延迟的功率模式单元及相关方法和系统
公开(公告)号：US20150301573A1
公开(公告)日：2015-10-22
申请号：US14258541
申请日：2014-04-22
申请人： QUALCOMM Incorporated
发明人： Suresh Kumar Venkumahanti , Peter Gene Sassone , Sanjay Bhagawan Patil
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3206 , G06F1/3243 , G06F1/3296 , G06F9/48 , Y02D10/152
摘要： Latency-based power mode units for controlling power modes of processor cores, and related methods and systems are disclosed. In one aspect, the power mode units are configured to reduce power provided to the processor core when the processor core has one or more threads in pending status and no threads in active status. An operand of an instruction being processed by a thread may be data in memory located outside processor core. If the processor core does not require as much power to operate while a thread waits for a request from outside the processor core, the power consumed by the processor core can be reduced during these waiting periods. Power can be conserved in the processor core even when threads are being processed if the only threads being processed are in pending status, and can reduce the overall power consumption in the processor core and its corresponding CPU.
摘要翻译：公开了用于控制处理器核心的功率模式的基于延迟的功率模式单元以及相关方法和系统。在一个方面，功率模式单元被配置为当处理器核心具有一个或多个处于挂起状态的线程并且没有处于活动状态的线程时，降低提供给处理器核心的功率。由线程处理的指令的操作数可以是位于处理器核心外部的存储器中的数据。如果在线程等待来自处理器核心的请求的情况下，处理器核心不需要足够的功率来操作，则在这些等待期间可以减少处理器核心消耗的功率。即使当正在处理的线程处于待处理状态时，即使在处理线程时处理器内核中的电源也可以节省，并且可以降低处理器内核及其对应CPU的总体功耗。

7. 发明授权

US11200058B2 Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer-readable media 有权
公开(公告)号：US11200058B2
公开(公告)日：2021-12-14
申请号：US14271812
申请日：2014-05-07
申请人： QUALCOMM Incorporated
发明人： Suresh Kumar Venkumahanti , Stephen Robert Shannon , Lin Wang
IPC分类号： G06F9/30 , G06F9/38 , G06F9/50
摘要： Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer readable media are disclosed. In one aspect, a dynamic load balancing circuit comprising a control unit is provided. The control unit is configured to determine whether a suboptimal load condition exists between a first cluster and a second cluster of a clustered processor core. If a suboptimal load condition exists, the control unit is further configured to transfer a content of private register(s) of a first hardware thread of the first cluster to private register(s) of a second hardware thread of the second cluster via shared hardware resources of the first hardware thread and the second hardware thread. The control unit is also configured to exchange a first identifier associated with the first hardware thread with a second identifier associated with the second hardware thread via the shared hardware resources.

8. 发明授权

US11074076B2 Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer-readable media 有权
公开(公告)号：US11074076B2
公开(公告)日：2021-07-27
申请号：US14271812
申请日：2014-05-07
申请人： QUALCOMM Incorporated
发明人： Suresh Kumar Venkumahanti , Stephen Robert Shannon , Lin Wang
IPC分类号： G06F9/30 , G06F9/38 , G06F9/50
摘要： Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer readable media are disclosed. In one aspect, a dynamic load balancing circuit comprising a control unit is provided. The control unit is configured to determine whether a suboptimal load condition exists between a first cluster and a second cluster of a clustered processor core. If a suboptimal load condition exists, the control unit is further configured to transfer a content of private register(s) of a first hardware thread of the first cluster to private register(s) of a second hardware thread of the second cluster via shared hardware resources of the first hardware thread and the second hardware thread. The control unit is also configured to exchange a first identifier associated with the first hardware thread with a second identifier associated with the second hardware thread via the shared hardware resources.

9. 发明授权

US10719325B2 System and method of VLIW instruction processing using reduced-width VLIW processor 有权
公开(公告)号：US10719325B2
公开(公告)日：2020-07-21
申请号：US15805935
申请日：2017-11-07
申请人： QUALCOMM Incorporated
发明人： Peter Sassone , Christopher Koob , Suresh Kumar Venkumahanti
IPC分类号： G06F9/30 , G06F9/38
摘要： Very long instruction word (VLIW) instruction processing using a reduced-width processor is disclosed. In a particular embodiment, a VLIW processor includes a control circuit configured to receive a VLIW packet that includes a first number of instructions and to distribute the instructions to a second number of instruction execution paths. The first number is greater than the second number. The VLIW processor also includes physical registers configured to store results of executing the instructions and a register renaming circuit that is coupled to the control circuit.

10. 发明授权

US10353447B2 Current in-rush mitigation for power-up of embedded memories 有权
公开(公告)号：US10353447B2
公开(公告)日：2019-07-16
申请号：US15449836
申请日：2017-03-03
申请人： QUALCOMM Incorporated
发明人： Harmander Singh , Sebastien Weyland , Suresh Kumar Venkumahanti
IPC分类号： G06F1/26 , G11C5/14 , G11C16/20 , G11C16/30 , G11C29/02
摘要： A programmable logic circuit such as a finite state machine is provided that is configured to determine a memory array power-up sequence from a configuration signal to successively enable each memory array. A delay circuit triggers an initial memory bank in each enabled memory array to power-up without a delay. The delay circuit then counts responsive to a clock to determine a delay between a successive triggering of remaining memory banks in each enabled memory array to power-up.

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