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1. 发明申请

US20180046209A1 VOLTAGE DROOP CONTROL 审中-公开
公开(公告)号：US20180046209A1
公开(公告)日：2018-02-15
申请号：US15791226
申请日：2017-10-23
申请人： QUALCOMM Incorporated
发明人： Sanjay Bhagawan Patil , Daniel Stasiak , Martin Pierre Saint-Laurent , Rui Li , Bin Liang , Sei Seung Yoon , Chulmin Jung
IPC分类号： G05F1/10 , G06F1/32 , H02M1/32
CPC分类号： G05F1/10 , G06F1/26 , G06F1/263 , G06F1/3287 , G06F1/329 , H02M1/32
摘要： A computer-readable storage medium for controlling voltage droop storing instructions that, when executed by a processor, cause a device to perform operations including receiving a first voltage to a first input of a first component of a device. The first voltage corresponding to a first logical value causes a first internal power supply of the first component to be charged using an external power supply. The operations further include providing a second voltage to a second input of a second component of the device in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second voltage corresponding to the first logical value causes a second internal power supply of the second component of the device to be charged using the external power supply.

2. 发明授权

US09804650B2 Supply voltage node coupling using a switch 有权
公开(公告)号：US09804650B2
公开(公告)日：2017-10-31
申请号：US14603130
申请日：2015-01-22
申请人： QUALCOMM Incorporated
发明人： Sanjay Bhagawan Patil , Daniel Stasiak , Martin Pierre Saint-Laurent
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/263 , G06F1/26 , G06F1/266 , G06F1/3253 , Y02D10/151
摘要： An apparatus includes a first node configured to provide a first supply voltage to a first device and a second node configured to provide a second supply voltage to a second device. The apparatus further includes a bus configured to communicatively couple the first device and the second device. The apparatus also includes a switch configured to couple the first node and the second node.

3. 发明授权

US10152101B2 Controlling voltage deviations in processing systems 有权
公开(公告)号：US10152101B2
公开(公告)日：2018-12-11
申请号：US14860715
申请日：2015-09-22
申请人： QUALCOMM Incorporated
发明人： Eric Wayne Mahurin , Sanjay Bhagawan Patil , Martin Pierre Saint-Laurent
IPC分类号： G06F1/30 , G06F1/32 , G06F1/26
摘要： Systems and methods relate to controlling voltage deviations in processing systems. A scheduler receives transactions and to be issued for execution in a pipeline. A voltage deviation that will occur if a particular transaction is executed in the pipeline is estimated before the transaction is issued. Threshold comparators are used to determine if the estimated voltage deviation will exceed specified thresholds to cause voltage overshoots or undershoots. The scheduler is configured to implement one or more corrective measures, such as increasing or decreasing energy in the pipeline, to mitigate possible voltage overshoots or undershoots, before the transaction is issued to be executed in the pipeline.

4. 发明申请

US20150301573A1 LATENCY-BASED POWER MODE UNITS FOR CONTROLLING POWER MODES OF PROCESSOR CORES, AND RELATED METHODS AND SYSTEMS 有权
标题翻译：用于控制处理器电源模式的基于延迟的功率模式单元及相关方法和系统
公开(公告)号：US20150301573A1
公开(公告)日：2015-10-22
申请号：US14258541
申请日：2014-04-22
申请人： QUALCOMM Incorporated
发明人： Suresh Kumar Venkumahanti , Peter Gene Sassone , Sanjay Bhagawan Patil
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3206 , G06F1/3243 , G06F1/3296 , G06F9/48 , Y02D10/152
摘要： Latency-based power mode units for controlling power modes of processor cores, and related methods and systems are disclosed. In one aspect, the power mode units are configured to reduce power provided to the processor core when the processor core has one or more threads in pending status and no threads in active status. An operand of an instruction being processed by a thread may be data in memory located outside processor core. If the processor core does not require as much power to operate while a thread waits for a request from outside the processor core, the power consumed by the processor core can be reduced during these waiting periods. Power can be conserved in the processor core even when threads are being processed if the only threads being processed are in pending status, and can reduce the overall power consumption in the processor core and its corresponding CPU.
摘要翻译：公开了用于控制处理器核心的功率模式的基于延迟的功率模式单元以及相关方法和系统。在一个方面，功率模式单元被配置为当处理器核心具有一个或多个处于挂起状态的线程并且没有处于活动状态的线程时，降低提供给处理器核心的功率。由线程处理的指令的操作数可以是位于处理器核心外部的存储器中的数据。如果在线程等待来自处理器核心的请求的情况下，处理器核心不需要足够的功率来操作，则在这些等待期间可以减少处理器核心消耗的功率。即使当正在处理的线程处于待处理状态时，即使在处理线程时处理器内核中的电源也可以节省，并且可以降低处理器内核及其对应CPU的总体功耗。

5. 发明授权

US10133285B2 Voltage droop control 有权
公开(公告)号：US10133285B2
公开(公告)日：2018-11-20
申请号：US15791226
申请日：2017-10-23
申请人： QUALCOMM Incorporated
发明人： Sanjay Bhagawan Patil , Daniel Stasiak , Martin Pierre Saint-Laurent , Rui Li , Bin Liang , Sei Seung Yoon , Chulmin Jung
IPC分类号： G05F1/10 , G06F1/32 , H02M1/32
摘要： A computer-readable storage medium for controlling voltage droop storing instructions that, when executed by a processor, cause a device to perform operations including receiving a first voltage to a first input of a first component of a device. The first voltage corresponding to a first logical value causes a first internal power supply of the first component to be charged using an external power supply. The operations further include providing a second voltage to a second input of a second component of the device in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second voltage corresponding to the first logical value causes a second internal power supply of the second component of the device to be charged using the external power supply.

6. 发明授权

US09851730B2 Voltage droop control 有权
公开(公告)号：US09851730B2
公开(公告)日：2017-12-26
申请号：US14684128
申请日：2015-04-10
申请人： QUALCOMM Incorporated
发明人： Sanjay Bhagawan Patil , Daniel Stasiak , Martin Pierre Saint-Laurent , Rui Li , Bin Liang , Sei Seung Yoon , Chulmin Jung
IPC分类号： G05F1/10 , G06F1/32 , H02M1/32
CPC分类号： G05F1/10 , G06F1/26 , G06F1/263 , G06F1/3287 , G06F1/329 , H02M1/32
摘要： Voltage droop control is disclosed. A device includes a first component coupled to an external power supply and a second component coupled to the external power supply. The first component includes a first input configured to receive a first voltage, a first internal power supply configured to be charged by the external power supply in response to the first voltage corresponding to a first logical value, and a voltage droop controller configured to output a second voltage via a first output. The second voltage corresponds to the first logical value in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second component includes a second input configured to receive the second voltage from the first output.

7. 发明授权

US09552033B2 Latency-based power mode units for controlling power modes of processor cores, and related methods and systems 有权
标题翻译：用于控制处理器核心功率模式的基于延迟的功率模式单元，以及相关方法和系统
公开(公告)号：US09552033B2
公开(公告)日：2017-01-24
申请号：US14258541
申请日：2014-04-22
申请人： QUALCOMM Incorporated
发明人： Suresh Kumar Venkumahanti , Peter Gene Sassone , Sanjay Bhagawan Patil
IPC分类号： G06F1/32 , G06F9/48
CPC分类号： G06F1/3203 , G06F1/3206 , G06F1/3243 , G06F1/3296 , G06F9/48 , Y02D10/152
摘要： Latency-based power mode units for controlling power modes of processor cores, and related methods and systems are disclosed. In one aspect, the power mode units are configured to reduce power provided to the processor core when the processor core has one or more threads in pending status and no threads in active status. An operand of an instruction being processed by a thread may be data in memory located outside processor core. If the processor core does not require as much power to operate while a thread waits for a request from outside the processor core, the power consumed by the processor core can be reduced during these waiting periods. Power can be conserved in the processor core even when threads are being processed if the only threads being processed are in pending status, and can reduce the overall power consumption in the processor core and its corresponding CPU.
摘要翻译：公开了用于控制处理器核心的功率模式的基于延迟的功率模式单元以及相关方法和系统。在一个方面，功率模式单元被配置为当处理器核心具有一个或多个处于挂起状态的线程并且没有处于活动状态的线程时，降低提供给处理器核心的功率。由线程处理的指令的操作数可以是位于处理器核心外部的存储器中的数据。如果在线程等待来自处理器核心的请求的情况下，处理器核心不需要足够的功率来操作，则在这些等待期间可以减少处理器核心消耗的功率。即使当正在处理的线程处于待处理状态时，即使在处理线程时处理器内核中的电源也可以节省，并且可以降低处理器内核及其对应CPU的总体功耗。

8. 发明申请

US20160299517A1 VOLTAGE DROOP CONTROL 有权
标题翻译：电压控制
公开(公告)号：US20160299517A1
公开(公告)日：2016-10-13
申请号：US14684128
申请日：2015-04-10
申请人： QUALCOMM Incorporated
发明人： Sanjay Bhagawan Patil , Daniel Stasiak , Martin Pierre Saint-Laurent , Rui Li , Bin Liang , Sei Seung Yoon , Chulmin Jung
IPC分类号： G05F1/10
CPC分类号： G05F1/10 , G06F1/26 , G06F1/263 , G06F1/3287 , G06F1/329 , H02M1/32
摘要： Voltage droop control is disclosed. A device includes a first component coupled to an external power supply and a second component coupled to the external power supply. The first component includes a first input configured to receive a first voltage, a first internal power supply configured to be charged by the external power supply in response to the first voltage corresponding to a first logical value, and a voltage droop controller configured to output a second voltage via a first output. The second voltage corresponds to the first logical value in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second component includes a second input configured to receive the second voltage from the first output.
摘要翻译：公开了电压下降控制。一种设备包括耦合到外部电源的第一组件和耦合到外部电源的第二组件。第一组件包括被配置为接收第一电压的第一输入，被配置为响应于对应于第一逻辑值的第一电压由外部电源充电的第一内部电源;以及电压下降控制器，被配置为输出经由第一输出的第二电压。响应于满足第二电压电平的第一内部电源的第一电压电平，第二电压对应于第一逻辑值。第二组件包括被配置为从第一输出接收第二电压的第二输入。

9. 发明申请

US20160070323A1 SUPPLY VOLTAGE NODE COUPLING USING A SWITCH 有权
标题翻译：使用开关供电电压节点耦合
公开(公告)号：US20160070323A1
公开(公告)日：2016-03-10
申请号：US14603130
申请日：2015-01-22
申请人： QUALCOMM Incorporated
发明人： Sanjay Bhagawan Patil , Daniel Stasiak , Martin Pierre Saint-Laurent
IPC分类号： G06F1/26
CPC分类号： G06F1/263 , G06F1/26 , G06F1/266 , G06F1/3253 , Y02D10/151
摘要： An apparatus includes a first node configured to provide a first supply voltage to a first device and a second node configured to provide a second supply voltage to a second device. The apparatus further includes a bus configured to communicatively couple the first device and the second device. The apparatus also includes a switch configured to couple the first node and the second node.
摘要翻译：一种装置包括被配置为向第一装置提供第一电源电压的第一节点和被配置为向第二装置提供第二电源电压的第二节点。所述装置还包括被配置为以第一设备和第二设备通信地耦合的总线。该设备还包括被配置为耦合第一节点和第二节点的交换机。

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