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1. 发明申请

WO2009009213A2 SUPER REGENERATIVE (SR) APPARATUS HAVING PLURALITY OF PARALLEL SR AMPLIFIERS TUNED TO DISTINCT FREQUENCIES 审中-公开
标题翻译：超级再生器（SR）具有调谐到不同频率的并联SR放大器的平均数的装置
公开(公告)号：WO2009009213A2
公开(公告)日：2009-01-15
申请号：PCT/US2008/062302
申请日：2008-05-01
申请人： QUALCOMM INCORPORATED , MONAT, Pavel , JULIAN, David Jonathan , DOUGLAS, Robert Keith , GUDEM, Prasad S.
发明人： MONAT, Pavel , JULIAN, David Jonathan , DOUGLAS, Robert Keith , GUDEM, Prasad S.
IPC分类号： H03D11/02
CPC分类号： H03D11/00 , H04B2001/6908
摘要： An apparatus, which may be configured as a receiver or transceiver, includes a plurality of super regenerative (SR) amplifiers coupled in parallel, wherein the SR amplifiers are tuned to distinct frequency bands, respectively. The apparatus may further include isolation amplifiers at the respective inputs and outputs of the SR amplifiers to prevent injection locking and reduce power leakage. The apparatus may include a circuit to reduce or substantially eliminate in-band jamming signals. The apparatus may form at least part of a wireless communications device adapted to receive signals from other wireless communications devices, adapted to transmit signal to other wireless communications devices, and adapted to both transmit and receive signals to and from other wireless communications devices.
摘要翻译：可以被配置为接收器或收发器的装置包括并联耦合的多个超再生（SR）放大器，其中SR放大器分别被调谐到不同的频带。该装置还可以包括在SR放大器的相应输入和输出处的隔离放大器，以防止注入锁定并减少功率泄漏。该装置可以包括用于减少或基本上消除带内干扰信号的电路。该装置可以形成适于从其他无线通信设备接收信号的无线通信设备的至少一部分，其适于向其他无线通信设备发送信号，并且适于向和从其他无线通信设备发送和接收信号。

2. 发明申请

WO2012106553A1 DUPLEXER BYPASS 审中-公开
标题翻译：双机旁路
公开(公告)号：WO2012106553A1
公开(公告)日：2012-08-09
申请号：PCT/US2012/023688
申请日：2012-02-02
申请人： QUALCOMM INCORPORATED , CHAN, ChunChung , NG, Alvin Siu-Chung , GUDEM, Prasad S.
发明人： CHAN, ChunChung , NG, Alvin Siu-Chung , GUDEM, Prasad S.
IPC分类号： H04B1/44
CPC分类号： H04B1/44 , H04B1/525 , H04B7/0602 , H04B7/0802
摘要： Disclosed are circuits, techniques and methods for implementing a process of selectively bypassing a duplexer in a transmission path. In a particular embodiment, a receiver and a transmitter are coupled to a shared antenna through a duplexer. The duplexer may be selectively bypassed under certain conditions while the receiver is disabled and/or powered off.
摘要翻译：公开了用于实现选择性地绕过传输路径中的双工器的过程的电路，技术和方法。在特定实施例中，接收机和发射机通过双工器耦合到共享天线。在接收机被禁用和/或断电的情况下，可以在特定条件下选择性地旁路双工器。

3. 发明申请

WO2008112800A3 WIRELESS RECEIVER WITH NOTCH FILTER TO REDUCE EFFECTS OF TRANSMIT SIGNAL LEAKAGE 审中-公开
公开(公告)号：WO2008112800A3
公开(公告)日：2008-09-18
申请号：PCT/US2008/056711
申请日：2008-03-12
申请人： QUALCOMM INCORPORATED , CHANG, Li-Chung , GUDEM, Prasad S. , CABANILLAS, Jose
发明人： CHANG, Li-Chung , GUDEM, Prasad S. , CABANILLAS, Jose
IPC分类号： H04B1/52 , H04B1/10
摘要： This disclosure describes techniques for reducing adverse effects of TX signal leakage in a full-duplex, wireless communication device. The techniques make use of a notch filter to reject TX signal leakage in a signal processed in the RX path of the wireless communication device. The notch filter may be constructed as a complex notch filter using passive resistor and capacitor components to produce a notch frequency that attenuates TX signal leakage components in a desired signal. The notch filter may be applied to a down-converted, baseband signal produced by a passive mixer.

4. 发明申请

WO2013026038A1 JOINT LINEAR AND NON-LINEAR CANCELLATION OF TRANSMIT SELF-JAMMING INTERFERENCE 审中-公开
标题翻译：接头线性和非线性消除传输自我干扰
公开(公告)号：WO2013026038A1
公开(公告)日：2013-02-21
申请号：PCT/US2012/051476
申请日：2012-08-17
申请人： QUALCOMM INCORPORATED , RIMINI, Roberto , HEIDMANN, Peter D. , GUDEM, Prasad S. , VERMA, Sumit , BURKE, Joseph
发明人： RIMINI, Roberto , HEIDMANN, Peter D. , GUDEM, Prasad S. , VERMA, Sumit , BURKE, Joseph
IPC分类号： H04B1/10 , H04B1/30 , H04B1/52
CPC分类号： H04B1/109 , H04B1/30 , H04B1/525
摘要： Certain aspects of the present disclosure propose an adaptive joint linear and non-linear digital filter that can adaptively estimate and reconstruct cascaded effects of linear and non-linear self-jamming distortions introduced by non-linearities in the transmit and/or receive chains. The proposed digital filter may be used to cancel second-order inter-modulation distortion (IM2) generated in the receive chain and/or harmonic distortion generated in the transmit chain, as well as other distortions introduced by the transmit/and or receive chains.
摘要翻译：本公开的某些方面提出了一种自适应联合线性和非线性数字滤波器，其可以自适应地估计和重建由发送和/或接收链中的非线性引入的线性和非线性自干扰失真的级联效应。所提出的数字滤波器可以用于消除在接收链中产生的二阶互调失真（IM2）和/或在发送链中产生的谐波失真以及由发送/和/或接收链引入的其他失真。

5. 发明申请

WO2009108815A1 DELTA-SIGMA MODULATOR CLOCK DITHERING IN A FRACTIONAL-N PHASE-LOCKED LOOP 审中-公开
标题翻译： DELTA-SIGMA调制器时钟在一个分段N相锁定环路
公开(公告)号：WO2009108815A1
公开(公告)日：2009-09-03
申请号：PCT/US2009/035349
申请日：2009-02-26
申请人： QUALCOMM Incorporated , XU, Yang , ZHANG, Gang , GUDEM, Prasad S.
发明人： XU, Yang , ZHANG, Gang , GUDEM, Prasad S.
IPC分类号： H03L7/197
CPC分类号： H03L7/1974
摘要： The clock signal supplied to the delta-sigma modulator in a fractional-N phase-locked loop is dithered. In one example, the PLL includes a novel programmable clock dithering circuit. The programmable clock dithering circuit is controllable via a serial bus to dither the phase of the clock signal in a selected one of several ways. If the clock signal is dithered in a first way (pseudo-random phase dithering), then the power of digital noise generated by the delta-sigma modulator is spread over a frequency band, thereby reducing the degree to which the noise interferes with other circuitry. If the clock signal is dithered in a second way (rotational phase dithering), then the power of digital noise is frequency shifted such that the degree to which the noise interferes with the other circuitry is reduced. The programmable clock dithering circuit can be controlled in other ways. For example, dithering can be programmably disabled.
摘要翻译：在分数N锁相环中提供给Δ-Σ调制器的时钟信号被抖动。在一个示例中，PLL包括新颖的可编程时钟抖动电路。可编程时钟抖动电路可通过串行总线进行控制，以选择的几种方式对时钟信号的相位进行抖动。如果时钟信号以第一种方式抖动（伪随机相位抖动），则由Δ-Σ调制器产生的数字噪声的功率在频带上扩展，从而降低噪声干扰其他电路的程度。如果时钟信号以第二种方式抖动（旋转相位抖动），则数字噪声的功率被频移，使得噪声干扰另一电路的程度降低。可编程时钟抖动电路可以以其他方式进行控制。例如，抖动可以可编程地禁用。

6. 发明申请

WO2009026413A1 ACTIVE CIRCUITS WITH LOAD LINEARIZATION 审中-公开
标题翻译：具有负载线性化的有源电路
公开(公告)号：WO2009026413A1
公开(公告)日：2009-02-26
申请号：PCT/US2008/073812
申请日：2008-08-21
申请人： QUALCOMM Incorporated , LIU, Li , GUDEM, Prasad S.
发明人： LIU, Li , GUDEM, Prasad S.
IPC分类号： H03F1/26 , H03F1/32 , H04B1/10 , H04B1/52
CPC分类号： H04B1/109 , H03F1/223 , H03F1/3205 , H03F1/3211 , H03F3/45179 , H03F3/45188 , H03F2200/453 , H03F2203/45306 , H03F2203/45352 , H03F2203/45386 , H03F2203/45394 , H04B1/525
摘要： Active circuits with active loads linearized via distortion cancellation are described. In one design, an apparatus includes a first stage and a load stage. For an amplifier, the first stage amplifies an input signal and provides an output signal having a larger signal level. For a mixer, the first stage mixes an input signal with an LO signal and provides an output signal. The load stage provides an active load for the first stage and is linearized by canceling distortion generated by the active load. In one design, the load stage includes a first transistor that provides the active load and generates distortion due to its nonlinearity. The load stage further includes at least one transistor that generates a replica of the distortion from the first transistor. The distortion replica is used to cancel the distortion from the first transistor. The first stage may also be linearized with distortion cancellation.
摘要翻译：描述了通过失真消除线性化的有源负载的有源电路。在一种设计中，装置包括第一级和负载级。对于放大器，第一级放大输入信号并提供具有较大信号电平的输出信号。对于混频器，第一级将输入信号与LO信号混频并提供输出信号。负载级为第一级提供有效负载，并通过消除由有效负载产生的失真来线性化。在一种设计中，负载级包括提供有源负载并由于其非线性而产生失真的第一晶体管。负载级还包括至少一个晶体管，其产生来自第一晶体管的失真的复制品。失真复制品用于消除第一晶体管的失真。第一级也可以通过失真消除线性化。

7. 发明申请

WO2011153077A1 REDUCING POWER CONSUMPTION BY IN-CIRCUIT MEASUREMENT OF RECEIVE BAND ATTENUATION AND/OR NOISE 审中-公开
标题翻译：通过线路衰减测量和/或噪声降低功耗
公开(公告)号：WO2011153077A1
公开(公告)日：2011-12-08
申请号：PCT/US2011/038245
申请日：2011-05-26
申请人： QUALCOMM Incorporated , GUDEM, Prasad S. , ASURI, Bhushan , LAU, Soon-Seng , LEUNG, Wingching Vincent
发明人： GUDEM, Prasad S. , ASURI, Bhushan , LAU, Soon-Seng , LEUNG, Wingching Vincent
IPC分类号： H04B1/10 , H04B1/52 , H04W52/02
CPC分类号： H04B1/1027 , H03F1/02 , H03F3/24 , H04B1/525 , H04B2001/045 , H04W52/0245 , Y02D70/1242 , Y02D70/164 , Y02D70/40
摘要： Although the duplexer in a full-duplex transceiver circuit may only be guaranteed by the duplexer manufacturer to have a transmit band rejection from its TX port to its RX port of a certain amount, and may only be guaranteed to have a receive band rejection of another amount, the actual transmit band rejection and the actual receive band rejection of a particular instance of the duplexer may be better than specified. Rather than consuming excess power in the receiver and/or transmitter in order to meet performance requirements assuming the duplexer only performs as well as specified, the duplexer's in-circuit performance is measured as part of a transmitter-to-receiver isolation determination. Transmitter and/or receiver power settings are reduced where possible to take advantage of the measured better-than-specified in-circuit duplexer performance, while still meeting transceiver performance requirements. Power settings are not changed during normal transmit and receive mode operation.
摘要翻译：虽然全双工收发器电路中的双工器可能只能由双工器制造商保证从其TX端口到其一定数量的RX端口的发射波段抑制，并且只能保证具有另一个的接收频带抑制数量，双工器的特定实例的实际发射频带抑制和实际接收频带抑制可能优于指定的。假设双工器仅执行指定，而不是在接收机和/或发射机中消耗多余的功率，以满足性能要求，则双工器的在线性能是作为发射机到接收机隔离确定的一部分进行测量的。发射机和/或接收机功率设置在可能的情况下可以减少，以便在仍然满足收发器性能要求的同时利用测得的优于指定的在线双工器性能。在正常的发送和接收模式操作期间，电源设置不会改变。

8. 发明申请

WO2011153076A2 REDUCING POWER CONSUMPTION BY TAKING ADVANTAGE OF SUPERIOR IN-CIRCUIT DUPLEXER PERFORMANCE 审中-公开
标题翻译：通过获得超级电路双工器性能优势降低功耗
公开(公告)号：WO2011153076A2
公开(公告)日：2011-12-08
申请号：PCT/US2011/038241
申请日：2011-05-26
申请人： QUALCOMM INCORPORATED , GUDEM, Prasad S. , LAU, Soon-Seng , LIU, Li
发明人： GUDEM, Prasad S. , LAU, Soon-Seng , LIU, Li
IPC分类号： H04B1/10 , H04B1/16 , H04B1/52
CPC分类号： H04B1/525 , H04B1/109 , H04W52/0238 , Y02D70/1242 , Y02D70/164 , Y02D70/40
摘要： Although the duplexer in a full-duplex transceiver circuit may only be guaranteed by the duplexer manufacturer to have a transmit band rejection from its TX port to its RX port of a certain amount, and may only be guaranteed to have a receive band rejection of another amount, the actual transmit band rejection and the actual receive band rejection of a particular instance of the duplexer may be better than specified. Rather than consuming excess power in the receiver and/or transmitter in order to meet performance requirements assuming the duplexer only performs as well as specified, the duplexer's in-circuit performance is measured as part of a transmitter-to-receiver isolation determination. Transmitter and/or receiver power settings are reduced where possible to take advantage of the measured better-than-specified in-circuit duplexer performance, while still meeting transceiver performance requirements. Power settings are not changed during normal transmit and receive mode operation.
摘要翻译：虽然全双工收发器电路中的双工器可能只能由双工器制造商保证从其TX端口到其一定数量的RX端口的发射波段抑制，并且只能保证具有另一个的接收频带抑制数量，双工器的特定实例的实际发射频带抑制和实际接收频带抑制可能优于指定的。假设双工器仅执行指定，而不是在接收机和/或发射机中消耗多余的功率，以满足性能要求，则双工器的在线性能是作为发射机到接收机隔离确定的一部分进行测量的。发射机和/或接收机功率设置在可能的情况下可以减少，以便在仍然满足收发器性能要求的同时利用测得的优于指定的在线双工器性能。在正常的发送和接收模式操作期间，电源设置不会改变。

9. 发明申请

WO2009079491A1 LOW NOISE AND LOW INPUT CAPACITANCE DIFFERENTIAL MDS LNA 审中-公开
标题翻译：低噪声和低输入电容差分MDS LNA
公开(公告)号：WO2009079491A1
公开(公告)日：2009-06-25
申请号：PCT/US2008/086950
申请日：2008-12-16
申请人： QUALCOMM Incorporated , CABANILLAS, Jose , GUDEM, Prasad S. , KIM, Namsoo , MARCU, Cristian , SAVLA, Anup
发明人： CABANILLAS, Jose , GUDEM, Prasad S. , KIM, Namsoo , MARCU, Cristian , SAVLA, Anup
IPC分类号： H03F1/32
CPC分类号： H03F3/45188 , H03F1/3205 , H03F1/3211 , H03F2203/45318 , H03F2203/45396
摘要： A differential low noise amplifier (LNA) involves two main amplifying transistors biased in saturation, and two cancel transistors biased in sub-threshold. In one example, the gates of the cancel transistors are coupled to the drains of main transistors, in a symmetrical and cross-coupled fashion. The main transistors are source degenerated. Because the gates of cancel transistors are not coupled to the differential input leads of the LNA, the input capacitance of the LNA is reduced. Noise introduced into the LNA output due to the cancel transistors being biased in the sub-threshold region is reduced because there are two stages. The first stage involves the main transistors, and the second stage involves the cancel transistors. By increasing the gain of the first stage and decreasing the gain of the second stage, overall LNA gain is maintained while reducing the noise that the sub-threshold biased transistors contribute to the LNA output.
摘要翻译：差分低噪声放大器（LNA）涉及两个偏置饱和的主放大晶体管，两个取消晶体管偏置为次阈值。在一个示例中，取消晶体管的栅极以对称和交叉耦合的方式耦合到主晶体管的漏极。主晶体管是源极退化的。因为取消晶体管的栅极没有耦合到LNA的差分输入引线，所以LNA的输入电容减小。由于存在两个阶段，由于在子阈值区域偏置的取消晶体管而导入到LNA输出中的噪声被减小。第一级涉及主晶体管，第二级涉及取消晶体管。通过增加第一级的增益并降低第二级的增益，保持整体LNA增益，同时降低子阈值偏置晶体管对LNA输出有贡献的噪声。

10. 发明公开

EP2263317A1 DELTA-SIGMA MODULATOR CLOCK DITHERING IN A FRACTIONAL-N PHASE-LOCKED LOOP 审中-公开
标题翻译： EINEM分数N-PLL中的FÜRDELTA-SIGMA调制器
公开(公告)号：EP2263317A1
公开(公告)日：2010-12-22
申请号：EP09715557.6
申请日：2009-02-26
申请人： Qualcomm Incorporated
发明人： XU, Yang , ZHANG, Gang , GUDEM, Prasad S.
IPC分类号： H03L7/197
CPC分类号： H03L7/1974
摘要： The clock signal supplied to the delta-sigma modulator in a fractional-N phase-locked loop is dithered. In one example, the PLL includes a novel programmable clock dithering circuit. The programmable clock dithering circuit is controllable via a serial bus to dither the phase of the clock signal in a selected one of several ways. If the clock signal is dithered in a first way (pseudo-random phase dithering), then the power of digital noise generated by the delta-sigma modulator is spread over a frequency band, thereby reducing the degree to which the noise interferes with other circuitry. If the clock signal is dithered in a second way (rotational phase dithering), then the power of digital noise is frequency shifted such that the degree to which the noise interferes with the other circuitry is reduced. The programmable clock dithering circuit can be controlled in other ways. For example, dithering can be programmably disabled.

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