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1. 发明申请

WO2008106354A3 SPS RECEIVER WITH ADJUSTABLE LINEARITY 审中-公开
公开(公告)号：WO2008106354A3
公开(公告)日：2008-09-04
申请号：PCT/US2008/054461
申请日：2008-02-20
申请人： QUALCOMM INCORPORATED , XU, Yang , PALS, Timothy Paul , WANG, Kevin Hsi-huai
发明人： XU, Yang , PALS, Timothy Paul , WANG, Kevin Hsi-huai
IPC分类号： G01S1/04
摘要： A satellite positioning system (SPS) receiver that can provide good performance with low power consumption is described. The SPS receiver may be operated in one of multiple modes, which may be associated with different bias current settings for the SPS receiver. One of the modes may be selected based on output power level of a transmitter co-located with the SPS receiver. The bias current of an LNA, a mixer, and/or an LO generator within the SPS receiver may be set based on the selected mode. In one design, a first (e.g., lower power) mode may be selected for the SPS receiver if the transmitter output power level is below a switch point. A second (e.g., high linearity) mode may be selected if the transmitter output power level is above the switch point. The second mode is associated with more bias current for the SPS receiver than the first mode.

2. 发明申请

WO2009108815A1 DELTA-SIGMA MODULATOR CLOCK DITHERING IN A FRACTIONAL-N PHASE-LOCKED LOOP 审中-公开
标题翻译： DELTA-SIGMA调制器时钟在一个分段N相锁定环路
公开(公告)号：WO2009108815A1
公开(公告)日：2009-09-03
申请号：PCT/US2009/035349
申请日：2009-02-26
申请人： QUALCOMM Incorporated , XU, Yang , ZHANG, Gang , GUDEM, Prasad S.
发明人： XU, Yang , ZHANG, Gang , GUDEM, Prasad S.
IPC分类号： H03L7/197
CPC分类号： H03L7/1974
摘要： The clock signal supplied to the delta-sigma modulator in a fractional-N phase-locked loop is dithered. In one example, the PLL includes a novel programmable clock dithering circuit. The programmable clock dithering circuit is controllable via a serial bus to dither the phase of the clock signal in a selected one of several ways. If the clock signal is dithered in a first way (pseudo-random phase dithering), then the power of digital noise generated by the delta-sigma modulator is spread over a frequency band, thereby reducing the degree to which the noise interferes with other circuitry. If the clock signal is dithered in a second way (rotational phase dithering), then the power of digital noise is frequency shifted such that the degree to which the noise interferes with the other circuitry is reduced. The programmable clock dithering circuit can be controlled in other ways. For example, dithering can be programmably disabled.
摘要翻译：在分数N锁相环中提供给Δ-Σ调制器的时钟信号被抖动。在一个示例中，PLL包括新颖的可编程时钟抖动电路。可编程时钟抖动电路可通过串行总线进行控制，以选择的几种方式对时钟信号的相位进行抖动。如果时钟信号以第一种方式抖动（伪随机相位抖动），则由Δ-Σ调制器产生的数字噪声的功率在频带上扩展，从而降低噪声干扰其他电路的程度。如果时钟信号以第二种方式抖动（旋转相位抖动），则数字噪声的功率被频移，使得噪声干扰另一电路的程度降低。可编程时钟抖动电路可以以其他方式进行控制。例如，抖动可以可编程地禁用。

3. 发明申请

WO2009042780A3 APPARATUS AND METHODS FOR DOWNCONVERTING RADIO FREQUENCY SIGNALS 审中-公开
公开(公告)号：WO2009042780A3
公开(公告)日：2009-04-02
申请号：PCT/US2008/077697
申请日：2008-09-25
申请人： QUALCOMM INCORPORATED , XU, Yang , PENG, Solti
发明人： XU, Yang , PENG, Solti
IPC分类号： H03D7/14
摘要： A noise isolation passive mixing apparatus is designed to mitigate noise contribution from intermediate frequency (IF) filters and amplifiers in a radio frequency translation stage. Common-gate configuration devices are inserted between passive mixer output and input of a transimpedance amplifier. In this way, circulation of the input-referred noise of the transimpedance amplifier is decreased, because of the relatively high output impedance of the common-gate devices, and the noise figure of the mixing apparatus can be improved. Since the radio frequency signal still sees low impedance, a radio frequency transconductance (RF gm) stage can be removed from the mixing apparatus, reducing current consumption. A double-balanced mixing apparatus with this general architecture may be implemented in a 0.18 micrometer CMOS technology and used in a low-IF global positioning system operating at 1.575GHz, in an access terminal of a cellular communication system, and in other systems.

4. 发明公开

EP2118672A2 SPS RECEIVER WITH ADJUSTABLE LINEARITY 有权
标题翻译： SPS-EMPFÄNGERMIT VERSTELLBARERLINEARITÄT
公开(公告)号：EP2118672A2
公开(公告)日：2009-11-18
申请号：EP08730293.1
申请日：2008-02-20
申请人： QUALCOMM Incorporated
发明人： XU, Yang , PALS, Timothy Paul , WANG, Kevin Hsi-huai
IPC分类号： G01S1/04
CPC分类号： H03F3/04 , G01S19/21 , G01S19/34 , G01S19/36 , H03F1/02 , H03F1/223 , H03F1/3205 , H03F3/19 , H03F3/24 , H04B7/18513 , H04B2001/045 , Y02D70/1222 , Y02D70/142 , Y02D70/144 , Y02D70/146 , Y02D70/164 , Y02D70/446
摘要： A satellite positioning system (SPS) receiver that can provide good performance with low power consumption is described. The SPS receiver may be operated in one of multiple modes, which may be associated with different bias current settings for the SPS receiver. One of the modes may be selected based on output power level of a transmitter co-located with the SPS receiver. The bias current of an LNA, a mixer, and/or an LO generator within the SPS receiver may be set based on the selected mode. In one design, a first (e.g., lower power) mode may be selected for the SPS receiver if the transmitter output power level is below a switch point. A second (e.g., high linearity) mode may be selected if the transmitter output power level is above the switch point. The second mode is associated with more bias current for the SPS receiver than the first mode.
摘要翻译：描述了能够以低功耗提供良好性能的卫星定位系统（SPS）接收机。 SPS接收机可以以多种模式之一操作，这可以与SPS接收机的不同偏置电流设置相关联。可以基于与SPS接收机共处的发射机的输出功率电平来选择其中一种模式。可以基于所选择的模式来设置SPS接收机内的LNA，混频器和/或LO发生器的偏置电流。在一种设计中，如果发射机输出功率电平低于切换点，则可以为SPS接收机选择第一（例如较低功率）模式。如果发射机输出功率电平高于开关点，则可以选择第二（例如，高线性度）模式。与第一模式相比，第二模式与SPS接收机的偏置电流相关。

5. 发明授权

EP2118672B1 SPS RECEIVER WITH ADJUSTABLE LINEARITY 有权
标题翻译：具有可调LINEARITY SPS接收机
公开(公告)号：EP2118672B1
公开(公告)日：2012-10-31
申请号：EP08730293.1
申请日：2008-02-20
申请人： QUALCOMM Incorporated
发明人： XU, Yang , PALS, Timothy Paul , WANG, Kevin Hsi-huai
IPC分类号： G01S19/21 , H03F1/32 , G01S19/34 , G01S19/36
CPC分类号： H03F3/04 , G01S19/21 , G01S19/34 , G01S19/36 , H03F1/02 , H03F1/223 , H03F1/3205 , H03F3/19 , H03F3/24 , H04B7/18513 , H04B2001/045 , Y02D70/1222 , Y02D70/142 , Y02D70/144 , Y02D70/146 , Y02D70/164 , Y02D70/446
摘要： A satellite positioning system (SPS) receiver that can provide good performance with low power consumption is described. The SPS receiver may be operated in one of multiple modes, which may be associated with different bias current settings for the SPS receiver. One of the modes may be selected based on output power level of a transmitter co-located with the SPS receiver. The bias current of an LNA, a mixer, and/or an LO generator within the SPS receiver may be set based on the selected mode. In one design, a first (e.g., lower power) mode may be selected for the SPS receiver if the transmitter output power level is below a switch point. A second (e.g., high linearity) mode may be selected if the transmitter output power level is above the switch point. The second mode is associated with more bias current for the SPS receiver than the first mode.

6. 发明授权

EP2356739B1 APPARATUS AND METHODS FOR DOWNCONVERTING RADIO FREQUENCY SIGNALS 有权
标题翻译：器件和方法高频信号的降低的混合
公开(公告)号：EP2356739B1
公开(公告)日：2012-11-07
申请号：EP08833814.0
申请日：2008-09-25
申请人： QUALCOMM Incorporated
发明人： XU, Yang , PENG, Solti
IPC分类号： H03D7/14
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/165 , H03D2200/0084

7. 发明公开

EP2356739A2 APPARATUS AND METHODS FOR DOWNCONVERTING RADIO FREQUENCY SIGNALS 有权
标题翻译：器件和方法高频信号的降低的混合
公开(公告)号：EP2356739A2
公开(公告)日：2011-08-17
申请号：EP08833814.0
申请日：2008-09-25
申请人： QUALCOMM Incorporated
发明人： XU, Yang , PENG, Solti
IPC分类号： H03D7/14
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/165 , H03D2200/0084
摘要： A noise isolation passive mixing apparatus is designed to mitigate noise contribution from intermediate frequency (IF) filters and amplifiers in a radio frequency translation stage. Common-gate configuration devices are inserted between passive mixer output and input of a transimpedance amplifier. In this way, circulation of the input-referred noise of the transimpedance amplifier is decreased, because of the relatively high output impedance of the common-gate devices, and the noise figure of the mixing apparatus can be improved. Since the radio frequency signal still sees low impedance, a radio frequency transconductance (RF gm) stage can be removed from the mixing apparatus, reducing current consumption. A double-balanced mixing apparatus with this general architecture may be implemented in a 0.18 micrometer CMOS technology and used in a low-IF global positioning system operating at 1.575GHz, in an access terminal of a cellular communication system, and in other systems.

8. 发明公开

EP2263317A1 DELTA-SIGMA MODULATOR CLOCK DITHERING IN A FRACTIONAL-N PHASE-LOCKED LOOP 审中-公开
标题翻译： EINEM分数N-PLL中的FÜRDELTA-SIGMA调制器
公开(公告)号：EP2263317A1
公开(公告)日：2010-12-22
申请号：EP09715557.6
申请日：2009-02-26
申请人： Qualcomm Incorporated
发明人： XU, Yang , ZHANG, Gang , GUDEM, Prasad S.
IPC分类号： H03L7/197
CPC分类号： H03L7/1974
摘要： The clock signal supplied to the delta-sigma modulator in a fractional-N phase-locked loop is dithered. In one example, the PLL includes a novel programmable clock dithering circuit. The programmable clock dithering circuit is controllable via a serial bus to dither the phase of the clock signal in a selected one of several ways. If the clock signal is dithered in a first way (pseudo-random phase dithering), then the power of digital noise generated by the delta-sigma modulator is spread over a frequency band, thereby reducing the degree to which the noise interferes with other circuitry. If the clock signal is dithered in a second way (rotational phase dithering), then the power of digital noise is frequency shifted such that the degree to which the noise interferes with the other circuitry is reduced. The programmable clock dithering circuit can be controlled in other ways. For example, dithering can be programmably disabled.

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