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1. 发明申请

WO2022104635A1 METHODS AND APPARATUS FOR SELECTION OF RENDERING MODES 审中-公开
公开(公告)号：WO2022104635A1
公开(公告)日：2022-05-27
申请号：PCT/CN2020/130048
申请日：2020-11-19
申请人： QUALCOMM INCORPORATED , DU, Bo , GRUBER, Andrew Evan , XU, Yongjun
发明人： DU, Bo , GRUBER, Andrew Evan , XU, Yongjun
IPC分类号： G06T15/04 , G06T15/06 , G06T11/40
摘要： The present disclosure relates to graphics processing. An apparatus of the present disclosure may determine visibility streams corresponding to a target and a set of bins into which the target is divided. The apparatus may select one of a first rendering mode or a second rendering mode for the target based on the first visibility stream and based on the set of second visibility streams. When the first rendering mode is select, the apparatus may configure each of the set of bins into a first subset associated with a first type of rendering pass or a second subset associated with a second type of rendering pass. The apparatus may then render the target based on the selected one of the first rendering mode or the second rendering mode and, if applicable, based on the first rendering pass type or the second rendering pass type.

2. 发明申请

WO2022104583A1 METHODS AND APPARATUS FOR SELECTION OF RENDERING MODES 审中-公开
公开(公告)号：WO2022104583A1
公开(公告)日：2022-05-27
申请号：PCT/CN2020/129706
申请日：2020-11-18
申请人： QUALCOMM INCORPORATED , ALLA, Srihari Babu , NAGENDRA KUMAR, Jonnala Gadda , SEETHARAMAIAH, Avinash , GRUBER, Andrew Evan , FRISINGER, Thomas Edwin , HAMMERSTONE, Richard H. , DU, Bo , XU, Yongjun
发明人： ALLA, Srihari Babu , NAGENDRA KUMAR, Jonnala Gadda , SEETHARAMAIAH, Avinash , GRUBER, Andrew Evan , FRISINGER, Thomas Edwin , HAMMERSTONE, Richard H. , DU, Bo , XU, Yongjun
IPC分类号： G06T15/04 , G06T15/06 , G06T11/40
摘要： The present disclosure relates to graphics processing. An apparatus of the present disclosure may determine visibility streams corresponding to a target and a set of bins into which the target is divided. The apparatus may select one of a first rendering mode or a second rendering mode for the target based on the first visibility stream and based on the set of second visibility streams. When the first rendering mode is select, the apparatus may configure each of the set of bins into a first subset associated with a first type of rendering pass or a second subset associated with a second type of rendering pass. The apparatus may then render the target based on the selected one of the first rendering mode or the second rendering mode and, if applicable, based on the first rendering pass type or the second rendering pass type.

3. 发明申请

WO2020198223A1 GENERAL PURPOSE REGISTER AND WAVE SLOT ALLOCATION IN GRAPHICS PROCESSING 审中-公开
公开(公告)号：WO2020198223A1
公开(公告)日：2020-10-01
申请号：PCT/US2020/024458
申请日：2020-03-24
申请人： QUALCOMM INCORPORATED
发明人： DU, Yun , GRUBER, Andrew Evan , YU, Chun , ZHANG, Chihong , SHANG, Hongjiang , YING, Zilin , WEI, Fei
IPC分类号： G06T15/00 , G06T15/04 , G06T1/60
摘要： Example techniques are described for generating graphics content by obtaining texture operation instructions corresponding to a texture operation, in response to determining at least one of insufficient general purpose register space is available for the texture operation or insufficient wave slots are available for the texture operation, generating an indication that the texture operation corresponds to a deferred wave, executing the texture operation, sending, to a texture processor, initial texture sample instructions corresponding to the texture operation that was executed, and receiving texture mapped data corresponding to the initial texture sample instructions.

4. 发明申请

WO2018022187A1 VERTEX SHADERS FOR BINNING BASED GRAPHICS PROCESSING 审中-公开
标题翻译： VERTEX SHADERS基于图像处理的BINING
公开(公告)号：WO2018022187A1
公开(公告)日：2018-02-01
申请号：PCT/US2017/035038
申请日：2017-05-30
申请人： QUALCOMM INCORPORATED
发明人： KAZAKOV, Maxim , GRUBER, Andrew Evan
IPC分类号： G06T15/00 , G06T1/20
CPC分类号： G06T1/20 , G06T15/005
摘要： This disclosure describes examples of using two vertex shaders each one during different graphics processing passes in a binning architecture for graphics processing. A first vertex shader processes subset of attributes of a vertex in a binning pass, where the subset of attributes include those that contribute to visibility determination and attributes that may benefit from being processed with a vertex shader that provides functional flexibility. A second, different vertex shader processes another subset of attributes of the vertex in the rendering pass.
摘要翻译：本公开描述了在用于图形处理的合并体系结构中的不同图形处理期间使用两个顶点着色器的示例。第一顶点着色器处理归并通过中顶点属性的子集，其中属性的子集包括对可见性确定有贡献的那些属性以及可能受益于提供功能灵活性的顶点着色器处理的属性。第二个不同的顶点着色器处理渲染过程中顶点属性的另一个子集。

5. 发明申请

WO2017204910A1 PER-INSTANCE PREAMBLE FOR GRAPHICS PROCESSING 审中-公开
标题翻译：用于图形处理的实例前导
公开(公告)号：WO2017204910A1
公开(公告)日：2017-11-30
申请号：PCT/US2017/026842
申请日：2017-04-10
申请人： QUALCOMM INCORPORATED
发明人： CHEN, Lin , HAMMERSTONE, Richard , LIU, Jiaji , ZHANG, Chihong , GRUBER, Andrew Evan , DU, Yun
IPC分类号： G06F12/0862 , G06F12/06 , G06F9/38 , G06F9/45 , G06T15/00
摘要： A method for processing data in a graphics processing unit (GPU) including receiving an instance identifier for an instance and a shader program comprising a preamble code block and a main shader code block, assigning, the instance identifier to a general purpose register at wave creation, allocating address space within the constant memory for instance uniforms, and determining the preamble code block has not been executed and the wave is a first wave of the instance to be executed, based on determining the preamble code block has not been executed and the wave is the first wave to be executed, executing the preamble code block to store the plurality of instance uniforms in the constant memory and based, at least in part, on executing the preamble code block, executing the wave of the plurality of waves using at least one of the plurality of instance constants stored inconstant memory.
摘要翻译：一种用于在图形处理单元（GPU）中处理数据的方法，所述方法包括：接收用于实例的实例标识符和包括前导码代码块和主着色器代码块的着色器程序;分配所述实例标识符基于确定前导码而在波形创建时向通用寄存器分配恒定存储器内的地址空间以用于实例均匀化，并且确定前导码块还没有被执行并且波是要被执行的实例的第一波块尚未被执行并且波是要被执行的第一波，执行前导码代码块以将多个实例统一性存储在常量存储器中并且至少部分地基于执行前导码代码块，执行波使用所存储的不定内存的多个实例常量中的至少一个来执行所述多个波中的一个或多个

6. 发明申请

WO2017204909A1 PER-SHADER PREAMBLE FOR GRAPHICS PROCESSING 审中-公开
标题翻译：用于图形处理的每片预涂器
公开(公告)号：WO2017204909A1
公开(公告)日：2017-11-30
申请号：PCT/US2017/026835
申请日：2017-04-10
申请人： QUALCOMM INCORPORATED
发明人： CHEN, Lin , DU, Yun , GRUBER, Andrew Evan , JIAO, Guofang , YU, Chun , GARCIA GARCIA, David Rigel
IPC分类号： G06T1/20
摘要： A method for processing data in a graphics processing unit including receiving a code block of instructions common to a plurality of groups of threads of a shader, executing the code block of instructions common to the plurality of groups of threads of the shader creating a result by a group of threads of the plurality of groups of threads, storing the result of the code block of instructions common to the plurality of groups of threads of the shader in on-chip random access memory (RAM) accessible by each of the plurality of groups of threads, and upon a determination that storing the result of the code block of instructions common to the plurality of groups of threads of the shader has completed, returning the result of the code block of instructions common to the plurality of groups of threads of the shader from on-chip RAM.
摘要翻译：一种用于处理图形处理单元中的数据的方法，所述方法包括：接收着色器的多个线程组所共有的指令的代码块;执行所述多个着色器的线程通过多个线程组中的线程组创建结果，将片上随机存取存储器（RAM）中的着色器的多个线程组所共有的指令的代码块的结果存储在存储器中，可由多个线程组中的每一个线程访问，并且在确定存储着色器的多个线程组共有的指令代码块的结果已完成时，将指令的代码块的结果返回到来自片上RAM的着色器的多组线程。

7. 发明申请

WO2016077025A1 DYNAMIC PIPELINE FOR GRAPHICS PROCESSING 审中-公开
标题翻译：用于图形处理的动态管道
公开(公告)号：WO2016077025A1
公开(公告)日：2016-05-19
申请号：PCT/US2015/055767
申请日：2015-10-15
申请人： QUALCOMM INCORPORATED
发明人： LI, Liang , GRUBER, Andrew Evan , JIAO, Guofang , QI, Zhenyu , PITARYS, Gregory Steve , NOLAN, Scott William
IPC分类号： G06T1/20
CPC分类号： G06T1/20 , G09G5/18 , G09G2330/022
摘要： This disclosure describes an apparatus configured to process graphics data. The apparatus may include a fixed hardware pipeline configured to execute one or more functions on a current set of graphics data. The fixed hardware pipeline may include a plurality of stages including a bypassable portion of the plurality of stages. The apparatus may further include a shortcut circuit configured to route the current set of graphics data around the bypassable portion of the plurality of stages, and a controller positioned before the bypassable portion of the plurality of stages, the controller configured to selectively route the current set of graphics data to one of the shortcut circuit or the bypassable portion of the plurality of stages.
摘要翻译：本公开描述了被配置为处理图形数据的装置。该装置可以包括被配置为在当前图形数据集上执行一个或多个功能的固定硬件流水线。固定硬件管线可以包括多个级，包括多个级的可旁路部分。该装置还可以包括快速电路，其被配置为将当前图形数据集合围绕多个级的可旁路部分路由，以及位于多个级的可旁路部分之前的控制器，所述控制器被配置为选择性地路由当前集合的图形数据提供给多个阶段的快捷电路或可旁路部分中的一个。

8. 发明申请

WO2015199997A1 LOAD SCHEME FOR SHARED REGISTER IN GPU 审中-公开
标题翻译： GPU中共享注册表的加载方案
公开(公告)号：WO2015199997A1
公开(公告)日：2015-12-30
申请号：PCT/US2015/035332
申请日：2015-06-11
申请人： QUALCOMM INCORPORATED
发明人： DU, Yun , GRUBER, Andrew Evan , CHEN, Lin , JIAO, Guofang , YU, Chun
IPC分类号： G09G5/36 , G06T1/60
CPC分类号： G06T1/60 , G06T15/80 , G09G5/363 , G09G2352/00 , G09G2360/06
摘要： Techniques are described for determining whether data of a variable for each of a plurality of graphics items is same. If determined that the data is the same, the techniques store the data in a storage location of a specialized shared general purpose register that is associated with the variable.
摘要翻译：描述了用于确定多个图形项目中的每一个的变量的数据是否相同的技术。如果确定数据相同，则该技术将数据存储在与变量相关联的专用共享通用寄存器的存储位置中。

9. 发明申请

WO2022081293A1 CONFIGURABLE APRON SUPPORT FOR EXPANDED-BINNING 审中-公开
公开(公告)号：WO2022081293A1
公开(公告)日：2022-04-21
申请号：PCT/US2021/050670
申请日：2021-09-16
申请人： QUALCOMM INCORPORATED
发明人： BHIRAVABHATLA, Kalyan Kumar , GUMMIDIPUDI, Krishnaiah , SINGH, Ankit Kumar , GRUBER, Andrew Evan , AKKARAJU, Pavan Kumar , ALLA, Srihari Babu , NAGENDRA KUMAR, Jonnala Gadda , NIKAM, Vishwanath Shashikant
IPC分类号： G06T15/40
摘要： This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for configurable aprons for expanded binning. Aspects of the present disclosure include identifying one or more pixel tiles in at least one bin and determining edge information for each pixel tile of the one or more pixel tiles. The edge information may be associated with one or more pixels adjacent to each pixel tile. The present disclosure further describes determining whether at least one adjacent bin is visible based on the edge information for each pixel tile, where the at least one adjacent bin may be adjacent to the at least one bin.

10. 发明申请

WO2022076960A1 GPU HARDWARE-BASED DEPTH BUFFER DIRECTION TRACKING 审中-公开
公开(公告)号：WO2022076960A1
公开(公告)日：2022-04-14
申请号：PCT/US2021/071394
申请日：2021-09-08
申请人： QUALCOMM INCORPORATED
发明人： ALLA, Srihari Babu , RAMESH BABU, Adimulam , NAGENDRA KUMAR, Jonnala Gadda , SEETHARAMAIAH, Avinash , WANG, Tao , TANG, Xuefeng , FRISINGER, Thomas Edwin , GRUBER, Andrew Evan
IPC分类号： G06T15/00 , G06T15/40 , G06T1/20 , G09G5/36
摘要： The present disclosure relates to methods and apparatus for graphics processing. An example method generally includes receiving, at a graphics processing unit (GPU), a plurality of commands corresponding to a plurality of draws across a frame, each of the plurality of commands indicating a depth test direction with respect to a low-resolution depth (LRZ) buffer for the corresponding draw. The method generally includes maintaining, at the GPU, a LRZ status buffer to store a corresponding depth test direction for a first command in time of the plurality of commands processed by the GPU. The method generally includes disabling, at the GPU, use of the LRZ buffer for depth testing for any of the plurality of commands remaining unprocessed after processing a command of the plurality of commands having a different depth test direction than the corresponding depth test direction stored in the LRZ status buffer.

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