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1. 发明申请

WO2015176295A1 FEED-FORWARD BIAS CIRCUIT 审中-公开
标题翻译：进给前进偏置电路
公开(公告)号：WO2015176295A1
公开(公告)日：2015-11-26
申请号：PCT/CN2014/078223
申请日：2014-05-23
申请人： QUALCOMM INCORPORATED , SU, Wenjun , LEE, Chulkyu , ZHANG, Le , YIN, Guangming
发明人： SU, Wenjun , LEE, Chulkyu , ZHANG, Le , YIN, Guangming
IPC分类号： H02M3/07
CPC分类号： H03K3/011 , G05F1/00 , G05F3/205 , G05F3/242 , G05F3/262 , H02M3/07 , H03K5/159 , H03K17/145 , H03K19/00384 , H03K2217/0018
摘要： A feed-forward bias circuit biases body bias terminals of transistors of another circuit to compensate for PVT variations in the other circuit.In some aspects,the feed- forward bias circuit compensates for transistor process corners in a circuit by enabling the generation of different bias signals under different corner conditions.In some implementations,the feed-forward bias circuit is used to bias a delay circuit so that the delay circuit exhibits relatively constant delay characteristics over different PVT conditions.
摘要翻译：前馈偏置电路偏置另一电路的晶体管的体偏置端子，以补偿另一电路中的PVT变化。在一些方面，前馈偏置电路通过使能产生不同偏置来补偿电路中的晶体管工艺角在一些实施方案中，前馈偏置电路用于偏置延迟电路，使得延迟电路在不同的PVT条件下表现出相对恒定的延迟特性。

2. 发明申请

WO2015066867A1 CLOCK AND DATA DRIVERS WITH ENHANCED TRANSCONDUCTANCE AND SUPPRESSED OUTPUT COMMON-MODE 审中-公开
标题翻译：具有增强的交叉和抑制输出通用模式的时钟和数据驱动器
公开(公告)号：WO2015066867A1
公开(公告)日：2015-05-14
申请号：PCT/CN2013/086674
申请日：2013-11-07
申请人： QUALCOMM INCORPORATED , SU, Wenjun , YIN, Guangming , ZHU, Quanqing
发明人： SU, Wenjun , YIN, Guangming , ZHU, Quanqing
IPC分类号： H03F3/45
CPC分类号： H03F3/45762 , H03F1/0277 , H03F3/211 , H03F3/45183 , H03F3/45609 , H03F3/72 , H03F2200/555 , H03F2200/72 , H03F2203/45288 , H03F2203/45301 , H03F2203/45511 , H03F2203/45638 , H03F2203/45644 , H03F2203/45702 , H03K5/12
摘要： Maintaining a low output common-mode voltagein a driver is desirable. To maintain the low output common-mode voltage, apparatus, method, and means are proposed as follows: a first differential amplifier stage configured to provide a differential output for the apparatus; and a second differential amplifier stage configured to drive the first differential amplifier stage, the second differential amplifier stage including a pre-driver amplifier, a pair of n-stage units, and an input skew averaging unit, the input skew averaging unit configured to suppress the output common-mode voltage by splitting each of the pair of n-stage units into two half blocks and driving the blocks with complementary digital input to cancel out a skew in a gate-to-source voltage of the pair of n-stage units. Furthermore, two feed-forward capacitors are added to enhance the transconductance and operating speed of main transistors of the first differential amplifier stage.
摘要翻译：在驱动器中维持低输出共模电压是理想的。为了保持低输出共模电压，提出了如下装置，方法和装置：第一差分放大器级，被配置为提供装置的差分输出; 以及第二差分放大器级，被配置为驱动所述第一差分放大器级，所述第二差分放大器级包括预驱动器放大器，一对n级单元和输入偏斜平均单元，所述输入偏斜平均单元被配置为抑制通过将一对n级单元中的每一个分成两个半块并且以互补的数字输入驱动该块以消除该对n级单元的栅极 - 源极电压的偏斜的输出共模电压。此外，添加两个前馈电容器以增强第一差分放大器级的主晶体管的跨导和操作速度。

3. 发明公开

EP2815478A1 SURGE PROTECTION FOR DIFFERENTIAL INPUT/OUTPUT INTERFACES 有权
标题翻译：浪涌保护差分输入/输出接口
公开(公告)号：EP2815478A1
公开(公告)日：2014-12-24
申请号：EP12868467.7
申请日：2012-02-15
申请人： Qualcomm Incorporated
发明人： ZHU, Quanqing , YIN, Guangming
IPC分类号： H02H9/00 , H02H9/04
CPC分类号： H02H3/22 , H04L25/0272 , H04L25/028
摘要： An integrated circuit device (200) includes a first and second differential I/O pins (TRXP/TRXN) and a surge protection circuit. The surge protection circuit includes a protection transistor, a positive surge detection circuit, and a negative surge detection circuit. The protection transistor is connected between the first and second I/O pins and has a gate to receive a control signal (CTRL). The protection transistor is turned on to connect the I/O pins together if the positive surge detection circuit detects a positive surge energy on either of the I/O pins and/or if the negative surge detection circuit detects a negative surge energy on either of the I/O pins. The surge protection circuit provides increased protection for Ethernet device against undesirable energy in a manner that does not adversely affect the performance of the device.

4. 发明授权

EP2883305B1 MULTI-CASCODE AMPLIFIER BIAS TECHNIQUES 有权
公开(公告)号：EP2883305B1
公开(公告)日：2019-03-13
申请号：EP13750611.9
申请日：2013-08-08
申请人： Qualcomm Incorporated
发明人： SU, Wenjun , NARATHONG, Chiewcharn , YIN, Guangming , HADJICHRISTOS, Aristotele
IPC分类号： H03F1/22 , H03F3/193

5. 发明申请

WO2015176303A1 AUTO-DETECTION OF FIBER WORKING MODES 审中-公开
标题翻译：自动检测光纤工作模式
公开(公告)号：WO2015176303A1
公开(公告)日：2015-11-26
申请号：PCT/CN2014/078252
申请日：2014-05-23
申请人： QUALCOMM INCORPORATED , YU, Hongchun , YIN, Guangming , LI, Shuguang , ZHU, Quanging , YANG, Li
发明人： YU, Hongchun , YIN, Guangming , LI, Shuguang , ZHU, Quanging , YANG, Li
IPC分类号： H04L29/10
CPC分类号： H04L69/24
摘要： A network device is disclosed that may automatically detect the working mode of an associated communications link by searching an incoming data stream for a pattern including at least a predetermined number of continuous ones or zeros. The device is initialized to operate in a first mode compliant with 1000Base-X protocols. A SERDES associated with encoding the data stream, when operating in the first mode, ensures that there are no more than five continuous ones or zeros in the data stream. Thus, if the data stream contains the pattern of six or more continuous ones or zeros, then occurrence of the pattern results from oversampling the data stream, and thus the data rate of the network device is higher than the data rate of the communications link.
摘要翻译：公开了一种网络设备，其可以通过搜索输入数据流来自动检测相关联的通信链路的工作模式，所述模式包括至少预定数量的连续1或零。该器件被初始化为符合1000Base-X协议的第一模式。当在第一模式下操作时，与编码数据流相关联的SERDES确保数据流中不超过五个连续的或零。因此，如果数据流包含六个或更多个连续的或零的模式，则由于对数据流进行过采样而产生模式，因此网络设备的数据速率高于通信链路的数据速率。

6. 发明申请

WO2015067172A1 CLOCK AND DATA DRIVERS WITH ENHANCED TRANSCONDUCTANCE AND SUPPRESSED OUTPUT COMMON-MODE 审中-公开
标题翻译：具有增强的交叉和抑制输出通用模式的时钟和数据驱动器
公开(公告)号：WO2015067172A1
公开(公告)日：2015-05-14
申请号：PCT/CN2014/090318
申请日：2014-11-05
申请人： QUALCOMM INCORPORATED , SU, Wenjun , YIN, Guangming , ZHU, Quanqing
发明人： SU, Wenjun , YIN, Guangming , ZHU, Quanqing
IPC分类号： H03K5/12
CPC分类号： H03F3/45762 , H03F1/0277 , H03F3/211 , H03F3/45183 , H03F3/45609 , H03F3/72 , H03F2200/555 , H03F2200/72 , H03F2203/45288 , H03F2203/45301 , H03F2203/45511 , H03F2203/45638 , H03F2203/45644 , H03F2203/45702 , H03K5/12
摘要： Methods, apparatus, and means for maintaining a low output common-mode voltage in a driver are provided. One example apparatus includes a first differential amplifier stage configured to provide a differential output for the apparatus; and a second differential amplifier stage configured to drive the first differential amplifier stage, the second differential amplifier stage including a pair of pre-driver amplifiers, a pair of n-stage circuits, and an input skew averaging circuit, wherein each of the pair of n-stage units is split into two half blocks. The input skew averaging circuit is configured to suppress the output common-mode voltage by driving the blocks with complementary digital inputs to average out a skew in a gate-to-source voltage of the pair of n-stage circuits. For certain aspects, two feed-forward capacitors may be added to enhance the transconductance and operating speed of main transistors of the first differential amplifier stage.
摘要翻译：提供了用于在驱动器中维持低输出共模电压的方法，装置和装置。一个示例性设备包括：第一差分放大器级，被配置为提供用于该设备的差分输出; 以及第二差分放大器级，被配置为驱动所述第一差分放大器级，所述第二差分放大器级包括一对预驱动器放大器，一对n级电路和输入偏差均衡电路，其中， n级单元分为两个半块。输入偏斜平均电路被配置为通过用互补数字输入驱动块来抑制输出共模电压，以平均一对n级电路的栅极至源极电压的偏移。对于某些方面，可以添加两个前馈电容器以增强第一差分放大器级的主晶体管的跨导和工作速度。

7. 发明公开

EP3146622A1 FEED-FORWARD BIAS CIRCUIT 有权
标题翻译： VORSCHUB-VORSPANNUNGSSCHALTUNG
公开(公告)号：EP3146622A1
公开(公告)日：2017-03-29
申请号：EP14892709.8
申请日：2014-05-23
申请人： Qualcomm Incorporated
发明人： SU, Wenjun , LEE, Chulkyu , ZHANG, Le , YIN, Guangming
IPC分类号： H02M3/07
CPC分类号： H03K3/011 , G05F1/00 , G05F3/205 , G05F3/242 , G05F3/262 , H02M3/07 , H03K5/159 , H03K17/145 , H03K19/00384 , H03K2217/0018
摘要： A feed-forward bias circuit biases body bias terminals of transistors of another circuit to compensate for PVT variations in the other circuit. In some aspects, the feed-forward bias circuit compensates for transistor process corners in a circuit by enabling the generation of different bias signals under different corner conditions. In some implementations, the feed-forward bias circuit is used to bias a delay circuit so that the delay circuit exhibits relatively constant delay characteristics over different PVT conditions.
摘要翻译：前馈偏置电路偏置另一电路的晶体管的体偏置端子，以补偿另一电路中的PVT变化。在一些方面，前馈偏置电路通过在不同的拐角条件下产生不同的偏置信号来补偿电路中的晶体管工艺角。在一些实现中，前馈偏置电路用于偏置延迟电路，使得延迟电路在不同的PVT条件下表现出相对恒定的延迟特性。

8. 发明公开

EP3420637A1 METHOD FOR ROBUST PHASE-LOCKED LOOP DESIGN 审中-公开
公开(公告)号：EP3420637A1
公开(公告)日：2019-01-02
申请号：EP16892077.5
申请日：2016-03-03
申请人： Qualcomm Incorporated
发明人： YU, Hongchun , LIN, Weiran , LI, Shuguang , YIN, Guangming
IPC分类号： H03K7/00

9. 发明公开

EP2883305A1 MULTI-CASCODE AMPLIFIER BIAS TECHNIQUES 审中-公开
标题翻译：多编码放大器偏置技术
公开(公告)号：EP2883305A1
公开(公告)日：2015-06-17
申请号：EP13750611.9
申请日：2013-08-08
申请人： Qualcomm Incorporated
发明人： SU, Wenjun , NARATHONG, Chiewcharn , YIN, Guangming , HADJICHRISTOS, Aristotele
IPC分类号： H03F1/22 , H03F3/193
CPC分类号： H03F1/223 , H03F3/193
摘要： Techniques for generating bias voltages for a multi-cascode amplifier. In an aspect, a multi-cascode bias network is provided, each transistor in the bias network being a replica of a corresponding transistor in the multi-cascode amplifier, enabling accurate biasing of the transistors in the multi-cascode amplifier. In another aspect, a voltage supply for the multi-cascode amplifier is provided separately from a voltage supply for the replica bias network, to advantageously decouple variations in the amplifier voltage supply from the bias network voltage supply. In yet another aspect, the bias voltages of transistors in the multi-cascode amplifier may be configured by adjusting the impedance of resistive voltage dividers coupled to the transistor gate biases. As the gain of the amplifier depends on the bias voltages of the cascode amplifiers, the gain of the amplifier may be adjusted in this manner without introducing a variable gain element directly in the amplifier signal path.
摘要翻译：用于为多级共源共栅放大器生成偏置电压的技术。在一个方面中，提供了多级共射共基放大器偏置网络，偏置网络中的每个晶体管是多级共射共基放大器中的对应晶体管的复制品，其实现了多级共射共基放大器中的晶体管的精确偏置。在进一步的方面中，用于多级共射共基放大器的电压供应与用于复制品偏置网络的电压供应分离地提供，以有利地将放大器电压供应中的变化与偏置网络电压供应去耦。在又一方面，多级共射共基放大器中的晶体管的偏置电压可以通过调整耦合到晶体管栅极偏置的电阻分压器的阻抗来配置。由于放大器的增益取决于共源共栅放大器的偏置电压，所以放大器的增益可以以这种方式有利地被调整，而不会直接在放大器信号路径中引入可变增益元件。

10. 发明申请

WO2020062099A1 BODY BIASING TO BALANCE RDAC SWITCHES 审中-公开
公开(公告)号：WO2020062099A1
公开(公告)日：2020-04-02
申请号：PCT/CN2018/108485
申请日：2018-09-28
申请人： QUALCOMM INCORPORATED , MIAO, Guoqing , SU, Wenjun , YIN, Guangming , JIANG, Bo
发明人： MIAO, Guoqing , SU, Wenjun , YIN, Guangming , JIANG, Bo
IPC分类号： H03M1/66
摘要： The present disclosure describes aspects of body biasing to balance resistive digital-to-analog converter (RDAC) switches. In some aspects, a unit of an RDAC circuit includes a first switch having a source coupled to a voltage source and a drain coupled to a resistor of the RDAC unit. The RDAC unit also includes a second switch having a source coupled to a lower potential and a drain coupled to the resistor of the RDAC unit. A body biasing circuit provides a bias voltage that is applied to a body terminal of the first switch or the second switch of the RDAC unit. By applying the bias voltage to the body terminal of one or both of the RDAC unit switches, respective on-resistances of the switches can be balanced or matched. This may in turn improve RDAC circuit performance, such as by reducing total harmonic distortion associated with switch on-resistance mismatch.

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