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1. 发明申请

WO2017156241A1 INTELLIGENT EQUALIZATION FOR A THREE-TRANSMITTER MULTI-PHASE SYSTEM 审中-公开
标题翻译：一个三发多相系统的智能均衡
公开(公告)号：WO2017156241A1
公开(公告)日：2017-09-14
申请号：PCT/US2017/021531
申请日：2017-03-09
申请人： QUALCOMM INCORPORATED
发明人： LEE, Chulkyu , CHOU, Shih-Wei , WILEY, George
IPC分类号： H04L25/49 , H04L25/03 , H04L25/02 , H03K5/153 , H04L25/14
摘要： An intelligent equalization technique is provided for a three-transmitter system in which mid-level transitions are selectively emphasized and de-emphasized to conserve power and reduce data jitter.
摘要翻译：为三发射机系统提供智能均衡技术，其中中级转换被选择性地强调和去强调以节省功率并减少数据抖动。

2. 发明申请

WO2017039985A1 MULTIPHASE CLOCK DATA RECOVERY FOR A 3-PHASE INTERFACE 审中-公开
标题翻译：用于三相接口的多相时钟数据恢复
公开(公告)号：WO2017039985A1
公开(公告)日：2017-03-09
申请号：PCT/US2016/046211
申请日：2016-08-09
申请人： QUALCOMM INCORPORATED
发明人： DUAN, Ying , LEE, Chulkyu , CHOU, Shih-Wei , DANG, Harry , KWON, Ohjoon
IPC分类号： H04L7/033 , H04L25/49
CPC分类号： H03L7/0807 , H03L7/0812 , H04L7/0037 , H04L7/0087 , H04L7/033 , H04L7/0331 , H04L7/04 , H04L25/4917
摘要： Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method of data communication includes configuring a clock recovery circuit to provide a first clock signal that includes a pulse for each symbol transmitted on the interface, where symbols are transmitted on the interface at a first frequency, adjusting a loop delay of the clock recovery circuit to modify the first clock to have a second frequency that is no more that half the first frequency, where the clock recovery circuit generates a pulse in the first clock signal for a first of an integer number of symbols and suppresses pulse generation for other symbols in the integer number of symbols, configuring a clock generation circuit to provide a second clock signal, and capturing symbols from the interface using the first clock signal and the second clock signal.
摘要翻译：公开了通过多线，多相接口进行数据通信的方法，装置和系统。一种数据通信方法包括配置时钟恢复电路以提供第一时钟信号，该第一时钟信号包括在接口上发送的每个符号的脉冲，其中符号以第一频率在接口上发送，调整时钟恢复电路的环路延迟以修改第一时钟以具有不超过第一频率的第二频率的第二频率，其中时钟恢复电路在第一时钟信号中产生用于整数符号中的第一个的脉冲，并且抑制其他符号中的其他符号的脉冲产生整数个符号，配置时钟发生电路以提供第二时钟信号，以及使用第一时钟信号和第二时钟信号从接口捕获符号。

3. 发明申请

WO2017019223A1 TIME BASED EQUALIZATION FOR A C-PHY 3-PHASE TRANSMITTER 审中-公开
标题翻译：基于时间均衡的C-PHY三相发射机
公开(公告)号：WO2017019223A1
公开(公告)日：2017-02-02
申请号：PCT/US2016/039667
申请日：2016-06-27
申请人： QUALCOMM INCORPORATED
发明人： SEJPAL, Dhaval , LEE, Chulkyu , WILEY, George Alan
IPC分类号： H04L25/02 , H04L7/00 , H04L25/49 , H04L7/033 , H04L25/14
CPC分类号： H04B3/54 , H04B3/462 , H04L7/0087 , H04L7/033 , H04L25/0286 , H04L25/14 , H04L25/4917
摘要： A method, an apparatus, and a computer program product for data communication over a multi-wire, multi-phase interface are provided. The method may include providing a sequence of symbols to be transmitted on a 3-wire interface, each symbol in the sequence of symbols defining one of three voltage states for each wire of the 3-wire interface, driving all wires of the 3-wire interface to a common voltage state during a transition from a first transmitted symbol to a second transmitted symbol, driving each wire of the 3-wire interface in accordance with the second transmitted symbol after a predetermined delay. Each wire may be in a different voltage state from the other wires of the 3-wire interface during transmission of the each symbol. The common voltage state may lie between two of the three voltage states.
摘要翻译：提供了一种用于通过多线，多相接口进行数据通信的方法，装置和计算机程序产品。该方法可以包括提供要在3线接口上发送的符号序列，符号序列中的每个符号定义3线接口的每根线的三种电压状态之一，驱动3线的所有线在从第一传输符号到第二传输符号的转变期间接合到公共电压状态，在预定延迟之后根据第二传输符号驱动3线接口的每条线。在每个符号的传输期间，每根导线可能处于与3线接口的其它线不同的电压状态。公共电压状态可以位于三个电压状态中的两个之间。

4. 发明申请

WO2015108847A1 ANALOG BEHAVIOR MODELING FOR 3-PHASE SIGNALING 审中-公开
标题翻译：用于三相信号的模拟行为建模
公开(公告)号：WO2015108847A1
公开(公告)日：2015-07-23
申请号：PCT/US2015/011142
申请日：2015-01-13
申请人： QUALCOMM INCORPORATED
发明人： LI, Xiang , MIDHA, Nakul , RADHAKRISHNAN, Varun , LEE, Chulkyu
IPC分类号： H04L25/02 , G01R31/28 , H04B3/46 , H04L25/49
CPC分类号： H04M1/0266 , G01R31/2848 , H04B17/00 , H04L25/0272 , H04L25/4917
摘要： System, methods and apparatus are described that model analog behavior in a multi-wire, multi-phase communications link. A digital signal representative of a physical connection in a communications link and a virtual signal characterizing a three-phase signal transmitted over the physical connection are generated. The virtual signal may be configured to model one or more analog characteristics of the physical connection. The analog characteristics may include voltage states defining the three-phase signal. The analog characteristics of the physical connection include at least three voltage states corresponding to signaling states of the three-phase signal.
摘要翻译：描述了在多线，多相通信链路中模拟模拟行为的系统，方法和装置。生成表示通信链路中的物理连接的数字信号和表征通过物理连接发送的三相信号的虚拟信号。虚拟信号可以被配置为建模物理连接的一个或多个模拟特性。模拟特性可以包括定义三相信号的电压状态。物理连接的模拟特性包括对应于三相信号的信令状态的至少三个电压状态。

5. 发明申请

WO2015054297A1 EYE PATTERN TRIGGERING BASED ON SYMBOL TRANSITION 审中-公开
标题翻译：基于符号转换的眼睛图案触发
公开(公告)号：WO2015054297A1
公开(公告)日：2015-04-16
申请号：PCT/US2014/059548
申请日：2014-10-07
申请人： QUALCOMM INCORPORATED
发明人： WILEY, George Alan , LEE, Chulkyu
IPC分类号： H04L1/24 , H04L1/20
CPC分类号： H04L7/042 , H04L1/205 , H04L1/206 , H04L1/247 , H04L5/20 , H04L25/0272 , H04L25/0282 , H04L25/0294 , H04L25/0298 , H04L25/4917
摘要： System, methods and apparatus are described that facilitate tests and measurements related to multi-wire, multi-phase communications links. Information is transmitted in N-phase polarity encoded symbols and an eye pattern corresponding to the symbols is generated such that the symbols are aligned with a trigger for each symbol that corresponds to a clock edge used to sample the symbols. The eye pattern may be used to determine sufficiency of setup times in the communication links and other such characteristics defining a communications channel capabilities.
摘要翻译：描述了便于与多线，多相通信链路相关的测试和测量的系统，方法和装置。信息以N相极性编码的符号发送，并且生成与符号相对应的眼图，使得符号与对应于用于采样符号的时钟边缘的每个符号的触发对齐。眼图可以用于确定通信链路中的建立时间的充分性以及定义通信信道能力的其它这样的特性。

6. 发明申请

WO2009111208A1 MULTIPLE TRANSMITTER SYSTEM AND METHOD 审中-公开
标题翻译：多传输系统和方法
公开(公告)号：WO2009111208A1
公开(公告)日：2009-09-11
申请号：PCT/US2009/034943
申请日：2009-02-24
申请人： QUALCOMM INCORPORATED , LEE, Chulkyu , DAVIERWALLA, Anosh B. , WILEY, George A.
发明人： LEE, Chulkyu , DAVIERWALLA, Anosh B. , WILEY, George A.
IPC分类号： H04L5/20 , H04L25/02
CPC分类号： H04L25/0272 , H04L25/49
摘要： Systems and methods of data transmission are disclosed. In an embodiment, at least two transmitters are selectively activated and at least one transmitter is deactivated at a serial interface to transmit data via at least two distinct lines.
摘要翻译：公开了数据传输的系统和方法。在一个实施例中，选择性地激活至少两个发射机，并且至少一个发射机在串行接口处被去激活，以经由至少两条不同的线路传输数据。

7. 发明申请

WO2022019969A1 CHARGE PUMP BASED LOW DROPOUT REGULATOR 审中-公开
公开(公告)号：WO2022019969A1
公开(公告)日：2022-01-27
申请号：PCT/US2021/027440
申请日：2021-04-15
申请人： QUALCOMM INCORPORATED
发明人： PANDE, Darshan Chandrashekhar , LEE, Chulkyu , MOHAMAD, Sajin , LEKKALA, Suresh Naidu
IPC分类号： G05F1/575 , H02M3/07
摘要： In certain aspects, a voltage regulator includes a pass transistor coupled between an input of the voltage regulator and an output of the voltage regulator, and an amplifier having a first input coupled to a reference voltage, a second input coupled to the output of the voltage regulator via a feedback path, and an output. The voltage regulator also includes a voltage booster coupled between the output of the amplifier and a gate of the pass transistor. In certain aspects, the voltage booster includes a first capacitor and a second capacitor for double charge pumping. In certain aspects, a control circuit of the voltage booster is coupled to a voltage source that is independent of an output voltage of the amplifier.

8. 发明申请

WO2019240853A1 INDEPENDENT PAIR 3-PHASE EYE SAMPLING CIRCUIT 审中-公开
公开(公告)号：WO2019240853A1
公开(公告)日：2019-12-19
申请号：PCT/US2019/019265
申请日：2019-02-22
申请人： QUALCOMM INCORPORATED
发明人： WILEY, George Alan , LEE, Chulkyu
IPC分类号： H04L7/033 , H04L7/00 , G06F13/42 , H04L25/49
摘要： Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method includes recovering a first clock signal from transitions between pairs of symbols representative of successive signaling states of a 3-wire interface, where a pulse in the first clock signal is generated in response to an earliest-occurring transition between the first and second symbols in one of three difference signals representative of differences in state between two wires, determining direction of voltage change of a first transition detected on a first difference signal, providing a value selected based on the direction of voltage change as value of the first difference signal in the second symbol, and providing a value of a second difference signal captured during the first symbol as the value of the second difference signal when the second difference signal does not transition between the first symbol and the second symbol.

9. 发明申请

WO2019212630A1 CALIBRATION PATTERN AND DUTY-CYCLE DISTORTION CORRECTION FOR CLOCK DATA RECOVERY IN A MULTI-WIRE, MULTI-PHASE INTERFACE 审中-公开
公开(公告)号：WO2019212630A1
公开(公告)日：2019-11-07
申请号：PCT/US2019/020192
申请日：2019-03-01
申请人： QUALCOMM INCORPORATED
发明人： DUAN, Ying , DIXIT, Abhay , CHOU, Shih-Wei , LEE, Chulkyu
IPC分类号： H04L7/033 , H04L25/49 , G06F13/42
摘要： Methods, apparatus, and systems for calibration and correction of data communications over a multi-wire, multi-phase interface are disclosed. In particular, calibration is provided for data communication devices coupled to a 3-line interface. The calibration includes generating and transmitting a calibration pattern on the 3-line interface, where the generation of the pattern includes toggling two of three interface lines from one voltage level to another voltage level over a predetermined time interval. Furthermore, the generation of the pattern includes maintaining a remaining third interface line at a common mode voltage level over the predetermined time interval, wherein only a single transition occurs for the predetermined time interval. Calibration data may then be derived in a receiver device using the transmitted calibration pattern.

10. 发明申请

WO2015021262A1 RUN-LENGTH DETECTION AND CORRECTION 审中-公开
标题翻译：运行长度检测和校正
公开(公告)号：WO2015021262A1
公开(公告)日：2015-02-12
申请号：PCT/US2014/050118
申请日：2014-08-07
申请人： QUALCOMM INCORPORATED
发明人： WILEY, George Alan , LEE, Chulkyu
IPC分类号： H04L25/02 , H04L25/14 , H04L25/49
CPC分类号： H04L1/0056 , H04L1/0014 , H04L25/0272 , H04L25/14 , H04L25/49 , H04L43/0811
摘要： System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. The apparatus may determine whether a run-length violation will occur or is likely to occur if a first sequence of symbols provided by a mapper of an M-Wire N-Phase encoder is transmitted on a plurality of wires. A second sequence of symbols may be substituted for the first sequence of symbols. The second sequence of symbols may comprise a surplus sequence of symbols that is not used for mapping data in the mapper.
摘要翻译：描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。如果由M-Wire N相编码器的映射器提供的第一符号序列在多条导线上发送，则该装置可以确定是否发生行程长度违规或可能发生。符号的第二序列可以代替第一符号序列。第二符号序列可以包括不用于映射器中的数据的多余符号序列。

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