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1. 发明申请

WO2016126862A1 MULTI-MODULATION FOR DATA-LINK POWER REDUCTION AND THROUGHPUT ENHANCEMENT 审中-公开
标题翻译：数据链路功率减少和通过增强的多调制
公开(公告)号：WO2016126862A1
公开(公告)日：2016-08-11
申请号：PCT/US2016/016433
申请日：2016-02-03
申请人： QUALCOMM INCORPORATED
发明人： MISHRA, Lalan Jee , WILEY, George , WIETFELDT, Richard , PANIAN, James
IPC分类号： H03M5/08 , H03M5/12
CPC分类号： H04L25/4902 , H03M5/08 , H03M5/12 , H04L7/08 , H04L27/2092
摘要： A multi-modulation scheme is provided that combines pulse-width modulation and phase modulation.
摘要翻译：提供组合脉宽调制和相位调制的多调制方案。

2. 发明公开

EP3690665A1 LOW-POWER AND LOW-LATENCY DEVICE ENUMERATION WITH CARTESIAN ADDRESSING 审中-公开
公开(公告)号：EP3690665A1
公开(公告)日：2020-08-05
申请号：EP20164699.9
申请日：2016-03-23
申请人： QUALCOMM Incorporated
发明人： MISHRA, Lalan Jee , PANIAN, James , WIETFELDT, Richard
IPC分类号： G06F13/42
摘要： An enumeration technique is provided that requires no pre-assignment of addresses to slave devices connected through P2P links to a host device. With regard to any P2P link between devices, one device has a master interface and the remaining device has a slave interface. To distinguish between the master and slave interfaces, a master/slave status bit may be used. Each P2P link has a link ID that may be concatenated with the status bit for a corresponding interface (slave or master) to form a node ID. The host device receives a unique concatenated address from each slave device that represents a concatenation of the node ID for the slave and the node ID for any intervening interfaces between the slave device and the host device. The host device then assigns a unique Cartesian address to each slave device.

3. 发明公开

EP3254376A1 MULTI-MODULATION FOR DATA-LINK POWER REDUCTION AND THROUGHPUT ENHANCEMENT 审中-公开
标题翻译：数据链路功率降低和吞吐量增强的多重调制
公开(公告)号：EP3254376A1
公开(公告)日：2017-12-13
申请号：EP16708002.7
申请日：2016-02-03
申请人： Qualcomm Incorporated
发明人： MISHRA, Lalan Jee , WILEY, George , WIETFELDT, Richard , PANIAN, James
IPC分类号： H03M5/08 , H03M5/12
CPC分类号： H04L25/4902 , H03M5/08 , H03M5/12 , H04L7/08 , H04L27/2092
摘要： A multi-modulation scheme is provided that combines pulse-width modulation and phase modulation.

4. 发明公开

EP3283969A1 ENHANCED VIRTUAL GPIO WITH MULTI-MODE MODULATION 有权
标题翻译：使用多模调制增强了虚拟GPIO
公开(公告)号：EP3283969A1
公开(公告)日：2018-02-21
申请号：EP16721296.8
申请日：2016-04-13
申请人： QUALCOMM INCORPORATED
发明人： MISHRA, Lalan Jee , WIETFELDT, Richard , PRASAD, Mohit , PANIAN, James
IPC分类号： G06F13/38
摘要： A multi-modulation scheme is provided that combines pulse-width modulation and phase modulation to transmit a plurality of GPIO signals as virtual GPIO signals.

5. 发明授权

EP3283969B1 ENHANCED VIRTUAL GPIO WITH MULTI-MODE MODULATION 有权
公开(公告)号：EP3283969B1
公开(公告)日：2020-05-27
申请号：EP16721296.8
申请日：2016-04-13
申请人： QUALCOMM INCORPORATED
发明人： MISHRA, Lalan Jee , WIETFELDT, Richard , PRASAD, Mohit , PANIAN, James
IPC分类号： G06F13/38

6. 发明公开

EP3274856A1 LOW-POWER AND LOW-LATENCY DEVICE ENUMERATION WITH CARTESIAN ADDRESSING 有权
标题翻译：采用C地址寻址的低功耗和低延迟器件枚举
公开(公告)号：EP3274856A1
公开(公告)日：2018-01-31
申请号：EP16713271.1
申请日：2016-03-23
申请人： Qualcomm Incorporated
发明人： MISHRA, Lalan Jee , PANIAN, James , WIETFELDT, Richard
IPC分类号： G06F13/42
CPC分类号： H04L67/1091 , G06F13/4247 , G06F2213/0052 , H04L61/2007 , H04L61/604
摘要： An enumeration technique is provided that requires no pre-assignment of addresses to slave devices connected through P2P links to a host device. With regard to any P2P link between devices, one device has a master interface and the remaining device has a slave interface. To distinguish between the master and slave interfaces, a master/slave status bit may be used. Each P2P link has a link ID that may be concatenated with the status bit for a corresponding interface (slave or master) to form a node ID. The host device receives a unique concatenated address from each slave device that represents a concatenation of the node ID for the slave and the node ID for any intervening interfaces between the slave device and the host device. The host device then assigns a unique Cartesian address to each slave device.

7. 发明申请

WO2016168369A1 ENHANCED VIRTUAL GPIO WITH MULTI-MODE MODULATION 审中-公开
标题翻译：具有多模式调制的增强型虚拟GPIO
公开(公告)号：WO2016168369A1
公开(公告)日：2016-10-20
申请号：PCT/US2016/027377
申请日：2016-04-13
申请人： QUALCOMM INCORPORATED
发明人： MISHRA, Lalan Jee , WIETFELDT, Richard , PRASAD, Mohit , PANIAN, James
IPC分类号： G06F13/38
CPC分类号： G06F13/4282 , G06F13/1678 , G06F13/385 , H03M13/19 , Y02D10/14 , Y02D10/151
摘要： A multi-modulation scheme is provided that combines pulse-width modulation and phase modulation to transmit a plurality of GPIO signals as virtual GPIO signals.
摘要翻译：提供了组合脉冲宽度调制和相位调制以将多个GPIO信号作为虚拟GPIO信号发送的多调制方案。

8. 发明申请

WO2016154347A1 LOW-POWER AND LOW-LATENCY DEVICE ENUMERATION WITH CARTESIAN ADDRESSING 审中-公开
标题翻译：低功耗和低功耗设备与卡特彼勒寻址
公开(公告)号：WO2016154347A1
公开(公告)日：2016-09-29
申请号：PCT/US2016/023826
申请日：2016-03-23
申请人： QUALCOMM INCORPORATED
发明人： MISHRA, Lalan Jee , PANIAN, James , WIETFELDT, Richard
IPC分类号： G06F13/42
CPC分类号： H04L67/1091 , G06F13/4247 , G06F2213/0052 , H04L61/2007 , H04L61/604
摘要： An enumeration technique is provided that requires no pre-assignment of addresses to slave devices connected through P2P links to a host device. With regard to any P2P link between devices, one device has a master interface and the remaining device has a slave interface. To distinguish between the master and slave interfaces, a master/slave status bit may be used. Each P2P link has a link ID that may be concatenated with the status bit for a corresponding interface (slave or master) to form a node ID. The host device receives a unique concatenated address from each slave device that represents a concatenation of the node ID for the slave and the node ID for any intervening interfaces between the slave device and the host device. The host device then assigns a unique Cartesian address to each slave device.
摘要翻译：提供了一种枚举技术，其不需要将通过P2P链接连接到主机设备的从设备的地址预先分配。关于设备之间的任何P2P链路，一个设备具有主接口，其余设备具有从接口。为了区分主从接口，可以使用主/从状态位。每个P2P链路具有可以与相应接口（从属或主机）的状态位连接以形成节点ID的链路ID。主设备从每个从设备接收代表从设备的节点ID的级联和从设备与主设备之间的任何介入接口的节点ID的唯一的级联地址。然后，主机设备为每个从设备分配唯一的笛卡尔地址。

9. 发明申请

WO2016053796A1 CLOCK-FREE DUAL-DATA-RATE LINK WITH BUILT-IN FLOW CONTROL 审中-公开
标题翻译：具有内置流量控制的无时钟双数据速率链路
公开(公告)号：WO2016053796A1
公开(公告)日：2016-04-07
申请号：PCT/US2015/052351
申请日：2015-09-25
申请人： QUALCOMM INCORPORATED
发明人： MISHRA, Lalan, Jee , WIETFELDT, Richard , PANIAN, James
IPC分类号： G06F13/42
CPC分类号： G06F1/3234 , G06F1/3243 , G06F13/4286 , G06F13/4295
摘要： A dual-data-rate interface is provided that includes a transmitter driving a transmit pin coupled to a receive pin of a receiver. The receiver drives its receive pin with cycles of a fetch clock. The transmitter responds to each edge of the fetch clock by transmitting a bit over the transmit pin to the receiver.
摘要翻译：提供了一种双数据速率接口，其包括驱动耦合到接收器的接收引脚的发送引脚的发射器。接收器通过提取时钟周期驱动其接收引脚。发送器通过将发送引脚上的位发送到接收器来响应获取时钟的每个边沿。

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