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1. 发明申请

WO2022060479A1 REAL-TIME CONTROL COMPLIANT RADIO FREQUENCY COEXISTENCE MANAGEMENT BUS 审中-公开
公开(公告)号：WO2022060479A1
公开(公告)日：2022-03-24
申请号：PCT/US2021/044373
申请日：2021-08-03
申请人： QUALCOMM INCORPORATED
发明人： MISHRA, Lalan Jee , PRASAD, Mohit Kishore , WIETFELDT, Richard Dominic , KHAN, Irfan
IPC分类号： G06F13/42
摘要： Systems, methods, and apparatus for multi-drop coexistence management are described. A data communication apparatus has a bus interface that couples the data communication apparatus to a serial bus and a controller configured to determine that a datagram received from the serial bus is addressed to a register address corresponding to a coexistence management identifier, activate a line driver of the bus interface circuit that is coupled to a data line of the serial bus during a portion of a first payload of the datagram when one or more coexistence management messages are ready for sending from the slave device, where the portion of the first payload of the datagram is allocated for use of the apparatus, and transmit a first coexistence management message in the portion of the first payload of the datagram that is allocated for use of the data communication apparatus.

2. 发明申请

WO2019217077A1 LATENCY OPTIMIZED I3C VIRTUAL GPIO WITH CONFIGURABLE OPERATING MODE AND DEVICE SKIP 审中-公开
公开(公告)号：WO2019217077A1
公开(公告)日：2019-11-14
申请号：PCT/US2019/028860
申请日：2019-04-24
申请人： QUALCOMM INCORPORATED
发明人： MISHRA, Lalan Jee , PITIGOI-ARON, Radu , WIETFELDT, Richard Dominic , GRAIF, Sharon , AMARILIO, Lior , HALDAR, Kishalay , NISHRY, Oren
IPC分类号： G06F13/42 , G06F13/12
摘要： Systems, methods, and apparatus for communicating virtual GPIO information generated at multiple source devices and directed to multiple destination devices. A method performed at a device coupled to a serial bus includes generating first virtual GPIO state information representative of state of one or more physical GPIO output pins, asserting a request to transmit the first virtual GPIO state information by driving a data line of the serial bus from a first state to a second state after a start code has been transmitted on a serial bus and before a first clock pulse is transmitted on a clock line of the serial bus, transmitting the first virtual GPIO state information as a first set of bits in a data frame associated with the start code, and receiving second virtual GPIO state information in a second set of bits in the data frame.

3. 发明申请

WO2019148111A1 IN-DATAGRAM CRITICAL-SIGNALING USING PULSE-COUNT-MODULATION FOR I3C BUS 审中-公开
公开(公告)号：WO2019148111A1
公开(公告)日：2019-08-01
申请号：PCT/US2019/015440
申请日：2019-01-28
申请人： QUALCOMM INCORPORATED
发明人： MISHRA, Lalan Jee , WIETFELDT, Richard Dominic , PITIGOI-ARON, Radu
IPC分类号： G06F13/42 , G06F13/376
摘要： Systems, methods, and apparatus are described that enable a device to indicate availability of priority data to be communicated over a half-duplex serial bus without waiting for an ongoing transmission to be completed. In-datagram critical signaling is accommodated without breaking backward compatibility. A method implemented at a transmitting device coupled to a serial bus includes transmitting a data byte over a first line of the serial bus to a receiving device in accordance with a clock signal transmitted by a master device on a second line of the serial device, detecting a first pulse on the first line of the serial bus during a cycle of the clock signal designated for an acknowledgement or negative acknowledgement by the second device, and processing an alert indicated by the first pulse.

4. 发明申请

WO2019143405A1 DATA LANE VALIDATION PROCEDURE FOR MULTILANE PROTOCOLS 审中-公开
公开(公告)号：WO2019143405A1
公开(公告)日：2019-07-25
申请号：PCT/US2018/062903
申请日：2018-11-28
申请人： QUALCOMM INCORPORATED
发明人： PITIGOI-ARON, Radu , MISHRA, Lalan Jee , WIETFELDT, Richard, Dominic
IPC分类号： G06F13/42
摘要： Systems, methods, and apparatus are described that enable a serial bus to be operated in multiple modes that employ additional wires for communicating data such that the bus width may be dynamically extended to improve bandwidth and/or throughput. One method includes transmitting a set of frames or sequences of symbols configured to carry up to a maximum number of data bytes over the serial bus, transmitting control signaling over a first data lane and the clock lane after the set of frames or sequences of symbols has been transmitted, and transmitting a first signal over a second data lane while transmitting the control signaling that may indicate whether the set of frames or sequences of symbols includes padding. The first signal may indicate a number of valid bytes or words in the set of frames or sequences of symbols.

5. 发明申请

WO2019112700A1 CLOCK LINE DRIVING FOR SINGLE-CYCLE DATA OVER CLOCK SIGNALING AND PRE-EMPTION REQUEST IN A MULTI-DROP BUS 审中-公开
公开(公告)号：WO2019112700A1
公开(公告)日：2019-06-13
申请号：PCT/US2018/057018
申请日：2018-10-23
申请人： QUALCOMM INCORPORATED
发明人： MISHRA, Lalan Jee , WIETFELDT, Richard Dominic
IPC分类号： G06F13/42 , G06F13/376
摘要： Systems, methods, and apparatus are described that enable single-cycle preemption on a serial bus. An apparatus is coupled to a serial bus through a bus interface and includes a controller configured to provide a clock signal on the first line of the serial bus, transmit data on a second line of the serial bus in accordance with timing provided by the clock signal, cause the line driver to enter a high impedance state after transmitting a first edge in the clock signal while transmitting the data on the second line, detect a first pulse on the clock signal while the line driver is in the high impedance state, cause the line driver to exit the high impedance state prior to transmitting a second edge in the clock signal, and initiate bus arbitration after detecting the first pulse. The first edge and the second edge may transition in opposite directions.

6. 发明申请

WO2018231710A1 METHOD TO ESTABLISH OPERATING CONFIGURATION IN A VGMI INTERFACE 审中-公开
公开(公告)号：WO2018231710A1
公开(公告)日：2018-12-20
申请号：PCT/US2018/036922
申请日：2018-06-11
申请人： QUALCOMM INCORPORATED
发明人： WIETFELDT, Richard Dominic , MISHRA, Lalan Jee
IPC分类号： G06F13/38
CPC分类号： G06F9/44505 , G06F13/102 , G06F13/385 , G06F2009/45579
摘要： In an aspect, an apparatus initializes a virtual general-purpose input/output and messaging interface based on at least one of a first mode configuration setting or a first protocol configuration setting. The apparatus is able to communicate with a device over the virtual general-purpose input/output and messaging interface using at least one of the first mode configuration setting or the first protocol configuration setting. The apparatus changes the first mode configuration setting of the virtual general-purpose input/output and messaging interface to a second mode configuration setting and/or changes the first protocol configuration setting of the virtual general-purpose input/output and messaging interface to a second protocol configuration setting. The apparatus communicates with the device over the virtual general-purpose input/output and messaging interface using at least one of the second mode configuration setting or the second protocol configuration setting.

7. 发明申请

WO2018026871A1 TRIPLE-DATA-RATE TECHNIQUE FOR A SYNCHRONOUS LINK 审中-公开
标题翻译：一种同步链路的三数据速率技术
公开(公告)号：WO2018026871A1
公开(公告)日：2018-02-08
申请号：PCT/US2017/044990
申请日：2017-08-01
申请人： QUALCOMM INCORPORATED
发明人： MISHRA, Lalan Jee , WIETFELDT, Richard Dominic , O'SHEA, Helena Deirdre
IPC分类号： G06F13/42
摘要： Systems, methods, and apparatus for transmitting additional information over a synchronous serial bus are described. A method performed at a transmitting device coupled to the serial bus includes providing first data in a data signal to be transmitted on a first wire of a multi-wire serial bus, providing a series of pulses in a clock signal to be transmitted on a second wire of a multi-wire serial bus, where each pulse has a rising edge and a falling edge, each edge being aligned with a different bit of the first data. The method may include encoding second data in the clock signal by controlling a duration of each pulse in the series of pulses based on a value of one or more bits of the second data, and transmitting the data signal and the clock signal over the serial bus.
摘要翻译：描述了用于通过同步串行总线传输附加信息的系统，方法和装置。在耦合到串行总线的发送设备处执行的方法包括：提供要在多线串行总线的第一导线上发送的数据信号中的第一数据，在时钟信号中提供要在第二导线上发送的一系列脉冲多线串行总线的导线，其中每个脉冲具有上升沿和下降沿，每个边沿与第一数据的不同位对齐。该方法可以包括通过基于第二数据的一个或多个比特的值来控制该系列脉冲中的每个脉冲的持续时间来编码时钟信号中的第二数据，并且通过串行总线传输数据信号和时钟信号

8. 发明申请

WO2017192198A1 IMAGING USING MULTIPLE UNMANNED AERIAL VEHICLES 审中-公开
标题翻译：使用多台无人机进行成像
公开(公告)号：WO2017192198A1
公开(公告)日：2017-11-09
申请号：PCT/US2017/018387
申请日：2017-02-17
申请人： QUALCOMM INCORPORATED
发明人： MISHRA, Lalan Jee , CORLETO MENA, Jose G.
IPC分类号： G05D1/10 , G03B15/03
摘要： An aerial imaging system and method of aerially capturing an image including a first unmanned aerial vehicle (UAV) and a second UAV. The first UAV includes a camera and may be configured to receive input from an operator. The second UAV may be configured to dock with and deploy from the first UAV. The second UAV includes a light configured to provide remote illumination for the camera. The light on the second UAV may be activated to illuminate a target of photography by the camera while the second UAV is flown separate from the first UAV.
摘要翻译：包括第一无人飞行器（UAV）和第二无人飞行器的空中成像系统和空中捕捉图像的方法。第一架UAV包括一台摄像机，并可配置为接收来自操作员的输入。第二UAV可以被配置为与第一UAV对接并且从第一UAV部署。第二台无人机包括一个配置为照相机提供远程照明的灯。当第二无人机与第一无人机分离时，第二无人机上的灯可以被激活以照亮摄像机的拍摄目标。

9. 发明申请

WO2016105672A1 SYSTEM AND METHOD FOR DYNAMIC ROBOT MANIPULATOR SELECTION 审中-公开
标题翻译：动态机器人操纵器选择的系统与方法
公开(公告)号：WO2016105672A1
公开(公告)日：2016-06-30
申请号：PCT/US2015/059408
申请日：2015-11-06
申请人： QUALCOMM INCORPORATED
发明人： MISHRA, Lalan Jee , CORLETO, Jose Gilberto
IPC分类号： B25J9/16 , B25J15/04
CPC分类号： B25J15/0466 , B25J9/1602 , B25J15/0483 , G05B2219/39468 , G05B2219/40302 , Y10S901/02 , Y10S901/09
摘要： A robotic system includes a set of manipulators selectively and operatively coupled via a common interconnect to a control module. The control module is responsive to parameters recorded while performing a defined task with members selected from the set of manipulators. The parameters are applied to a selection engine that identifies an optimal member from the set of manipulators for a defined task.
摘要翻译：机器人系统包括通过公共互连选择性地和可操作地耦合到控制模块的一组操纵器。控制模块响应于在从一组操纵器中选择的成员执行定义的任务时记录的参数。这些参数被应用于从定义的任务的操纵器集合中识别最佳成员的选择引擎。

10. 发明申请

WO2022060478A1 ERROR SIGNALING WINDOWS FOR PHASE-DIFFERENTIAL PROTOCOLS 审中-公开
公开(公告)号：WO2022060478A1
公开(公告)日：2022-03-24
申请号：PCT/US2021/044368
申请日：2021-08-03
申请人： QUALCOMM INCORPORATED
发明人： PITIGOI-ARON, Radu , WIETFELDT, Richard Dominic , MISHRA, Lalan Jee
IPC分类号： G06F13/42 , H04L29/00 , H04L25/49
摘要： Systems, methods, and apparatus for error signaling on a serial bus are described. An apparatus includes a bus interface configured to couple the apparatus to a serial bus, a phase-differential decoder configured to decode data from transitions between pairs of symbols in a sequence of symbols received from the serial bus, each symbol being representative of signaling state of the serial bus, and a processor configured to detect an indicator of an error signaling window in signaling state of two wires of the serial bus, the indicator of the error signaling window corresponding to a prohibited combination of symbols or a delay in control signaling, signaling an error through the bus interface during the error signaling window when an error is detected in the sequence of symbols or in timing of the indicator of the error signaling window.

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