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1. 发明申请

WO2021091643A1 METHODS AND APPARATUS FOR REDUCING THE TRANSFER OF RENDERING INFORMATION 审中-公开
公开(公告)号：WO2021091643A1
公开(公告)日：2021-05-14
申请号：PCT/US2020/054576
申请日：2020-10-07
申请人： QUALCOMM INCORPORATED
发明人： WANG, Tao , KHANDELWAL, Shambhoo , GRUBER, Andrew Evan , YU, Shangmei , GAO, Jing , SHAO, Junmei , FRISINGER, Thomas Edwin , HAMMERSTONE, Rick
IPC分类号： G06T1/20 , G06T15/00
摘要： The present disclosure relates to methods and apparatus for graphics processing. Aspects of the present disclosure can determine a portion of a display area, where the portion of the display area is determined based on display content of the display area. Further, aspects of the present disclosure can communicate display information corresponding to the determined portion of the display area. Additionally, aspects of the present disclosure can update the display information corresponding to the determined portion of the display area. Aspects of the present disclosure can also communicate the updated display information corresponding to the determined portion of the display area. Aspects of the present disclosure can also render at least some display content of the display area corresponding to the determined portion of the display area. In some aspects, the updated display information can be based on the rendered display content of the display area.

2. 发明申请

WO2017048381A1 STORING BANDWIDTH-COMPRESSED GRAPHICS DATA 审中-公开
标题翻译：存储带宽压缩图形数据
公开(公告)号：WO2017048381A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/044975
申请日：2016-08-01
申请人： QUALCOMM INCORPORATED
发明人： GRUBER, Andrew Evan , HILL, Rexford Alan , KHANDELWAL, Shambhoo
IPC分类号： G06T1/20 , G06T1/60 , G06F12/02 , G06T11/40
CPC分类号： G06T1/60 , G06F12/0207 , G06F2212/401 , G06T1/20 , G06T11/40 , G06T2210/08
摘要： A computing device may allocate a plurality of blocks in the memory, wherein each of the plurality of blocks is of a uniform fixed size in the memory. The computing device may further store a plurality of bandwidth-compressed graphics data into the respective plurality of blocks in the memory, wherein one or more of the plurality of bandwidth-compressed graphics data each has a size that is smaller than the fixed size. The computing device may further store data associated with the plurality of bandwidth-compressed graphics data into unused space of one or more of the plurality of blocks that contains the respective one or more of the plurality of bandwidth-compressed graphics data.
摘要翻译：计算设备可以在存储器中分配多个块，其中多个块中的每个块在存储器中具有均匀的固定大小。计算设备还可以将多个带宽压缩的图形数据存储到存储器中的相应的多个块中，其中多个带宽压缩图形数据中的一个或多个具有小于固定大小的尺寸。计算设备还可以将与多个带宽压缩的图形数据相关联的数据存储在多个块中的一个或多个块的未使用空间中，该多个块包含多个带宽压缩图形数据中的相应一个或多个。

3. 发明公开

EP4055552A1 METHODS AND APPARATUS FOR REDUCING THE TRANSFER OF RENDERING INFORMATION 审中-实审
公开(公告)号：EP4055552A1
公开(公告)日：2022-09-14
申请号：EP20799888.1
申请日：2020-10-07
申请人： QUALCOMM INCORPORATED
发明人： WANG, Tao , KHANDELWAL, Shambhoo , GRUBER, Andrew Evan , YU, Shangmei , GAO, Jing , SHAO, Junmei , FRISINGER, Thomas Edwin , HAMMERSTONE, Rick
IPC分类号： G06T1/20 , G06T15/00

4. 发明公开

EP3061070A2 SELECTIVELY MERGING PARTIALLY-COVERED TILES TO PERFORM HIERARCHICAL Z-CULLING 有权
标题翻译：于执行分级结构Z剔除部分覆盖瓦片选择性归并
公开(公告)号：EP3061070A2
公开(公告)日：2016-08-31
申请号：EP14789461.2
申请日：2014-10-08
申请人： Qualcomm Incorporated
发明人： WANG, Tao , GRUBER, Andrew Evan , KHANDELWAL, Shambhoo
IPC分类号： G06T15/00 , G06T15/40
CPC分类号： G06T15/405 , G06T1/60 , G06T15/005
摘要： This disclosure describes techniques for performing hierarchical z-culling in a graphics processing system. In some examples, the techniques may involve selectively merging partially-covered source tiles for a tile location into a fully-covered merged source tile based on whether conservative farthest z-values for the partially-covered source tiles are nearer than a culling z-value for the tile location, and using a conservative farthest z-value associated with the fully-covered merged source tile to update the culling z-value for the tile location. In further examples, the techniques may use a cache unit that is not associated with an underlying memory to store conservative farthest z-values and coverage masks for merged source tiles. The capacity of the cache unit may be smaller than the size of cache needed to store merged source tile data for all of the tile locations in a render target.
摘要翻译：本发明描述用于执行分级结构Z剔除在图形处理系统。在一些实例中，所述技术用于执行分级结构Z剔除可以涉及选择性地合并部分覆盖源瓦片用于图块位置为基于一个完全覆盖的合并源瓦是否对所述部分覆盖的源瓦片保守最远z值比用于图块位置的剔除z值越接近，并且使用与所述完全覆盖的合并源块相关联的一个保守的最远z值来更新剔除ž 对于瓷砖的位置值。在另外的实例中，用于执行分级结构Z剔除可使用高速缓存单元的技术并没有与在底层存储器相关联来存储保守最远z值和覆盖遮罩用于合并源瓷砖。所述高速缓存单元的容量可以比为所有瓦片位置存储在一个渲染目标合并源瓦片数据所需高速缓存的大小要小。

5. 发明公开

EP3350766A1 STORING BANDWIDTH-COMPRESSED GRAPHICS DATA 有权
公开(公告)号：EP3350766A1
公开(公告)日：2018-07-25
申请号：EP16753760.4
申请日：2016-08-01
申请人： Qualcomm Incorporated
发明人： GRUBER, Andrew Evan , HILL, Rexford Alan , KHANDELWAL, Shambhoo
IPC分类号： G06T1/20 , G06T1/60 , G06F12/02 , G06T11/40
摘要： A computing device may allocate a plurality of blocks in the memory, wherein each of the plurality of blocks is of a uniform fixed size in the memory. The computing device may further store a plurality of bandwidth-compressed graphics data into the respective plurality of blocks in the memory, wherein one or more of the plurality of bandwidth-compressed graphics data each has a size that is smaller than the fixed size. The computing device may further store data associated with the plurality of bandwidth-compressed graphics data into unused space of one or more of the plurality of blocks that contains the respective one or more of the plurality of bandwidth-compressed graphics data.

6. 发明申请

WO2017052750A2 DYNAMICALLY SWITCHING BETWEEN LATE DEPTH TESTING AND CONSERVATIVE DEPTH TESTING 审中-公开
标题翻译：深度测试和保守深度测试之间的动态切换
公开(公告)号：WO2017052750A2
公开(公告)日：2017-03-30
申请号：PCT/US2016/044060
申请日：2016-07-26
申请人： QUALCOMM INCORPORATED
发明人： KHANDELWAL, Shambhoo , XIA, Yang , TANG, Xuefeng , LIANG, Jian , WANG, Tao , GRUBER, Andrew Evan , DEMERS, Eric
IPC分类号： G06T15/00
CPC分类号： G06T7/20 , G06T1/20 , G06T1/60 , G06T15/005 , G06T15/80 , G06T2200/04 , G06T2200/28
摘要： A graphics processing unit (GPU) may determine a workload of a fragment shader program that executes on the GPU. The GPU may compare the workload of the fragment shader program to a threshold. In response to determining that the workload of the fragment shader program is lower than a specified threshold, the fragment shader program may process one or more fragments without the GPU performing early depth testing of the one or more fragments before the processing by the fragment shader program. The GPU may perform, after processing by the fragment shader program, late depth testing of the one or more fragments to result in one or more non-occluded fragments. The GPU may write pixel values for the one or more non-occluded fragments into a frame buffer.
摘要翻译：图形处理单元（GPU）可以确定在GPU上执行的片段着色器程序的工作负载。 GPU可以将片段着色器程序的工作负载与阈值进行比较。响应于确定片段着色器程序的工作负荷低于指定的阈值，片段着色器程序可以处理一个或多个片段，而GPU未在片段着色器程序处理之前执行对一个或多个片段的早期深度测试。在片段着色器程序处理之后，GPU可以执行一个或多个片段的深度深度测试以产生一个或多个未遮挡的片段。 GPU可以将一个或多个非遮挡片段的像素值写入帧缓冲器。

7. 发明申请

WO2015061044A2 SELECTIVELY MERGING PARTIALLY-COVERED TILES TO PERFORM HIERARCHICAL Z-CULLING 审中-公开
标题翻译：选择性地将部分覆盖的瓷砖合并为分层Z-CULLING
公开(公告)号：WO2015061044A2
公开(公告)日：2015-04-30
申请号：PCT/US2014/059717
申请日：2014-10-08
申请人： QUALCOMM INCORPORATED
发明人： WANG, Tao , GRUBER, Andrew Evan , KHANDELWAL, Shambhoo
IPC分类号： G06T15/00
CPC分类号： G06T15/405 , G06T1/60 , G06T15/005
摘要： This disclosure describes techniques for performing hierarchical z-culling in a graphics processing system. In some examples, the techniques may involve selectively merging partially-covered source tiles for a tile location into a fully-covered merged source tile based on whether conservative farthest z-values for the partially-covered source tiles are nearer than a culling z-value for the tile location, and using a conservative farthest z-value associated with the fully-covered merged source tile to update the culling z-value for the tile location. In further examples, the techniques may use a cache unit that is not associated with an underlying memory to store conservative farthest z-values and coverage masks for merged source tiles. The capacity of the cache unit may be smaller than the size of cache needed to store merged source tile data for all of the tile locations in a render target.
摘要翻译：本公开描述了用于在图形处理系统中执行分级z剔除的技术。在一些示例中，这些技术可以涉及基于部分覆盖的源瓦片的保守最远z值是否比剔除z值更接近地将瓦片位置的部分覆盖的源瓦片合并到完全覆盖的合并源瓦片中对于图块位置，并且使用与完全覆盖的合并源图块相关联的保守最远z值来更新图块位置的剔除z值。在进一步的示例中，这些技术可以使用不与底层存储器相关联的高速缓存单元来存储用于合并的源瓦片的保守最远的z值和覆盖遮罩。高速缓存单元的容量可以小于为渲染目标中的所有瓦片位置存储合并的源瓦片数据所需的高速缓存的大小。

8. 发明申请

WO2014099249A1 MULTI-MODE MEMORY ACCESS TECHNIQUES FOR PERFORMING GRAPHICS PROCESSING UNIT-BASED MEMORY TRANSFER OPERATIONS 审中-公开
标题翻译：用于执行图形处理的多模式存储器访问技术基于单元的存储器传输操作
公开(公告)号：WO2014099249A1
公开(公告)日：2014-06-26
申请号：PCT/US2013/071283
申请日：2013-11-21
申请人： QUALCOMM INCORPORATED
发明人： GRUBER, Andrew Evan , WANG, Tao , KHANDELWAL, Shambhoo
IPC分类号： G11C7/10 , G09G5/393 , G09G3/36 , G09G5/395 , G09F3/14 , G06F12/02 , G06F12/06 , G06F13/16
CPC分类号： G09G5/363 , G06F12/0607 , G06F12/0875 , G06F2212/1021 , G06F2212/455 , G06F2212/601 , G09G5/393 , G09G5/395
摘要： This disclosure describes techniques for performing memory transfer operations with a graphics processing unit (GPU) based on a selectable memory transfer mode, and techniques for selecting a memory transfer mode for performing all or part of a memory transfer operation with a GPU. In some examples, the techniques of this disclosure may include selecting a memory transfer mode for performing at least part of a memory transfer operation, and performing, with a GPU, the memory transfer operation based on the selected memory transfer mode. The memory transfer mode may be selected from a set of at least two different memory transfer modes that includes an interleave memory transfer mode and a sequential memory transfer mode. The techniques of this disclosure may be used to improve the performance of GPU-assisted memory transfer operations.
摘要翻译：本公开描述了基于可选存储器传输模式的用于执行图形处理单元（GPU）的存储器传送操作的技术，以及用于选择用于执行与GPU的存储器传送操作的全部或部分的存储器传送模式的技术。在一些示例中，本公开的技术可以包括选择用于执行存储器传送操作的至少一部分的存储器传送模式，以及基于所选择的存储器传输模式，使用GPU执行存储器传送操作。可以从包括交织存储器传送模式和顺序存储器传输模式的至少两个不同的存储器传输模式的集合中选择存储器传送模式。本公开的技术可以用于改善GPU辅助的存储器传送操作的性能。

9. 发明授权

EP3350766B1 STORING BANDWIDTH-COMPRESSED GRAPHICS DATA 有权
公开(公告)号：EP3350766B1
公开(公告)日：2019-11-06
申请号：EP16753760.4
申请日：2016-08-01
申请人： Qualcomm Incorporated
发明人： GRUBER, Andrew Evan , HILL, Rexford Alan , KHANDELWAL, Shambhoo
IPC分类号： G06T1/20 , G06T1/60 , G06F12/02 , G06T11/40

10. 发明授权

EP3061070B1 SELECTIVELY MERGING PARTIALLY-COVERED TILES TO PERFORM HIERARCHICAL Z-CULLING 有权
标题翻译：选择性地将部分覆盖的瓷砖合并为分层Z-CULLING
公开(公告)号：EP3061070B1
公开(公告)日：2017-12-20
申请号：EP14789461.2
申请日：2014-10-08
申请人： Qualcomm Incorporated
发明人： WANG, Tao , GRUBER, Andrew Evan , KHANDELWAL, Shambhoo
IPC分类号： G06T15/00 , G06T15/40
CPC分类号： G06T15/405 , G06T1/60 , G06T15/005

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