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1. 发明申请

WO2019212629A1 MULTIPHASE CLOCK DATA RECOVERY WITH ADAPTIVE TRACKING FOR A MULTI-WIRE, MULTI-PHASE INTERFACE 审中-公开
公开(公告)号：WO2019212629A1
公开(公告)日：2019-11-07
申请号：PCT/US2019/020185
申请日：2019-03-01
申请人： QUALCOMM INCORPORATED
发明人： LEE, Chulkyu , CHOU, Shih-Wei , DUAN, Ying
IPC分类号： H04L7/033 , H04L25/49
摘要： Data communication apparatus and methods for a multi-wire interface are disclosed. A half rate clock and data recovery (CDR) circuit derives a clock signal including pulses corresponding to symbols transmitted on a 3-wire interface, where the symbols are transmitted at a particular frequency with each of the symbols occurring over a unit interval (UI) time period. The first clock signal is input to a flip-flop logic included in a delay loop, and serves to trigger the first flip-flop logic. A second clock signal is generated using a programmable generator in the delay loop and has a frequency of a half UI and is fed back to a data input of the flip-flop. The output of the flip-flop is used as a recovered clock signal for the CDR at a half rate frequency. This design provides ease of timing control, a delay line without extra nonlinear-effects, and less hardware overhead.

2. 发明申请

WO2015199883A1 SKEW CONTROL FOR THREE-PHASE COMMUNICATION 审中-公开
标题翻译：用于三相通信的SKEW控制
公开(公告)号：WO2015199883A1
公开(公告)日：2015-12-30
申请号：PCT/US2015/032898
申请日：2015-05-28
申请人： QUALCOMM INCORPORATED
发明人： DUAN, Ying , DANG, Harry, Huy , LEE, Chulkyu
IPC分类号： H04B3/30 , H04L25/02 , H04L25/03
CPC分类号： H04B1/0475 , H04B3/30 , H04B15/02 , H04L25/028 , H04L25/03878
摘要： Aspects disclosed in the detailed description include skew control for three-phase communication. A three-phase communication involves three signal branches. A signal skew may occur when one signal branch is being coupled to a common mode voltage while another signal branch is being decoupled from the common mode voltage. In this regard, in one aspect, an impedance mismatch is introduced in the signal branch being coupled to the common mode voltage to help shift a rightmost crossing of the signal skew leftward. In another aspect, a current source or a current sink is coupled to the signal branch being decoupled from the common mode voltage to help shift a leftmost crossing of the signal skew rightward. By shifting the rightmost crossing leftward and the leftmost crossing rightward, it is possible to reduce the signal skew, thus leading to reduced jitter and improved data integrity in the three-phase communication.
摘要翻译：在详细描述中公开的方面包括用于三相通信的偏斜控制。三相通信涉及三个信号分支。当一个信号分支耦合到共模电压而另一个信号分支与共模电压分离时，可能发生信号偏移。在这方面，在一个方面，在耦合到共模电压的信号支路中引入阻抗失配，以帮助向左偏移信号偏移的最右边的交叉。在另一方面，电流源或电流吸收器耦合到信号分支与共模电压分离，以帮助向右偏移信号偏移的最左边的交叉。通过向右移动最左边的交叉点，向右移动最左边的交叉点，可以减少信号偏移，从而导致三相通信中的抖动减小和数据完整性的改善。

3. 发明申请

WO2021086625A1 C-PHY HALF-RATE WIRE STATE ENCODER AND DECODER 审中-公开
公开(公告)号：WO2021086625A1
公开(公告)日：2021-05-06
申请号：PCT/US2020/055804
申请日：2020-10-15
申请人： QUALCOMM INCORPORATED
发明人： LEE, Chulkyu , DUAN, Ying , CHOU, Shih-Wei
IPC分类号： H04L25/02
摘要： Methods, apparatus, and systems provide improved throughput on a communication link. An apparatus has a plurality of line drivers, a first wire state encoder configured to receive a first symbol in a sequence of symbols when a 3-wire link is in a first signaling state, and to define a second signaling state for the 3-wire link based on the first symbol and the first signaling state, a second wire state encoder configured to receive a second symbol in the sequence of symbols, and to define a third signaling state for the 3-wire link based on the second symbol and the second signaling state. The first symbol immediately precedes the second symbol in the sequence of symbols. The 3-wire link transitions from the first to the second signaling state, and from the second to the third signaling state in consecutive transmission intervals.

4. 发明申请

WO2019209409A1 SIGNAL MONITORING AND MEASUREMENT FOR A MULTI-WIRE, MULTI-PHASE INTERFACE 审中-公开
公开(公告)号：WO2019209409A1
公开(公告)日：2019-10-31
申请号：PCT/US2019/020187
申请日：2019-03-01
申请人： QUALCOMM INCORPORATED
发明人： AHMED, Yasser , DUAN, Ying
IPC分类号： H04L25/02 , G06F13/42 , H04L1/20 , H04L7/00 , H04L25/08 , H04L25/49
摘要： Methods, apparatus, and systems for monitoring and measuring signal characteristics for signals received over a multi-wire, multi-phase interface are disclosed. Signals present on each line of a 3-line communication interface are sampled using auxiliary samplers having a programmable time delay to delay the sampled signal by a set time, as well as a programmable voltage offset. The auxiliary sampler outputs are compared with direct line samples of signals on each of the three lines to generate error signals. From this comparison, an array of error signal data occurring over a particular sampling period may be generated. In turn, waveform characteristics can be determined from the error signal data, such as an eye-pattern. Furthermore, skew measurement may further be effectuated using the auxiliary samplers but determining the time difference of when the error signals of the different wires cross a predetermined threshold.

5. 发明申请

WO2017039984A1 MULTIPHASE CLOCK DATA RECOVERY CIRCUIT CALIBRATION 审中-公开
标题翻译：多相时钟数据恢复电路校准
公开(公告)号：WO2017039984A1
公开(公告)日：2017-03-09
申请号：PCT/US2016/046208
申请日：2016-08-09
申请人： QUALCOMM INCORPORATED
发明人： DUAN, Ying , LEE, Chulkyu , DANG, Harry , KWON, Ohjoon
IPC分类号： H04L7/033 , H03K5/13 , H04L25/02
CPC分类号： H04L7/0008 , H03K5/135 , H04L5/0048 , H04L7/033 , H04L7/04 , H04L7/08 , H04L25/0272
摘要： Methods, apparatus, and systems for clock calibration are disclosed. A method for clock data recovery circuit calibration includes configuring a first clock recovery circuit to provide a clock signal that has a first frequency and that includes a single pulse for each symbol transmitted on a 3-wire, 3-phase interface, and calibrating the first clock recovery circuit by incrementally increasing a delay period provided by a delay element of the first clock recovery circuit until the clock signal provided by the first clock recovery circuit has a frequency that is less than the first frequency and, when the first clock recovery circuit has a frequency that is less than the first frequency, incrementally decreasing the delay period provided by the delay element of the first clock recovery circuit until the clock signal provided by the first clock recovery circuit has a frequency that matches the first frequency.
摘要翻译：公开了用于时钟校准的方法，装置和系统。一种用于时钟数据恢复电路校准的方法包括配置第一时钟恢复电路以提供具有第一频率的时钟信号，并且对于在3线3相接口上传输的每个符号包括单个脉冲，并且校准第一频率时钟恢复电路，通过逐渐增加由第一时钟恢复电路的延迟元件提供的延迟时间，直到由第一时钟恢复电路提供的时钟信号具有小于第一频率的频率，并且当第一时钟恢复电路具有小于第一频率的频率，逐渐减小由第一时钟恢复电路的延迟元件提供的延迟时间，直到由第一时钟恢复电路提供的时钟信号具有与第一频率匹配的频率。

6. 发明申请

WO2022164629A1 C-PHY DATA-TRIGGERED EDGE GENERATION WITH INTRINSIC HALF-RATE OPERATION 审中-公开
公开(公告)号：WO2022164629A1
公开(公告)日：2022-08-04
申请号：PCT/US2022/012021
申请日：2022-01-11
申请人： QUALCOMM INCORPORATED
发明人： YING, Da , CHOU, Shih-Wei , DUAN, Ying , DIXIT, Abhay
IPC分类号： G06F13/42 , H04L7/033 , H04L25/49 , H04L25/14
摘要： Methods, apparatus, and systems for clock and data recovery in a C-PHY interface are disclosed. A receiving device has a plurality of differential receivers and a recovery circuit. The differential receivers are configured to generate difference signals. Each difference signal is representative of voltage difference between one pair of wires in a three-wire serial bus. The recovery circuit is configured to identify a first difference signal that has the greatest voltage magnitude among the plurality of difference signals in a first unit interval and determine signaling state of the three-wire serial bus for the first unit interval based on identity of the pair of wires corresponding to the first difference signal and polarity of the first difference signal in the first unit interval, and to generate a first edge in a clock signal responsive to a transition in the first difference signal during the first unit interval.

7. 发明申请

WO2021080686A1 SMALL LOOP DELAY CLOCK AND DATA RECOVERY BLOCK FOR HIGH-SPEED NEXT GENERATION C-PHY 审中-公开
公开(公告)号：WO2021080686A1
公开(公告)日：2021-04-29
申请号：PCT/US2020/047919
申请日：2020-08-26
申请人： QUALCOMM INCORPORATED
发明人： DUAN, Ying , WU, Jing , CHOU, Shih-Wei
IPC分类号： H04L7/033 , H04L25/14 , G06F13/40 , H04L25/49
摘要： Methods, apparatus, and systems for communication over a multi-wire, multi-phase interface are disclosed. A clock recovery method includes generating a combination signal that includes transition pulses, each transition pulse being generated responsive to a transition in a difference signal representative of a difference in signaling state of a pair of wires in a three-wire bus. The combination signal is provided to a logic circuit that is configured to provide a clock signal as its output, where pulses in the combination signal cause the clock signal to be driven to a first state. The logic circuit receives a reset signal that is derived from the clock signal by delaying transitions to the first state while passing transitions from the first state without added delay. The clock signal is driven from the first state after passing a transition of the clock signal to the first state.

8. 发明申请

WO2021050838A1 ANALOG FRONT-END RECEIVERS 审中-公开
公开(公告)号：WO2021050838A1
公开(公告)日：2021-03-18
申请号：PCT/US2020/050349
申请日：2020-09-11
申请人： QUALCOMM INCORPORATED
发明人： DUAN, Ying , CHOU, Shih-Wei , SHAIK, Mansoor Basha , DANG, Harry , DIXIT, Abhay
IPC分类号： G06F13/40
摘要： In certain aspects, a device comprises one or more IO inputs; a first receiver coupled to a first supply voltage and the one or more IO inputs, wherein the first receiver comprises thick oxide transistors; and a high-speed circuit comprising: an isolation block coupled to the one or more IO inputs, wherein the isolation block comprises thick oxide transistors; and a second receiver coupled to the isolation block and a second supply voltage, wherein the second receiver comprises thin oxide transistors.

9. 发明申请

WO2019212630A1 CALIBRATION PATTERN AND DUTY-CYCLE DISTORTION CORRECTION FOR CLOCK DATA RECOVERY IN A MULTI-WIRE, MULTI-PHASE INTERFACE 审中-公开
公开(公告)号：WO2019212630A1
公开(公告)日：2019-11-07
申请号：PCT/US2019/020192
申请日：2019-03-01
申请人： QUALCOMM INCORPORATED
发明人： DUAN, Ying , DIXIT, Abhay , CHOU, Shih-Wei , LEE, Chulkyu
IPC分类号： H04L7/033 , H04L25/49 , G06F13/42
摘要： Methods, apparatus, and systems for calibration and correction of data communications over a multi-wire, multi-phase interface are disclosed. In particular, calibration is provided for data communication devices coupled to a 3-line interface. The calibration includes generating and transmitting a calibration pattern on the 3-line interface, where the generation of the pattern includes toggling two of three interface lines from one voltage level to another voltage level over a predetermined time interval. Furthermore, the generation of the pattern includes maintaining a remaining third interface line at a common mode voltage level over the predetermined time interval, wherein only a single transition occurs for the predetermined time interval. Calibration data may then be derived in a receiver device using the transmitted calibration pattern.

10. 发明申请

WO2023048956A1 C-PHY RECEIVER WITH SELF-REGULATED COMMON MODE SERVO LOOP 审中-公开
公开(公告)号：WO2023048956A1
公开(公告)日：2023-03-30
申请号：PCT/US2022/042932
申请日：2022-09-08
申请人： QUALCOMM INCORPORATED
发明人： CHOU, Shih-Wei , RASMUS, Todd Morgan , DUAN, Ying , DIXIT, Abhay
IPC分类号： G06F13/40
摘要： A receiving apparatus includes a terminating network for a three-wire serial bus and a feedback circuit. Each wire of the three-wire serial bus may be coupled through a resistance to a common node of the terminating network. The feedback circuit has a first amplifier circuit having an input coupled to the common node, a comparator that receives an output of the first amplifier circuit as a first input and a reference voltage as a second input, and a second amplifier circuit responsive to an output of the comparator and configured to inject a current through the common node.

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