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1. 发明申请

WO2008028103A3 METHODS AND APPARATUS FOR EMULATING THE BRANCH PREDICTION BEHAVIOR OF AN EXPLICIT SUBROUTINE CALL 审中-公开
标题翻译：用于模拟显式子程序呼叫的分支预测行为的方法和设备
公开(公告)号：WO2008028103A3
公开(公告)日：2008-05-29
申请号：PCT/US2007077340
申请日：2007-08-31
申请人： QUALCOMM INC , DIEFFENDERFER JAMES NORRIS , STEMPEL BRIAN , SARTORIUS THOMAS ANDREW , SMITH WAYNE
发明人： DIEFFENDERFER JAMES NORRIS , STEMPEL BRIAN , SARTORIUS THOMAS ANDREW , SMITH WAYNE
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38
CPC分类号： G06F9/3844 , G06F9/3005 , G06F9/30058 , G06F9/30101 , G06F9/322 , G06F9/3806
摘要： An apparatus for emulating the branch prediction behavior of an explicit subroutine call is disclosed. The apparatus includes a first input which is configured to receive an instruction address and a second input. The second input is configured to receive predecode information which describes the instruction address as being related to an implicit subroutine call to a subroutine. In response to the predecode information, the apparatus also includes an adder configured to add a constant to the instruction address defining a return address, causing the return address to be stored to an explicit subroutine resource, thus, facilitating subsequent branch prediction of a return call instruction.
摘要翻译：公开了一种用于模拟显式子例程调用的分支预测行为的装置。该装置包括被配置为接收指令地址和第二输入的第一输入。第二输入被配置为接收将指令地址描述为与对子例程的隐式子例程调用相关的预解码信息。响应于预解码信息，该装置还包括加法器，该加法器被配置为向定义返回地址的指令地址添加常数，使得返回地址被存储到显式子例程资源，从而便于后续分支预测返回呼叫指令。

2. 发明申请

WO2007143508A3 SLIDING-WINDOW, BLOCK-BASED BRANCH TARGET ADDRESS CACHE 审中-公开
标题翻译：滑动窗口，基于块的分支目标地址高速缓存
公开(公告)号：WO2007143508A3
公开(公告)日：2008-01-31
申请号：PCT/US2007070111
申请日：2007-05-31
申请人： QUALCOMM INC , SMITH RODNEY WAYNE , DIEFFENDERFER JAMES NORRIS , STEMPEL BRIAN MICHAEL , SARTORIUS THOMAS ANDREW
发明人： SMITH RODNEY WAYNE , DIEFFENDERFER JAMES NORRIS , STEMPEL BRIAN MICHAEL , SARTORIUS THOMAS ANDREW
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3836 , G06F9/3844
摘要： A sliding-window, block-based branch target address cache (BTAC) comprises a plurality of entries, each entry associated with a block of instructions containing at least one branch instruction having been evaluated taken, and having a tag associated with the address of the first instruction in the block. The blocks each correspond to a group of instructions fetched from memory, such as an I-cache. Where a branch instruction is included in two or more fetch groups, it is also included in two or more instruction blocks associated with BTAC entries. The sliding-window, block-based BTAC allows for storing the branch target address (BTA) of two or more taken branch instructions that fall in the same instruction block, without providing for multiple BTA storage space in each BTAC entry, by storing BTAC entries associated with different instruction blocks, each containing at least one of the taken branch instructions.
摘要翻译：滑动窗口，基于块的分支目标地址高速缓存（BTAC）包括多个条目，每个条目与包含已被评估的至少一个分支指令的指令块相关联，并且具有与该地址相关联的标签第一个指令在块中。这些块各自对应于从存储器获取的一组指令，例如I缓存。在两个或更多个取出组中包含分支指令的情况下，还包括在与BTAC条目相关联的两个或多个指令块中。滑动窗口，基于块的BTAC允许存储落在相同指令块中的两个或更多个采取的分支指令的分支目标地址（BTA），而不需要在每个BTAC条目中提供多个BTA存储空间，通过存储BTAC条目与不同的指令块相关联，每个指令块包含至少一个采取的分支指令。

3. 发明申请

WO2006130466A3 A METHOD AND APPARATUS FOR PREDICTING BRANCH INSTRUCTIONS 审中-公开
标题翻译：一种用于预测分支指令的方法和装置
公开(公告)号：WO2006130466A3
公开(公告)日：2007-11-22
申请号：PCT/US2006020440
申请日：2006-05-24
申请人： QUALCOMM INC , SARTORIUS THOMAS ANDREW , STEMPEL BRIAN MICHAEL , BRIDGES JEFFREY TODD , DIEFFENDERFER JAMES NORRIS , SMITH RODNEY WAYNE
发明人： SARTORIUS THOMAS ANDREW , STEMPEL BRIAN MICHAEL , BRIDGES JEFFREY TODD , DIEFFENDERFER JAMES NORRIS , SMITH RODNEY WAYNE
IPC分类号： G06F9/42
CPC分类号： G06F9/3844
摘要： A microprocessor (10) includes two branch history tables, and is configured to use a first one (48) of the branch history tables for predicting branch instructions that are hits in a branch target cache (46), and to use a second one (50) of the branch history tables for predicting branch instructions that are misses in the branch target cache (46). As such, the first branch history table (48) is configured to have an access speed matched to that of the branch target cache (46), so that its prediction information is timely available relative to branch target cache hit detection, which may happen early in the microprocessor's instruction pipeline. The second branch history table (50) thus need only be as fast as is required for providing timely prediction information in association with recognizing branch target cache misses as branch instructions, such as at the instruction decode stage(s) of the instruction pipeline.
摘要翻译：微处理器（10）包括两个分支历史表，并且被配置为使用分支历史表中的第一个（48）来预测分支目标高速缓存（46）中的命中的分支指令，并且使用第二个分支指令 50）用于预测分支目标高速缓存（46）中未命中的分支指令的分支历史表。因此，第一分支历史表（48）被配置为具有与分支目标高速缓存（46）的访问速度相匹配的访问速度，使得其预测信息相对于可能发生的早期的分支目标高速缓存命中检测而及时可用在微处理器的指令管道中。因此，第二分支历史表（50）仅需要与将识别分支目标高速缓存未命中作为分支指令（例如在指令流水线的指令解码阶段）相关联地提供及时的预测信息所需的速度。

4. 发明申请

WO2006096568A3 POWER SAVING METHODS AND APPARATUS FOR VARIABLE LENGTH INSTRUCTIONS 审中-公开
标题翻译：节能方法和设备可变长度指示
公开(公告)号：WO2006096568A3
公开(公告)日：2007-01-11
申请号：PCT/US2006007758
申请日：2006-03-03
申请人： QUALCOMM INC , STEMPEL BRIAN MICHAEL , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , SMITH RODNEY WAYNE , SARTORIUS THOMAS ANDREW
发明人： STEMPEL BRIAN MICHAEL , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , SMITH RODNEY WAYNE , SARTORIUS THOMAS ANDREW
IPC分类号： G06F9/30
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816 , G06F12/0875 , Y02D10/13
摘要： A processor capable of fetching and executing variable length instructions is described having instructions of at least two lengths. The processor operates in multiple modes. One of the modes restricts instructions that can be fetched and executed to the longer length instructions. An instruction cache is used for storing variable length instructions and their associated predecode bit fields in an instruction cache line and storing the instruction address and processor operating mode state information at the time of the fetch in a tag line. The processor operating mode state information indicates the program specified mode of operation of the processor. The processor fetches instructions from the instruction cache for execution. As a result of an instruction fetch operation, the instruction cache may selectively enable the writing of predecode bit fields in the instruction cache and may selectively enable the reading of predecode bit fields stored in the instruction cache based on the processor state at the time of the fetch.
摘要翻译：描述具有至少两个长度的指令的能够获取和执行可变长度指令的处理器。处理器以多种模式运行。其中一种模式限制了可以获取并执行到较长长度指令的指令。指令高速缓存用于在指令高速缓存行中存储可变长度指令及其相关联的预解码位字段，并且在标记行中存储指令地址和处理器操作模式状态信息。处理器操作模式状态信息指示处理器的程序指定的操作模式。处理器从指令缓存器中获取指令以执行。作为指令提取操作的结果，指令高速缓存可以选择性地启用指令高速缓存中的预解码位字段的写入，并且可以基于处理器状态来选择性地启用存储在指令高速缓存中的预解码位字段的读取取。

5. 发明申请

WO2006057907A3 PRE-DECODE ERROR HANDLING VIA BRANCH CORRECTION 审中-公开
标题翻译：通过分支校正进行预解码错误处理
公开(公告)号：WO2006057907A3
公开(公告)日：2006-12-14
申请号：PCT/US2005041850
申请日：2005-11-18
申请人： QUALCOMM INC , SMITH RODNEY WAYNE , STEMPEL BRIAN MICHAEL , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , SARTORIUS THOMAS ANDREW
发明人： SMITH RODNEY WAYNE , STEMPEL BRIAN MICHAEL , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , SARTORIUS THOMAS ANDREW
IPC分类号： G06F9/318
CPC分类号： G06F9/3861 , G06F9/30152 , G06F9/3017 , G06F9/382
摘要： In a pipelined processor where instructions are pre-decoded prior to being stored in a cache, an incorrectly pre-decoded instruction is detected during execution in the pipeline. The corresponding instruction is invalidated in the cache, and the instruction is forced to evaluate as a branch instruction. In particular, the branch instruction is evaluated as "mispredicted not taken" with a branch target address of the incorrectly pre-decoded instruction's address. This, with the invalidated cache line, causes the incorrectly pre-decoded instruction to be re-fetched from memory with a precise address. The re-fetched instruction is then correctly pre-decoded, written to the cache, and executed.
摘要翻译：在其中指令在被存储在高速缓冲存储器中之前进行预解码的流水线处理器中，在流水线执行期间检测到不正确的预解码指令。相应的指令在高速缓存中无效，并且强制将该指令作为分支指令进行求值。特别地，分支指令被评估为未被错误地预解码的指令的地址的分支目标地址“未被预测”。这使得无效的高速缓存行导致错误地预解码的指令从具有精确地址的存储器重新获取。重新读取的指令然后被正确地预解码，写入高速缓存并执行。

6. 发明申请

WO2006096569A3 FORWARD LOOKING BRANCH TARGET ADDRESS CACHING 审中-公开
标题翻译：前瞻性分支目标地址缓存
公开(公告)号：WO2006096569A3
公开(公告)日：2006-12-21
申请号：PCT/US2006007759
申请日：2006-03-03
申请人： QUALCOMM INC , SMITH RODNEY WAYNE , STEMPEL BRIAN MICHAEL , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , SARTORIUS THOMAS ANDREW
发明人： SMITH RODNEY WAYNE , STEMPEL BRIAN MICHAEL , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , SARTORIUS THOMAS ANDREW
IPC分类号： G06F9/38 , G06F9/32 , G06F12/08
CPC分类号： G06F12/1063 , G06F9/321 , G06F9/3806 , G06F9/3844 , G06F12/0862 , G06F12/0875 , G06F2212/6028
摘要： A pipelined processor comprises an instruction cache (iCache), a branch target address cache (BTAC), and processing stages, including a stage to fetch from the iCache and the BTAC. To compensate for the number of cycles needed to fetch a branch target address from the BTAC, the fetch from the BTAC leads the fetch of a branch instruction from the iCache by an amount related to the cycles needed to fetch from the BTAC. Disclosed examples either decrement a write address of the BTAC or increment a fetch address of the BTAC, by an amount essentially corresponding to one less than the cycles needed for a BTAC fetch.
摘要翻译：流水线处理器包括指令缓存（iCache），分支目标地址缓存（BTAC）和处理阶段，包括从iCache和BTAC中提取的阶段。为了补偿从BTAC获取分支目标地址所需的周期数，从BTAC获取从iCache获取的分支指令的数量与从BTAC获取所需的周期相关。所公开的示例或者递减BTAC的写地址或者增加BTAC的提取地址的量基本上对应于比BTAC提取所需的周期小的量。

7. 发明申请

WO2006060198A9 TRANSLATION LOOKASIDE BUFFER (TLB) ACCESS SUPRESSION FOR INTRA-PAGE PROGRAM COUNTER RELATIVE OR ABSOLUTE ADDRESS BRANCH INSTRUCTIONS 审中-公开
标题翻译：翻译LOOKASIDE BUFFER（TLB）访问权限用于内部程序计数器相对或绝对地址分支指令
公开(公告)号：WO2006060198A9
公开(公告)日：2006-12-14
申请号：PCT/US2005041998
申请日：2005-11-17
申请人： QUALCOMM INC , DIEFFENDERFER JAMES NORRIS , SARTORIUS THOMAS ANDREW , SMITH RODNEY WAYNE , STEMPEL BRIAN MICHAEL
发明人： DIEFFENDERFER JAMES NORRIS , SARTORIUS THOMAS ANDREW , SMITH RODNEY WAYNE , STEMPEL BRIAN MICHAEL
IPC分类号： G06F9/32 , G06F1/32 , G06F12/10
CPC分类号： G06F12/1027 , G06F9/30054 , G06F9/32 , G06F9/3804 , G06F9/382 , G06F2212/1028 , G06F2212/655 , Y02D10/13
摘要： In a pipelined processor, a pre-decoder in advance of an instruction cache calculates the branch target address (BTA) of PC-relative and absolute address branch instructions. The pre-decoder compares the BTA with the branch instruction address (BIA) to determine whether the target and instruction are in the same memory page. A branch target same page (BTSP) bit indicating this is written to the cache and associated with the instruction. When the branch is executed and evaluated as taken, a TLB access to check permission attributes for the BTA is suppressed if the BTA is in the same page as the BIA, as indicated by the BTSP bit. This reduces power consumption as the TLB access is suppressed and the BTA/BIA comparison is only performed once, when the branch instruction is first fetched. Additionally, the pre-decoder removes the BTA/BIA comparison from the BTA generation and selection critical path.
摘要翻译：在流水线处理器中，在指令高速缓存之前的预解码器计算PC相对分支目标地址（BTA）和绝对地址分支指令。预解码器将BTA与分支指令地址（BIA）进行比较，以确定目标和指令是否在相同的存储器页面中。指示这一点的分支目标相同页（BTSP）位被写入高速缓存并与指令相关联。当分支被执行并被评估时，如果BTA与BIA位于同一页面中，那么如BTSP位所指示的那样，对BTA的TLB访问检查权限属性被抑制。当首先取出分支指令时，这样可以降低TLB访问的功耗，并且仅执行一次BTA / BIA比较。另外，预解码器从BTA生成和选择关键路径去除BTA / BIA比较。

8. 发明申请

WO2006124410A3 LATENCY INSENSITIVE FIFO SIGNALING PROTOCOL 审中-公开
标题翻译： LATENCY INSENSITIVE FIFO信号协议
公开(公告)号：WO2006124410A3
公开(公告)日：2007-09-20
申请号：PCT/US2006017899
申请日：2006-05-08
申请人： QUALCOMM INC , DOCKSER KENNETH ALAN , AUGSBURG VICTOR ROBERTS , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , CLANCY ROBERT DOUGLAS , SARTORIUS THOMAS ANDREW
发明人： DOCKSER KENNETH ALAN , AUGSBURG VICTOR ROBERTS , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , CLANCY ROBERT DOUGLAS , SARTORIUS THOMAS ANDREW
IPC分类号： G06F13/38
CPC分类号： G06F13/4059 , G06F5/06 , G06F2205/126
摘要： Data from a source domain (311 ) operating at a first data rate is transferred to a FIFO (319) in another domain (313) operating at a different data rate. The FIFO (319) buffers data before transfer to a sink for further processing or storage. A source side counter (325) tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter (325) decrements in response to a data ready signal from the source domain (311)1 without delay. The counter (325) increments in response to signaling from the sink domain (313) of a read of data off the FIFO (319). Hence, incrementing is subject to the signaling latency between domains. The source (315) may send one more beat of data when the counter (325) indicates the FIFO (319) is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one o more FIFO positions.
摘要翻译：来自以第一数据速率运行的源域（311）的数据被传送到以不同数据速率工作的另一域（313）中的FIFO（319）。 FIFO（319）在传输到宿之前缓冲数据以进一步处理或存储。源侧计数器（325）跟踪FIFO中可用的空间。在所公开的示例中，初始计数器值对应于FIFO深度。计数器（325）响应于来自源域（311）1的数据就绪信号而没有延迟地递减。计数器（325）响应于来自接收器域（313）的从FIFO（319）读取的数据的信令而递增。因此，增量受到域之间的信令等待时间的限制。当计数器（325）指示FIFO（319）已满时，源（315）可以再发送一个数据节拍。数据的最后一次节拍从源头连续发送到指示FIFO位置可用为止; 有效提供一个以上的FIFO位置。

9. 发明申请

WO2006135590A3 METHOD AND APPARATUS FOR MANAGING INSTRUCTION FLUSHING IN A MICROPROCESSOR'S INSTRUCTION PIPELINE 审中-公开
标题翻译：用于管理微处理器指令管道中的指导性冲洗的方法和装置
公开(公告)号：WO2006135590A3
公开(公告)日：2007-05-31
申请号：PCT/US2006021617
申请日：2006-06-02
申请人： QUALCOMM INC , MCILVAINE MICHAEL SCOTT , DIEFFENDERFER JAMES NORRIS , SARTORIUS THOMAS ANDREW
发明人： MCILVAINE MICHAEL SCOTT , DIEFFENDERFER JAMES NORRIS , SARTORIUS THOMAS ANDREW
IPC分类号： G06F9/44
CPC分类号： G06F9/3861 , G06F9/30072 , G06F9/3867 , G06F12/0855 , G06F12/0862 , G06F2212/6028
摘要： In one or more embodiments, a processor includes one or more circuits to flush instructions from an instruction pipeline on a selective basis responsive to detecting a branch misprediction, such that those instructions marked as being dependent on the branch instruction associated with the branch misprediction are flushed. Thus, the one or more circuits may be configured to mark instructions fetched into the processor's instruction pipeline(s) to indicate their branch prediction dependencies, directly or indirectly detect incorrect branch predictions, and directly or indirectly flush instructions in the instruction pipeline(s) that are marked as being dependent on an incorrect branch prediction.
摘要翻译：在一个或多个实施例中，处理器包括一个或多个电路，用于响应于检测到分支错误预测而选择性地从指令流水线中刷新指令，使得标记为依赖于与分支错误预测相关联的分支指令的那些指令被刷新。因此，一个或多个电路可以被配置为标记被提取到处理器的指令流水线中以指示其分支预测依赖性的指令，直接或间接地检测不正确的分支预测，以及直接或间接地刷新指令流水线中的指令，这被标记为依赖于不正确的分支预测。

10. 发明申请

WO2006089194A3 UNALIGNED MEMORY ACCESS PREDICTION 审中-公开
公开(公告)号：WO2006089194A3
公开(公告)日：2007-03-29
申请号：PCT/US2006005782
申请日：2006-02-16
申请人： QUALCOMM INC , BRIDGES JEFFREY TODD , AUGSBURG VICTOR ROBERTS , DIEFFENDERFER JAMES NORRIS , SARTORIUS THOMAS ANDREW
发明人： BRIDGES JEFFREY TODD , AUGSBURG VICTOR ROBERTS , DIEFFENDERFER JAMES NORRIS , SARTORIUS THOMAS ANDREW
IPC分类号： G06F9/312 , G06F9/318 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/30145 , G06F9/30189 , G06F9/3824 , G06F9/3832 , G06F9/3855
摘要： In an instruction execution pipeline, the misalignment of memory access instructions is predicted. Based on the prediction, an additional micro-operation is generated in the pipeline prior to the effective address generation of the memory access instruction. The additional micro-operation accesses the memory falling across a predetermined address boundary. Predicting the misalignment and generating a micro-operation early in the pipeline ensures that sufficient pipeline control resources are available to generate and track the additional micro-operation, avoiding a pipeline flush if the resources are not available at the time of effective address generation. The misalignment prediction may employ known conditional branch prediction techniques, such as a flag, a bimodal counter, a local predictor, a global predictor, and combined predictors. A misalignment predictor may be enabled or biased by a memory access instruction flag or misaligned instruction type.
摘要翻译：在指令执行流水线中，预测存储器访问指令的未对准。基于该预测，在存储器访问指令的有效地址生成之前在流水线中生成附加的微操作。附加的微操作访问落在预定地址边界上的存储器。预测未对准并在管道早期生成微操作确保足够的流水线控制资源可用于生成和跟踪额外的微操作，如果资源在有效地址生成时不可用，则避免管道冲洗。不对准预测可以使用已知的条件分支预测技术，例如标志，双模计数器，局部预测器，全局预测器和组合预测器。未对准预测器可能被存储器访问指令标志或未对准指令类型使能或偏置。

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