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1. 发明申请

WO2008022288A1 METHOD AND APPARATUS FOR EXECUTING PROCESSOR INSTRUCTIONS BASED ON A DYNAMICALLY ALTERABLE DELAY 审中-公开
标题翻译：基于动态可变延迟执行处理器指令的方法和装置
公开(公告)号：WO2008022288A1
公开(公告)日：2008-02-21
申请号：PCT/US2007/076151
申请日：2007-08-16
申请人： QUALCOMM Incorporated , MICHALAK, Gerald Paul , DOCKSER, Kenneth Alan
发明人： MICHALAK, Gerald Paul , DOCKSER, Kenneth Alan
IPC分类号： G06F9/38
CPC分类号： G06F9/30145 , G06F9/3806 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3869 , G06F9/3877
摘要： Instruction execution delay is alterable after the system design has been finalized, thus enabling the system to dynamically account for various conditions that impact instruction execution. In some embodiments, the dynamic delay is determined by an application to be executed by the processing system. In other embodiments, the dynamic delay is determined by analyzing the history of previously executed instructions. In yet other embodiments, the dynamic delay is determined by assessing the processing resources available to a given application. Regardless, the delay may be dynamically altered on a per-instruction, multiple instruction, or application basis. Processor instruction execution may be controlled by determining a first delay value for a first set of one or more instructions and a second delay value for a second set of one or more instructions. Execution of the sets of instructions is delayed based on the corresponding delay value.
摘要翻译：指令执行延迟在系统设计完成后可以改变，从而使系统能够动态地考虑影响指令执行的各种条件。在一些实施例中，动态延迟由处理系统要执行的应用程序确定。在其他实施例中，通过分析先前执行的指令的历史来确定动态延迟。在其他实施例中，通过评估给定应用可用的处理资源来确定动态延迟。无论如何，延迟可以在每个指令，多个指令或应用程序的基础上动态地改变。处理器指令执行可以通过确定一个或多个指令的第一组的第一延迟值和第二组一个或多个指令的第二延迟值来控制。基于相应的延迟值来延迟指令集的执行。

2. 发明申请

WO2006113420A3 SYSTEM AND METHOD WHEREIN CONDITIONAL INSTRUCTIONS UNCONDITIONALLY PROVIDE OUTPUT 审中-公开
标题翻译：条件指令的系统和方法无条件地提供输出
公开(公告)号：WO2006113420A3
公开(公告)日：2006-12-21
申请号：PCT/US2006014042
申请日：2006-04-14
申请人： QUALCOMM INC , SARTORIUS THOMAS ANDREW , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , DOCKSER KENNETH ALAN , MCILVAINE MICHAEL SCOTT , SMITH RODNEY WAYNE
发明人： SARTORIUS THOMAS ANDREW , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , DOCKSER KENNETH ALAN , MCILVAINE MICHAEL SCOTT , SMITH RODNEY WAYNE
IPC分类号： G06F9/38
CPC分类号： G06F9/30072 , G06F9/3826 , G06F9/3838 , G06F9/384
摘要： A conditional instruction architected to receive one or more operands as inputs, to output to a target the result of an operation performed on the operands if a condition is satisfied, and to not provide an output if the condition is not satisfied, is executed so that it unconditionally provides an output to the target. The conditional instruction obtains the prior value of the target (that is, the value produced by the most recent instruction preceding the conditional instruction that updated that target). The condition is evaluated. If the condition is satisfied, an operation is performed and the result of the operation output to the target. If the condition is not satisfied, the prior value is output to the target. Subsequent instructions may rely on the target as an operand source (whether written to a register or forwarded to the instruction), prior to the condition evaluation.
摘要翻译：一种条件指令，被设计为接收一个或多个操作数作为输入，如果满足条件，则向目标输出对操作数执行的操作的结果，并且如果条件不满足则不提供输出，以便它无条件地向目标提供输出。条件指令获取目标的先前值（即由更新该目标的条件指令之前的最新指令产生的值）。评估条件。如果满足条件，则执行操作，并将操作结果输出到目标。如果条件不满足，则将先前值输出到目标。后续指令可以在条件评估之前依赖目标作为操作数源（无论是写入寄存器还是转发到指令）。

3. 发明申请

WO2006113420A2 SYSTEM AND METHOD WHEREIN CONDITIONAL INSTRUCTIONS UNCONDITIONALLY PROVIDE OUTPUT 审中-公开
标题翻译：系统和方法在条件指令无条件地提供输出
公开(公告)号：WO2006113420A2
公开(公告)日：2006-10-26
申请号：PCT/US2006/014042
申请日：2006-04-14
申请人： QUALCOMM INCORPORATED , SARTORIUS, Thomas, Andrew , DIEFFENDERFER, James, Norris , BRIDGES, Jeffrey, Todd , DOCKSER, Kenneth, Alan , MCILVAINE, Michael, Scott , SMITH, Rodney, Wayne
发明人： SARTORIUS, Thomas, Andrew , DIEFFENDERFER, James, Norris , BRIDGES, Jeffrey, Todd , DOCKSER, Kenneth, Alan , MCILVAINE, Michael, Scott , SMITH, Rodney, Wayne
IPC分类号： G06F9/38
CPC分类号： G06F9/30072 , G06F9/3826 , G06F9/3838 , G06F9/384
摘要： A conditional instruction architected to receive one or more operands as inputs, to output to a target the result of an operation performed on the operands if a condition is satisfied, and to not provide an output if the condition is not satisfied, is executed so that it unconditionally provides an output to the target. The conditional instruction obtains the prior value of the target (that is, the value produced by the most recent instruction preceding the conditional instruction that updated that target). The condition is evaluated. If the condition is satisfied, an operation is performed and the result of the operation output to the target. If the condition is not satisfied, the prior value is output to the target. Subsequent instructions may rely on the target as an operand source (whether written to a register or forwarded to the instruction), prior to the condition evaluation.
摘要翻译：被构造为接收一个或多个操作数作为输入的条件指令，如果满足条件则向目标输出对操作数执行的操作的结果，并且如果条件满足则不提供输出不满意，被执行以便无条件地向目标提供输出。条件指令获取目标的先前值（即，由更新该目标的条件指令之前的最近指令产生的值）。条件被评估。如果条件满足，则执行操作并将操作的结果输出到目标。如果条件不满足，则将先前值输出到目标。在条件评估之前，后续指令可能依赖目标作为操作数源（无论写入寄存器还是转发给指令）。

4. 发明申请

WO2012106719A1 PROCESSOR WITH A COPROCESSOR HAVING EARLY ACCESS TO NOT-YET ISSUED INSTRUCTIONS 审中-公开
标题翻译：具有早期访问不能发出指令的联合处理器的处理程序
公开(公告)号：WO2012106719A1
公开(公告)日：2012-08-09
申请号：PCT/US2012/023998
申请日：2012-02-06
申请人： QUALCOMM INCORPORATED , DOCKSER, Kenneth Alan , TEKMEN, Yusuf Cagatay
发明人： DOCKSER, Kenneth Alan , TEKMEN, Yusuf Cagatay
IPC分类号： G06F9/38
CPC分类号： G06F9/3814 , G06F9/382 , G06F9/3836 , G06F9/3859 , G06F9/3877 , G06F9/3885
摘要： Apparatus and methods provide early access of instructions. A fetch queue is coupled to an instruction cache and configured to store a mix of processor instructions for a first processor and coprocessor instructions for a second processor. A coprocessor instruction selector is coupled to the fetch queue and configured to copy coprocessor instructions from the fetch queue. A queue is coupled to the coprocessor instruction selector and from which coprocessor instructions are accessed for execution before the coprocessor instruction is issued to the first processor. Execution of the copied coprocessor instruction is started in the coprocessor before the coprocessor instruction is issued to a processor. The execution of the copied coprocessor instruction is completed based on information received from the processor after the coprocessor instruction has been issued to the processor.
摘要翻译：装置和方法提供了指令的早期访问。获取队列被耦合到指令高速缓存并且被配置为存储用于第一处理器的处理器指令和用于第二处理器的协处理器指令的混合。协处理器指令选择器被耦合到获取队列并被配置为从提取队列中复制协处理器指令。在协处理器指令被发送到第一处理器之前，队列被耦合到协处理器指令选择器并且从哪个协处理器指令被访问以执行。在将协处理器指令发送到处理器之前，在协处理器中启动复制的协处理器指令的执行。复制的协处理器指令的执行是在协处理器指令发出到处理器之后基于从处理器接收到的信息完成的。

5. 发明申请

WO2012106716A1 PROCESSOR WITH A HYBRID INSTRUCTION QUEUE WITH INSTRUCTION ELABORATION BETWEEN SECTIONS 审中-公开
标题翻译：具有混合指令队列的处理程序与指令之间的指导性绘制
公开(公告)号：WO2012106716A1
公开(公告)日：2012-08-09
申请号：PCT/US2012/023994
申请日：2012-02-06
申请人： QUALCOMM INCORPORATED , DOCKSER, Kenneth, Alan , TEKMEN, Yusuf, Cagatay
发明人： DOCKSER, Kenneth, Alan , TEKMEN, Yusuf, Cagatay
IPC分类号： G06F9/38
CPC分类号： G06F9/3802 , G06F9/3814 , G06F9/382 , G06F9/3836 , G06F9/3877 , G06F9/3885
摘要： Methods and apparatus for processing instructions by elaboration of instructions prior to issuing the instructions for execution are described. An instruction is received at a hybrid instruction queue comprised of a first queue and a second queue. When the second queue has available space, the instruction is elaborated to expand one or more bit fields to reduce decoding complexity when the elaborated instruction is issued, wherein the elaborated instruction is stored in the second queue. When the second queue does not have available space, the instruction is stored in an unelaborated form in a first queue. The first queue is configured as an exemplary in-order queue and the second queue is configured as an exemplary out-of-order queue.
摘要翻译：描述用于在发出用于执行的指令之前通过阐述指令来处理指令的方法和装置。在由第一队列和第二队列组成的混合指令队列中接收指令。当第二队列具有可用空间时，阐述指令以扩展一个或多个比特字段以在发出详细指令时降低解码复杂度，其中详细指令被存储在第二队列中。当第二个队列没有可用空间时，该指令以未预定义的形式存储在第一个队列中。第一队列被配置为示例性的按顺序队列，并且第二队列被配置为示例性的无序队列。

6. 发明申请

WO2007101216A3 FLOATING-POINT PROCESSOR WITH REDUCED POWER REQUIREMENTS FOR SELECTABLE SUBPRECISION 审中-公开
公开(公告)号：WO2007101216A3
公开(公告)日：2007-09-07
申请号：PCT/US2007/062908
申请日：2007-02-27
申请人： QUALCOMM INCORPORATED , DOCKSER, Kenneth Alan
发明人： DOCKSER, Kenneth Alan
IPC分类号： G06F7/57 , G06F7/499
摘要： A method and apparatus for performing a floating-point operation with a floating-point processor having a given precision is disclosed. A subprecision for the floating-point operation on one or more floating-point numbers is selected. The selection of the subprecision results in one or more excess bits for each of the one or more floating-point numbers. Power may be removed from one or more components in the floating-point processor that would otherwise be used to store or process the one or more excess bits, and the floating-point operation is performed with power removed from the one or more components.

7. 发明申请

WO2007085012A3 PRE-SATURATING FIXED-POINT MULTIPLIER 审中-公开
标题翻译：预饱和固定点乘法器
公开(公告)号：WO2007085012A3
公开(公告)日：2008-01-24
申请号：PCT/US2007060816
申请日：2007-01-22
申请人： QUALCOMM INC , DOCKSER KENNETH ALAN , SEXTON BONNIE COLLETT
发明人： DOCKSER KENNETH ALAN , SEXTON BONNIE COLLETT
IPC分类号： G06F7/499 , G06F7/533
CPC分类号： G06F7/49921 , G06F7/5338
摘要： A pre-saturating multiplier inspects the operands to a multiply operation prior to performing any multiplication. If the operands will cause an overflow requiring saturation, the multiplier outputs the saturated value without multiplying the original operands. In one embodiment, parameters derived from the operands are altered such that when the multiply operation is performed on the altered parameters, the multiplier produces the saturated result. This may comprise altering a Booth recoded bit group to select a negative zero instead of a zero as a partial product, and suppressing the addition of the value one to the partial products (thus effectively subtracting the value one). In another embodiment, when the operands that will cause an overflow are detected, the output of the multiplier is forced to a predetermined saturation value.
摘要翻译：预饱和乘法器在执行任何乘法之前检查操作数到乘法运算。如果操作数将导致需要饱和的溢出，则乘法器输出饱和值，而不会将原始操作数相乘。在一个实施例中，改变从操作数导出的参数，使得当对改变的参数执行乘法运算时，乘法器产生饱和结果。这可以包括改变布斯重新编码的位组，以选择负零而不是零作为部分乘积，并且抑制将值1加到部分积（从而有效地减去值1）。在另一个实施例中，当检测到将导致溢出的操作数时，乘法器的输出被强制为预定的饱和值。

8. 发明申请

WO2007133914A1 MODE-BASED MULTIPLY-ADD PROCESSOR FOR DENORMAL OPERANDS 审中-公开
标题翻译：基于模式的多用途加法处理器
公开(公告)号：WO2007133914A1
公开(公告)日：2007-11-22
申请号：PCT/US2007/067649
申请日：2007-04-27
申请人： QUALCOMM INCORPORATED , DOCKSER, Kenneth Alan , LALL, Pathik Sunil
发明人： DOCKSER, Kenneth Alan , LALL, Pathik Sunil
IPC分类号： G06F7/499 , G06F7/487 , G06F7/544
CPC分类号： G06F7/49915 , G06F7/4876 , G06F7/5443 , G06F2207/3884
摘要： In a denormal support mode, the normalization circuit of a floating-point adder is used to normalize or denormalize the output of a floating-point multiplier. Each floating-point multiply instruction is speculatively converted to a multiply-add instruction, with the addend forced to zero. This preserves the value of the product, while normalizing or denormalizing the product using the floating-point adder's normalization circuit. If the operands will not generate an unnormal intermediate product or a denormal final product, the add operation is suppressed, such as by operand-f orwarding. Additionally, each non-fused floating-point multiply-add instruction is replaced with a multiply-add instruction having a zero addend, and a floating-point add instruction having the addend of the original multiply-add instruction is inserted into the instruction stream. If an unnormal intermediate result or a denormal final result will not occur, the addend may be restored to the multiply-add instruction and the add instruction converted to a NOP.
摘要翻译：在非正常支持模式中，浮点加法器的归一化电路用于对浮点乘法器的输出进行归一化或非归一化。每个浮点乘法指令被推测转换为乘法加法指令，加数被强制为零。这样可以保留产品的价值，同时使用浮点加法器的归一化电路对产品进行规范化或非规范化。如果操作数不会产生非正常的中间产品或非正常的最终产品，则加法运算被抑制，例如通过操作数转换。此外，每个非融合浮点乘法指令被具有零加法的加法指令代替，并且具有原始加法指令的加数的浮点加法指令被插入到指令流中。如果不会发生非正常的中间结果或非正常的最终结果，则可以将加数恢复为乘法加法指令，并将加法指令转换为NOP。

9. 发明申请

WO2006124410A3 LATENCY INSENSITIVE FIFO SIGNALING PROTOCOL 审中-公开
标题翻译： LATENCY INSENSITIVE FIFO信号协议
公开(公告)号：WO2006124410A3
公开(公告)日：2007-09-20
申请号：PCT/US2006017899
申请日：2006-05-08
申请人： QUALCOMM INC , DOCKSER KENNETH ALAN , AUGSBURG VICTOR ROBERTS , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , CLANCY ROBERT DOUGLAS , SARTORIUS THOMAS ANDREW
发明人： DOCKSER KENNETH ALAN , AUGSBURG VICTOR ROBERTS , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , CLANCY ROBERT DOUGLAS , SARTORIUS THOMAS ANDREW
IPC分类号： G06F13/38
CPC分类号： G06F13/4059 , G06F5/06 , G06F2205/126
摘要： Data from a source domain (311 ) operating at a first data rate is transferred to a FIFO (319) in another domain (313) operating at a different data rate. The FIFO (319) buffers data before transfer to a sink for further processing or storage. A source side counter (325) tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter (325) decrements in response to a data ready signal from the source domain (311)1 without delay. The counter (325) increments in response to signaling from the sink domain (313) of a read of data off the FIFO (319). Hence, incrementing is subject to the signaling latency between domains. The source (315) may send one more beat of data when the counter (325) indicates the FIFO (319) is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one o more FIFO positions.
摘要翻译：来自以第一数据速率运行的源域（311）的数据被传送到以不同数据速率工作的另一域（313）中的FIFO（319）。 FIFO（319）在传输到宿之前缓冲数据以进一步处理或存储。源侧计数器（325）跟踪FIFO中可用的空间。在所公开的示例中，初始计数器值对应于FIFO深度。计数器（325）响应于来自源域（311）1的数据就绪信号而没有延迟地递减。计数器（325）响应于来自接收器域（313）的从FIFO（319）读取的数据的信令而递增。因此，增量受到域之间的信令等待时间的限制。当计数器（325）指示FIFO（319）已满时，源（315）可以再发送一个数据节拍。数据的最后一次节拍从源头连续发送到指示FIFO位置可用为止; 有效提供一个以上的FIFO位置。

10. 发明申请

WO2006124410A2 LATENCY INSENSITIVE FIFO SIGNALING PROTOCOL 审中-公开
标题翻译： LATENCY INSENSITIVE FIFO信号协议
公开(公告)号：WO2006124410A2
公开(公告)日：2006-11-23
申请号：PCT/US2006/017899
申请日：2006-05-08
申请人： QUALCOMM INCORPORATED , DOCKSER, Kenneth, Alan , AUGSBURG, Victor, Roberts , DIEFFENDERFER, James, Norris , BRIDGES, Jeffrey, Todd , CLANCY, Robert, Douglas , SARTORIUS, Thomas, Andrew
发明人： DOCKSER, Kenneth, Alan , AUGSBURG, Victor, Roberts , DIEFFENDERFER, James, Norris , BRIDGES, Jeffrey, Todd , CLANCY, Robert, Douglas , SARTORIUS, Thomas, Andrew
IPC分类号： G06F13/38
CPC分类号： G06F13/4059 , G06F5/06 , G06F2205/126
摘要： Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further processing or storage. A source side counter tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter decrements in response to a data ready signal from the source domain, without delay. The counter increments in response to signaling from the sink domain of a read of data off the FIFO. Hence, incrementing is subject to the signaling latency between domains. The source may send one more beat of data when the counter indicates the FIFO is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one more FIFO position.
摘要翻译：来自以第一数据速率运行的源域的数据被传送到以不同数据速率操作的另一域中的FIFO。 FIFO在传输到接收器之前缓冲数据以进一步处理或存储。源侧计数器跟踪FIFO中可用的空间。在所公开的示例中，初始计数器值对应于FIFO深度。响应于来自源域的数据就绪信号，计数器无延迟地递减。计数器响应来自接收器域的信令从FIFO的数据读取而递增。因此，增量受到域之间的信令等待时间的限制。当计数器指示FIFO已满时，源可能再发送一次数据。数据的最后一次节拍从源头连续发送到指示FIFO位置可用为止; 有效提供一个FIFO位置。

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